coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Caveh Jalali (Code Review) 17 Nov '20

17 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 ) Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 02:00:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 17 Nov '20

17 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 136: BIT(2) > I think we could make a nice set of #define for this, here's my suggestion: […] Done https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 129: /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= BIT(2); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : } > I think this should go in fw_config.c as well. […] hmmm... can we update struct soc_intel_tigerlake_config from there? i think this needs to happen when called from platform_fsp_silicon_init_params_cb(). https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 34: #define TGL_GPIO_ID_GPP_E22 0x090E0016 : #define TGL_GPIO_ID_GPP_E23 0x090E0017 : > I think we can do a little better here too 😊 […] that's a question for brandon.breitenstein(a)intel.com. i'm not introducing new values here, all of this is based on what we already have in the device trees. -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 6 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Nov 2020 01:59:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 17 Nov '20

17 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#7). Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h 9 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 7 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 17 Nov '20

17 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#6). Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h 9 files changed, 59 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 6 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/volteer2: Turn I2C2 bus freq closer to 400...
by Johnny Li (Code Review) 17 Nov '20

17 Nov '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47558 ) Change subject: mb/google/volteer/variants/volteer2: Turn I2C2 bus freq closer to 400 kHz for WLAN ...................................................................... mb/google/volteer/variants/volteer2: Turn I2C2 bus freq closer to 400 kHz for WLAN The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring the bus frequency closer to 400 kHz. BUG=b:153588771 TEST=Verified that I2C2 frequency is 380 kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176 --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47558/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index e4da0e6..4678d26 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -36,6 +36,13 @@ }, .i2c[2] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, .i2c[3] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/47558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96fa5ed586de41324733ac7537b6bd73f39fc176 Gerrit-Change-Number: 47558 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/bobba: Add G2Touch touchscreen support
by Sheng-Liang Pan (Code Review) 17 Nov '20

17 Nov '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46808 ) Change subject: mb/google/octopus/variants/bobba: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/bobba: Add G2Touch touchscreen support Add G2Touch touchscreen support for bobba. BUG=b:171636614 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4 --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46808/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 20c376a..c3a63c7 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -210,6 +210,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4 Gerrit-Change-Number: 46808 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/tiogapass: use ACPI to control GPIO [WIP]
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39987 ) Change subject: mb/ocp/tiogapass: use ACPI to control GPIO [WIP] ...................................................................... mb/ocp/tiogapass: use ACPI to control GPIO [WIP] Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/39987/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 9d33865..59ee7f8 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -35,5 +35,7 @@ // Xeon-SP ACPI tables Scope (\_SB) { #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Gerrit-Change-Number: 39987 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/ocp/deltalake: use ACPI to control GPIO
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45768 ) Change subject: [WIP] mb/ocp/deltalake: use ACPI to control GPIO ...................................................................... [WIP] mb/ocp/deltalake: use ACPI to control GPIO Change-Id: Ie5ec6bbc01092b743dea62aaf9dfc6dc3b3c0059 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/deltalake/dsdt.asl 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45768/1 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c74b5fe..dd1fed2 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -20,4 +20,12 @@ // CPX-SP ACPI tables #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ec6bbc01092b743dea62aaf9dfc6dc3b3c0059 Gerrit-Change-Number: 45768 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/intel/cedarisland: use ACPI to control GPIO
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45897 ) Change subject: [WIP] mb/intel/cedarisland: use ACPI to control GPIO ...................................................................... [WIP] mb/intel/cedarisland: use ACPI to control GPIO Change-Id: Ic3d6c3d5e64a640875aaff6a3b58b778080167bf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/cedarisland_crb/dsdt.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45897/1 diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 407ee37..61e40ab 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -23,7 +23,8 @@ { #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl> - + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> } Device (UNC0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6c3d5e64a640875aaff6a3b58b778080167bf Gerrit-Change-Number: 45897 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy: Add late_gpio support
by Tim Wawrzynczak (Code Review) 16 Nov '20

16 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46619 ) Change subject: mb/google/poppy: Add late_gpio support ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46619/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46619/1//COMMIT_MSG@18 PS1, Line 18: TEST=tested with patch stack to verify that we successfully reset the I assume you'll want to cherry-pick this into firmware-poppy-10431.B ? -- To view, visit https://review.coreboot.org/c/coreboot/+/46619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I847f90275740ca825e4c93e6b8d5650143228476 Gerrit-Change-Number: 46619 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 21:42:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2020