coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common/block/cse: Add functions to support setting DAM state
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/46882 ) Change subject: soc/intel/common/block/cse: Add functions to support setting DAM state ...................................................................... soc/intel/common/block/cse: Add functions to support setting DAM state This patch adds the following helper functions, get_dam_state : To get DAM state. set_dam_state : To set DAM state. disable_dam : To disable DAM. To communicate with CSE, BIOS uses read_file_ex, set_file_ex and commit_file commands over MEI messages. After passing DAM setting to CSE, BIOS needs to initiate a global reset. BUG=b:169626786 BRANCH=None TEST=Build, boot drawlat and check DAM state, set DAM state. Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46882/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Gerrit-Change-Number: 46882 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/46880 ) Change subject: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib ...................................................................... soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib This patch adds the following, 1. MCHI MCA group command ID. 2. Read File Ex command Id and heci_read_file_ex helper function to read contents of a file. 3. Set File Ex command Id and heci_set_file_ex helper function to set file's data for write. 4. Commit Files command Id and heci_commit_files helper function to commit files previously set by set file command. BUG=b:169626786 BRANCH=None TEST=Build and boot drawcia. Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46880/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Gerrit-Change-Number: 46880 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has uploaded a new patch set (#6) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/46881 ) Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address Modify heci_send_receive function to add support to send and receive messages to MCHI Client address. BUG=b:169626786 BRANCH=None TEST=Verify send and receive reply HECI message on drawlat. Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46881/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ACPI: Define acpi_get_preferred_pm_profile()
by Felix Held (Code Review) 17 Nov '20

17 Nov '20

Hello Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47666 to review the following change. Change subject: ACPI: Define acpi_get_preferred_pm_profile() ...................................................................... ACPI: Define acpi_get_preferred_pm_profile() Change-Id: Id90737cc93261290b7227e9a3249c2b7df79ca3d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/acpi.c M src/arch/x86/Makefile.inc A src/arch/x86/acpi_pm.c M src/include/acpi/acpi.h 4 files changed, 26 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47666/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 259813b..f08a6e3 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1251,14 +1251,7 @@ /* should be 0 ACPI 3.0 */ fadt->reserved = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) - fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) - fadt->preferred_pm_profile = PM_TABLET; - else - fadt->preferred_pm_profile = PM_DESKTOP; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); arch_fill_fadt(fadt); diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a5c3309..8470989 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -240,6 +240,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c diff --git a/src/arch/x86/acpi_pm.c b/src/arch/x86/acpi_pm.c new file mode 100644 index 0000000..59ea29d --- /dev/null +++ b/src/arch/x86/acpi_pm.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <smbios.h> + +/* Default mapping to ACPI FADT preferred_pm_profile field. */ +uint8_t acpi_get_preferred_pm_profile(void) +{ + switch (smbios_mainboard_enclosure_type()) { + case SMBIOS_ENCLOSURE_LAPTOP: + case SMBIOS_ENCLOSURE_CONVERTIBLE: + return PM_MOBILE; + case SMBIOS_ENCLOSURE_DETACHABLE: + case SMBIOS_ENCLOSURE_TABLET: + return PM_TABLET; + case SMBIOS_ENCLOSURE_DESKTOP: + return PM_DESKTOP; + case SMBIOS_ENCLOSURE_UNKNOWN: + default: + return PM_UNSPECIFIED; + } +} diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 78740fb..71dcea8 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1044,6 +1044,8 @@ } #endif +uint8_t acpi_get_preferred_pm_profile(void); + /* Returns ACPI_Sx values. */ int acpi_get_sleep_type(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/47666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id90737cc93261290b7227e9a3249c2b7df79ca3d Gerrit-Change-Number: 47666 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Mariusz Szafrański (Code Review) 17 Nov '20

17 Nov '20

Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: Code-Review-1 Denverton-NS maintainers list update is planned this week. I`ll update it when it will be confirmed and let you know. -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 13:11:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Kyösti Mälkki (Code Review) 17 Nov '20

17 Nov '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: Dimitri, do you have plans wrt. upstreaming your design, for which coreboot support was forked from intel/harcuvar? -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 12:16:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Angel Pons (Code Review) 17 Nov '20

17 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: > Patch Set 1: Code-Review+1 > > What is the downside of this announcement? It directly says, that if a maintainer steps up, and hardware can be tested, that it will be left in the tree. So, please include it. It's currently full of unresolved comments and collides with other patches. I don't really mind the change per se. -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 12:06:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Paul Menzel (Code Review) 17 Nov '20

17 Nov '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: Code-Review+1 What is the downside of this announcement? It directly says, that if a maintainer steps up, and hardware can be tested, that it will be left in the tree. So, please include it. -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 11:40:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45540 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "Die()" needs <console/console.h>. Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/poppy/variants/nami/memory.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_i2c.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45540/1 diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 3e482a9..6faca2b 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <gpio.h> #include <variant/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 46499f4..bea9cd8 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <console/console.h> #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 3dbe3e6..9614b4e 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> +#include <console/console.h> #include <string.h> #include <soc/qupv3_config.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index b80c3df..c9adba4 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/i2c_simple.h> #include <gpio.h> #include <inttypes.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Gerrit-Change-Number: 45540 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45539 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/aspeed/common/ast_post.c M src/lib/asan.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/hatch/romstage_spd_smbus.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/volteer/romstage.c M src/security/vboot/vboot_logic.c M src/soc/amd/picasso/reset.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/intel/ibexpeak/early_pch.c 19 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45539/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index b5f794b..bf974ff 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -2,6 +2,8 @@ /* * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ + +#include <console/console.h> #include <edid.h> #include <device/pci_def.h> diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index c909182..68ecca8 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -2,6 +2,7 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 +#include <console/console.h> #include <delay.h> #include "ast_drv.h" diff --git a/src/lib/asan.c b/src/lib/asan.c index 6de0de1..cf91111 100644 --- a/src/lib/asan.c +++ b/src/lib/asan.c @@ -8,6 +8,7 @@ * */ +#include <console/console.h> #include <symbols.h> #include <assert.h> #include <arch/symbols.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index fcf50a9..1af2e02 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <boot/coreboot_tables.h> +#include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> #include "../qemu-i440fx/fw_cfg.h" diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index d21e867..e697379 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 3b247e9..d641405 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <chip.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci_ids.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 564c18c..cf9344e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 57f3a3b..54d8b0d 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootmode.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8893785..375bb0c 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <fsp/soc_binding.h> #include <fw_config.h> diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c4c3b4b..43405bc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -2,6 +2,7 @@ #include <arch/exception.h> #include <assert.h> +#include <console/console.h> #include <bootmode.h> #include <fmap.h> #include <security/tpm/tspi/crtm.h> diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 902538ff..7a0074c 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <console/console.h> #include <reset.h> #include <soc/pci_devs.h> #include <soc/reset.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 15874c0..f3e47e5 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/sort.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f..16f7856 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <device/pci.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb..0316e1e 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <assert.h> +#include <console/console.h> #include <post.h> #include <device/pci.h> #include <soc/acpi.h> diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 62aa4d1..e9665c3 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -3,6 +3,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <console/console.h> #include <device/pci_def.h> #include <hob_iiouds.h> diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 919735d..8763a9d 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index cac590c..6750c3e 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/qcom_qup_se.h> struct qup qup[12] = { diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index d086a27..23914bb 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <lib.h> #include <soc/clock.h> #include <soc/gpio.h> diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac009..122c8e4 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Gerrit-Change-Number: 45539 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020