Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47646 )
Change subject: Update to use upstream version 4.3.12
......................................................................
Update to use upstream version 4.3.12
The EM100Pro/EM100Pro-G2 Software package was updated by Dediprog
to 4.3.12 on 2020-11-13 13:41:05.
Upstream 4.3.12 is using the original download slot again, adjust
the makechips.sh script.
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Change-Id: I310f34d493569d7b887873a277e22cda325d8049
---
M makechips.sh
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/em100 refs/changes/46/47646/1
diff --git a/makechips.sh b/makechips.sh
index 8a2d901..b4c43d0 100755
--- a/makechips.sh
+++ b/makechips.sh
@@ -12,8 +12,7 @@
# GNU General Public License for more details.
#
-URL="https://www.dediprog.com/download/save/1145.msi"
-VURL="https://www.dediprog.com/download?productCategory=SPI+Flash+Solution&produc…"
+URL="https://www.dediprog.com/download/save/78.msi"
if ! which curl > /dev/null; then
echo "Install curl to run this script."
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Julien Viard de Galbert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 )
Change subject: Documentation: Update release notes for Denverton NS deprecation
......................................................................
Patch Set 1:
I can only help maintaining it as a hobbyist, my day job is no longer to work on that port.
Also it seams that denverton EDS is no longer public, the link on Intel returns only the spec update, so I no longer have access to the full specifications.
I can update code and patches from time to time, test it on one 'scaleway/tagada' board, but without help from Intel, it will be hard to maintain the port.
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Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28101 )
Change subject: Makefile: Write .xcompile to $(obj)
......................................................................
Patch Set 10: Code-Review+1
This change is ready for review.
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Julien Viard de Galbert has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/24929 )
Change subject: [DONOTSUBMIT] for testing only: use both gpio conf function and compare logs ;)
......................................................................
Abandoned
This was for testing only and the related patches are merged.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 )
Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in…
File src/soc/intel/tigerlake/include/soc/early_tcss.h:
https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in…
PS1, Line 103: 0x09000000
> for the GPIO pins this is how FSP has them defined and what it is expecting. see FspsUpd. […]
I see, it's a chipset-specific constant, thanks Brandon!
Caveh, how about a `#define TGL_LP_GPIO_ID 0x09000000` instead?
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 )
Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47501/7//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47501/7//COMMIT_MSG@7
PS7, Line 7: Config for passive USB-C DB on C1
Plesae make it a statement by adding a verb (in imperative mood):
> Add config for passive USB-C DB on C1
> Integrate passive USB-C DB on C1
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Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 )
Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in…
File src/soc/intel/tigerlake/include/soc/early_tcss.h:
https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in…
PS1, Line 103: 0x09000000
> @brandon.breitenstein@intel.com […]
for the GPIO pins this is how FSP has them defined and what it is expecting. see FspsUpd.h and reference the GpioPinsTGLH.h file in FSP
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Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45010
to look at the new patch set (#8).
Change subject: soc/intel/skylake: Use correct NHLT_PDM_DEV definition
......................................................................
soc/intel/skylake: Use correct NHLT_PDM_DEV definition
According to the NHLT specification[1], PDM_DEV is defined as "1" on
Kabylake based platforms. coreboot currently sets it to "0" on
all platforms. Add an entry to the enum and use it to define
NHLT_PDM_DEV for Kabylake.
"Device Type" will resume from "2" on all platforms, but entries are
currently reserved.
Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array
DMIC, on Windows 10.
1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf
Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/include/nhlt.h
M src/soc/intel/skylake/nhlt/dmic.c
2 files changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45010/8
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