coreboot-gerrit November 2020

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Change in coreboot[master]: vboot: stop implementing VbExDisplayScreen
by Joel Kitching (Code Review) 18 Nov '20

18 Nov '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47233 ) Change subject: vboot: stop implementing VbExDisplayScreen ...................................................................... vboot: stop implementing VbExDisplayScreen This function is no longer required to be implemented since EC/AUXFW sync was decoupled from vboot UI. (See CL:2087016.) BUG=chromium:2117776 TEST=Compile locally BRANCH=none Signed-off-by: Joel Kitching <kitching(a)google.com> Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2 --- M src/security/vboot/ec_sync.c 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47233/1 diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 97b8ed9..1fd7e75 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -12,7 +12,6 @@ #include <timer.h> #include <timestamp.h> #include <vb2_api.h> -#include <vboot_api.h> /* for VbExDisplayScreen() and VbScreenData */ #define _EC_FILENAME(select, suffix) \ (select == VB_SELECT_FIRMWARE_READONLY ? "ecro" suffix : "ecrw" suffix) @@ -402,21 +401,6 @@ ***********************************************************************/ /* - * Unsupported. - * - * coreboot does not support the graphics initialization needed to - * display the vboot "wait" screens, etc., because the use case for - * supporting software sync early in the boot flow is to be able to - * quickly update the EC and/or sysjump to RW earlier so that USB-PD - * power (> 15 W) can be negotiated for earlier. - */ -vb2_error_t VbExDisplayScreen(uint32_t screen_type, uint32_t locale, - const VbScreenData *data) -{ - return VB2_ERROR_UNKNOWN; -} - -/* * Write opaque data into NV storage region. */ vb2_error_t vb2ex_commit_data(struct vb2_context *ctx) -- To view, visit https://review.coreboot.org/c/coreboot/+/47233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43e8160a4766a38c4fa14bcf4495fc719fbcd6c2 Gerrit-Change-Number: 47233 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Caveh Jalali (Code Review) 18 Nov '20

18 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47653 to look at the new patch set (#2). Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... soc/intel/tigerlake: Define TCSS AUX pin bias control This adds definitions for controlling the TCSS AUX pins biasing and port orientation. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations in combination with following patches Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/tigerlake/include/soc/early_tcss.h 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47653/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary
by Jamie Ryu (Code Review) 18 Nov '20

18 Nov '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46431 ) Change subject: [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary ...................................................................... [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary BUG=b:166982406 TEST=build with cse rw binary and verify volteer boot time is close to 1 sec. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46431/1 diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd old mode 100644 new mode 100755 index 07a5464..246561d --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -10,13 +10,15 @@ RW_LEGACY(CBFS)@0x0 0xb00000 RW_SECTION_A@0xb00000 0x5e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x5cffc0 - RW_FWID_A@0x5dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x34ffc0 + RW_FWID_A@0x35ffc0 0x40 + FW_MAIN_A_EXTN(CBFS)@0x360000 0x280000 } RW_SECTION_B@0x10e0000 0x5e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x5cffc0 - RW_FWID_B@0x5dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x34ffc0 + RW_FWID_B@0x35ffc0 0x40 + FW_MAIN_B_EXTN(CBFS)@0x360000 0x280000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/46431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea Gerrit-Change-Number: 46431 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/common: Boot time optimization
by Sridhar Siricilla (Code Review) 18 Nov '20

18 Nov '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46312 ) Change subject: soc/intel/common: Boot time optimization ...................................................................... soc/intel/common: Boot time optimization Th CSE RW blob which will be used by coreboot to update CSE RW partition, is packed part of FW_MAIN_A and FW_MAIN_B. This increase the size of FW_MAIN_A and FW_MAIN_B. So, accordingly loads and hash calculation of FW_MAIN_A (or FW_MAIN_B) increases during verstage. The boot time impact is around 300ms. The patch addresses boot time by pulling CSE RW blob outside of FW_MAIN_A/B. So, it creates new FMAP region within RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions as a CBFS file. Changes: 1. Makefile changes to accommodate CSE RW blob part of FW_MAIN_A_EXTN/ FW_MAIN_B_EXTN and add RW blob metadata file part of FW_MAIN_A/B. 2. Kconfig change to define CBFS name and default file name for RW blob metadata. 3. CSE Lite driver BUG=b:169077783 TEST=verified on hatch. Yet to verify on JSL/TGL platforms. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 227 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46312/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..0172fc2 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -37,3 +37,15 @@ default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS entry name for CSE RW blob" + default "me_rw_metadata" + help + CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_METADATA_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..9543156 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -4,11 +4,21 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c + ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") -CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B -cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-type := raw +CSE_LITE_RW = $(call strip_quotes, $(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW) = FW_MAIN_A_EXTN,FW_MAIN_B_EXTN +cbfs-files-y += $(CSE_LITE_RW) +$(CSE_LITE_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_RW)-name := $(CSE_LITE_RW) +$(CSE_LITE_RW)-type := raw +endif + +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE),"") +CSE_LITE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE)) +$(CSE_LITE_RW_METADATA)-name := $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f..5b50828 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -12,6 +12,11 @@ #include <vb2_api.h> #include <soc/intel/common/reset.h> + +#define FMAP_FW_MAIN_A_EXTN_NAME "FW_MAIN_A_EXTN" + +#define FMAP_FW_MAIN_B_EXTN_NAME "FW_MAIN_B_EXTN" + /* CSE RW version size reserved in the CSE CBFS RW binary */ #define CSE_RW_VERSION_SZ 16 @@ -64,7 +69,13 @@ CSE_LITE_SKU_COMMUNICATION_ERROR = 6, /* Fails to wipe CSE runtime data */ - CSE_LITE_SKU_DATA_WIPE_ERROR = 7 + CSE_LITE_SKU_DATA_WIPE_ERROR = 7, + + /* CSE RW is not found */ + CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, + + /* CSE CBFS RW SHA-256 mismatch with the provided SHA */ + CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9 }; /* @@ -157,6 +168,43 @@ struct cse_bp_info bp_info; } __packed; +/* CSE CBFS RW metadata */ +struct cse_cbfs_rw_info { + + /* This struct version */ + uint8_t version; + + /* CSE CBFS RW version */ + struct fw_version fw_ver; + + /* Ifwi build version */ + uint8_t ifwi_build_version; + + /* Indicate CSE CBFS RW is compressed or not */ + uint8_t compressed; + + /* SHA-256 of CSE CBFS RW */ + uint8_t hash[VB2_SHA256_DIGEST_SIZE]; + + uint8_t reserved[5]; +}; + +/* CSE Boot Partition Descriptor Table Header */ +struct cse_bpdt { + + /* Signature:0x000055AA is expected for a valid BP */ + uint32_t signature; + + /* reserved field */ + uint8_t reserved[8]; + + /* ifwi build version */ + uint32_t ifwi_build_ver; + + /* FIT tool version */ + struct fw_version fit_tool_ver; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -419,11 +467,38 @@ return true; } +static bool cse_get_cbfs_rw(struct region_device *rdev) +{ + const char *fmap_fw_main_extn; + uint32_t cbfs_type = CBFS_TYPE_RAW; + static struct cbfsf fh; + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + return false; + + if (vboot_is_firmware_slot_a(ctx)) + fmap_fw_main_extn = FMAP_FW_MAIN_A_EXTN_NAME; + else + fmap_fw_main_extn = FMAP_FW_MAIN_B_EXTN_NAME; + + if (cbfs_locate_file_in_region(&fh, fmap_fw_main_extn, + CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, &cbfs_type)) { + printk(BIOS_ERR, "cse_lite: Failed to locate %s in the %s", + CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, fmap_fw_main_extn); + + return false; + } + + cbfs_file_data(rdev, &fh); + + return true; +} + static bool cse_get_cbfs_rdev(struct region_device *source_rdev) { struct cbfsf file_desc; - if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, NULL) < 0) return false; cbfs_file_data(source_rdev, &file_desc); @@ -503,15 +578,32 @@ return true; } -static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, - void *cse_cbfs_rw_ver) +static bool cse_get_cbfs_rw_metadata(const struct region_device *source_info_rdev, + struct cse_cbfs_rw_info *source_info) { - if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) - != sizeof(struct fw_version)) { - printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); + if (rdev_readat(source_info_rdev, (void *) source_info, 0, + sizeof(struct cse_cbfs_rw_info)) != sizeof(struct cse_cbfs_rw_info)) { + printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW blob metadata\n"); return false; } + + printk(BIOS_SPEW, "cse_lite: version: %d\n", source_info->version); + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); + printk(BIOS_SPEW, "cse_lite: IFWI build version: 0x%x\n", + source_info->ifwi_build_version); + printk(BIOS_SPEW, "cse_lite: compressed blob: 0x%x\n", + source_info->compressed); + printk(BIOS_SPEW, "cse_lite: RW blob hash: "); + + for (uint8_t i = 0; i < 32; i++) + printk(BIOS_SPEW, "%x", source_info->hash[i]); + + printk(BIOS_SPEW, "\n"); return true; } @@ -522,30 +614,27 @@ * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - struct fw_version cse_cbfs_rw_ver; const struct fw_version *cse_rw_ver; - if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) - return false; printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - cse_cbfs_rw_ver.major, - cse_cbfs_rw_ver.minor, - cse_cbfs_rw_ver.hotfix, - cse_cbfs_rw_ver.build); + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); cse_rw_ver = cse_get_rw_version(cse_bp_info); - if (cse_cbfs_rw_ver.major != cse_rw_ver->major) - return cse_cbfs_rw_ver.major - cse_rw_ver->major; - else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) - return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; - else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) - return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + if (source_info->fw_ver.major != cse_rw_ver->major) + return source_info->fw_ver.major - cse_rw_ver->major; + else if (source_info->fw_ver.minor != cse_rw_ver->minor) + return source_info->fw_ver.minor - cse_rw_ver->minor; + else if (source_info->fw_ver.hotfix != cse_rw_ver->hotfix) + return source_info->fw_ver.hotfix - cse_rw_ver->hotfix; else - return cse_cbfs_rw_ver.build - cse_rw_ver->build; + return source_info->fw_ver.build - cse_rw_ver->build; } /* Check if CSE RW data partition is valid or not */ @@ -557,6 +646,21 @@ return rw_bp->status != BP_STATUS_DATA_FAILURE; } +static int cse_is_ifwi_build_version_latest(const struct cse_cbfs_rw_info *source_info, + const struct region_device *target_dev) +{ + uint32_t ifwi_build_ver; + uint8_t ifwi_build_ver_offset = offsetof(struct cse_bpdt, ifwi_build_ver); + + if (rdev_readat(target_dev, &ifwi_build_ver, ifwi_build_ver_offset, + sizeof(ifwi_build_ver)) != sizeof(ifwi_build_ver)) { + printk(BIOS_ERR, "cse_lite: Failed to read OEM Version CSE RW partition\n"); + return false; + } + + return (ifwi_build_ver == source_info->ifwi_build_version); +} + /* * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE * otherwise false if any operation fails. @@ -587,8 +691,8 @@ return true; } -static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, - size_t size) +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, + size_t offset, size_t size) { if (rdev_writeat(target_rdev, buf, offset, size) < 0) { printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); @@ -599,36 +703,33 @@ } static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return !cse_check_version_mismatch(cse_bp_info, source_rdev); + return !cse_check_version_mismatch(cse_bp_info, source_info); } static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; + return cse_check_version_mismatch(cse_bp_info, source_info) < 0; } static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_rdev)); + !cse_is_rw_version_latest(cse_bp_info, source_info) || + !cse_is_ifwi_build_version_latest(source_info, target_rdev)); } static bool cse_write_rw_region(const struct region_device *target_rdev, - const struct region_device *source_rdev) + const void *cse_cbfs_rw, const size_t cse_cbfs_rw_sz) { - void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, - region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); - /* Points to CSE CBFS RW image after boot partition signature */ uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; /* Size of CSE CBFS RW image without boot partition signature */ - uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - - (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + uint32_t cse_cbfs_rw_wo_sign_sz = cse_cbfs_rw_sz - CSE_RW_SIGN_SIZE; /* Update except CSE RW signature */ if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, @@ -639,21 +740,19 @@ if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) goto exit_rw_update; - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); return true; exit_rw_update: - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); return false; } -static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, const void *cse_cbfs_rw, + const size_t cse_blob_sz, struct region_device *target_rdev) { if (!cse_erase_rw_region(target_rdev)) return false; - if (!cse_write_rw_region(target_rdev, source_rdev)) + if (!cse_write_rw_region(target_rdev, cse_cbfs_rw, cse_blob_sz)) return false; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); @@ -661,7 +760,7 @@ } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { /* * To set CSE's operation mode to HMRFPO mode: @@ -671,7 +770,7 @@ if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + if (cse_is_downgrade_instance(cse_bp_info, source_info) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); return false; @@ -680,20 +779,54 @@ return cse_hmrfpo_enable(); } -static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +/* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ +static uint8_t cse_verify_rw_blob_sha256(const uint8_t *expected_rw_blob_sha, + const void *rw_blob, const size_t rw_blob_sz) + { - if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) + uint8_t rw_comp_sha[VB2_SHA256_DIGEST_SIZE]; + + if (!vb2_digest_buffer(rw_blob, rw_blob_sz, VB2_HASH_SHA256, rw_comp_sha, + VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: CSE RW blob SHA-256 calculation has failed\n"); + return false; + } + + if (!memcmp(expected_rw_blob_sha, rw_comp_sha, VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: Computed SHA is not matching with the given SHA\n"); + return false; + } + + return true; +} + +static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) +{ + + struct region_device source_rdev; + + if (!cse_get_cbfs_rw(&source_rdev)) + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; + + void *cse_cbfs_rw = rdev_mmap(&source_rdev, 0, region_device_sz(&source_rdev)); + + if (cse_verify_rw_blob_sha256(source_info->hash, cse_cbfs_rw, + region_device_sz(&source_rdev))) + return CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH; + + if (!cse_prep_for_rw_update(cse_bp_info, source_info)) return CSE_LITE_SKU_COMMUNICATION_ERROR; - if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) + if (!cse_update_rw(cse_bp_info, cse_cbfs_rw, region_device_sz(&source_rdev), + target_rdev)) return CSE_LITE_SKU_FW_UPDATE_ERROR; return 0; } static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct region_device *source_info_rdev) { struct region_device target_rdev; @@ -702,9 +835,17 @@ return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + struct cse_cbfs_rw_info source_info; + + /* Read CSE RW blob metadata */ + if (!cse_get_cbfs_rw_metadata(source_info_rdev, &source_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE RW blob metadata\n"); + return CSE_LITE_SKU_UNSPECIFIED; + } + + if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -736,11 +877,15 @@ if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); - /* If RW blob is present in CBFS, then trigger CSE firmware update */ + /* + * If RW blob metadata is present in CBFS, then trigger CSE firmware update. + * The driver triggers if RW blob metadata is present in the CBFS and RW blob is not + * available. + */ uint8_t rv; - struct region_device source_rdev; - if (cse_get_cbfs_rdev(&source_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); + struct region_device source_info_rdev; + if (cse_get_cbfs_rdev(&source_info_rdev)) { + rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev); if (rv) cse_trigger_recovery(rv); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 Gerrit-Change-Number: 46312 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

8 36

Change in coreboot[master]: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
by V Sowmya (Code Review) 18 Nov '20

18 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47557 ) Change subject: mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update ...................................................................... mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update This patch modifies flash layout to add ME_RW_A/B to add the CSE RW blob and also enable the CSE RW update feature for JSLRVP BUG=b:169077783 TEST= Built for jslrvp. Verified that CSE RW and metadata files are included in cbfs. Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47557/1 diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 1125a9b..01b9ab7 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -21,6 +21,7 @@ select SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_RW_UPDATE config MAINBOARD_DIR string diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 05f4592..57be7f1 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -7,13 +7,15 @@ SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x12ffc0 + RW_FWID_A@0x13ffc0 0x40 + ME_RW_A(CBFS)@0x140000 0x190000 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x12ffc0 + RW_FWID_B@0x13ffc0 0x40 + ME_RW_B(CBFS)@0x140000 0x190000 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/47557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d Gerrit-Change-Number: 47557 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/google/dedede: Modify flash layout to add CSE_RW_A/B regions
by V Sowmya (Code Review) 18 Nov '20

18 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47439 ) Change subject: mb/google/dedede: Modify flash layout to add CSE_RW_A/B regions ...................................................................... mb/google/dedede: Modify flash layout to add CSE_RW_A/B regions Existing implemenation adds the CSE RW update binary to FW_MAIN_A/B regions and this has significant impact on boot time due to the increase in the size of these regions leading to higher loading and hashing time. This patch modifies flash layout to add new CSE_RW_A/B fmap regions in the RW_SECTION_A/B. BUG=b:169077783 TEST= Built for dedede. Verified that CSE RW binary is added to the CSE_RW_A/B fmap region. Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd M src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd 2 files changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47439/1 diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index 0e21c4c..ec458d0 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -7,13 +7,15 @@ RW_LEGACY(CBFS)@0x0 0x100000 RW_SECTION_A@0x100000 0x3a4800 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x3a27c0 - RW_FWID_A@0x3a47c0 0x40 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + CSE_RW_A(CBFS)@0x214800 0x190000 } RW_SECTION_B@0x4a4800 0x3a4800 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x3a27c0 - RW_FWID_B@0x3a47c0 0x40 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + CSE_RW_B(CBFS)@0x214800 0x190000 } RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd index 60ea3de..47eb446 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd @@ -10,13 +10,15 @@ RW_LEGACY(CBFS)@0x0 0xf00000 RW_SECTION_A@0xf00000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x23ffc0 + RW_FWID_A@0x24ffc0 0x40 + CSE_RW_A(CBFS)@0x250000 0x190000 } RW_SECTION_B@0x12e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x23ffc0 + RW_FWID_B@0x24ffc0 0x40 + CSE_RW_B(CBFS)@0x250000 0x190000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/47439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992 Gerrit-Change-Number: 47439 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B
by V Sowmya (Code Review) 18 Nov '20

18 Nov '20

Hello Maulik V Vaghela, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47431 to review the following change. Change subject: soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B ...................................................................... soc/intel/common: Generate the CSE RW metadata and add to FW_MAIN_A/B In the existing implementation CSE RW metadata file is generated by scripts and to avoid incompitable issues between coreboot and the scripts this patch adds the follwing changes, * Move the metadata generation to the coreboot makefile. * Add CBFS component type struct to create a metadata file during the compile time. * Extract the CSE RW version from SOC_INTEL_CSE_RW_VERSION config and update the major, minor, hotfix and build versions using the compile time flags. * Compute the hash of CSE RW binary in hex format using the openssl and use the HASH_BYTEARRAY macro to convert the 64 character hex values into the array. * Add the cse_rw.metadata cbfs file to FW_MAIN_A and FW_MAIN_B regions. BUG=b:169077783 TEST= Built for dedede. Verify that metadata file was generated and added to the FW_MAIN_A/B. Extracted it using cbfstool and verfied that metadata was generated properly. Change-Id: I412581400a9606fa17cf4398faffda923f07b320 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/cse/cse_rw_metadata.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 83 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47431/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 9d781f9..0cac75c 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -34,6 +34,13 @@ help CBFS entry name for Intel CSE CBFS RW blob +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS name for CSE RW metadata file" + depends on SOC_INTEL_CSE_LITE_SKU + default "cse_rw.metadata" + help + CBFS name for Intel CSE CBFS RW metadata file + config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" depends on SOC_INTEL_CSE_LITE_SKU diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..bb42b1d 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -12,3 +12,28 @@ $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw endif + +# Extract the CSE RW firmware version and update the cse_rw_metadata structure +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") +CSE_RW_VERSION:=$(subst ., ,$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))) +MAJOR = $(word 1, $(CSE_RW_VERSION)) +MINOR = $(word 2, $(CSE_RW_VERSION)) +HOTFIX = $(word 3, $(CSE_RW_VERSION)) +BUILD = $(word 4, $(CSE_RW_VERSION)) +CPPFLAGS_common += -DCSE_RW_MAJOR=$(MAJOR) -DCSE_RW_MINOR=$(MINOR) -DCSE_RW_HOTFIX=$(HOTFIX) -DCSE_RW_BUILD=$(BUILD) +endif + +# Compute the hash of the CSE RW binary and update the cse_rw_metadata structure +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") +CSE_RW_PATH := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +HASH := $(shell openssl dgst -sha256 -hex $(CSE_RW_PATH) | cut -d " " -f2 | fold -w2 | paste -sd',' -) +CPPFLAGS_common += -DCSE_RW_SHA256=$(HASH) +endif + +# Add the CSE RW metadata file to FW_MAIN_A/B +CSE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_RW_METADATA) +$(CSE_RW_METADATA)-file := cse_rw_metadata.c:struct +$(CSE_RW_METADATA)-name := $(CSE_RW_METADATA) +$(CSE_RW_METADATA)-type := raw diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f..11efec1 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -110,14 +110,6 @@ BP_INFO_READ_ONLY_CFG = 1 << 2, }; -/* Boot Partition FW Version */ -struct fw_version { - uint16_t major; - uint16_t minor; - uint16_t hotfix; - uint16_t build; -} __packed; - /* CSE boot partition entry info */ struct cse_bp_entry { /* Boot partition version */ diff --git a/src/soc/intel/common/block/cse/cse_rw_metadata.c b/src/soc/intel/common/block/cse/cse_rw_metadata.c new file mode 100644 index 0000000..c744a33 --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_rw_metadata.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/cse.h> + +#define HASH_TO_ARRAY(x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15, x16,\ + x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30,\ + x31, x32) { 0x##x1, 0x##x2, 0x##x3, 0x##x4, 0x##x5, 0x##x6, 0x##x7,\ + 0x##x8, 0x##x9, 0x##x10, 0x##x11, 0x##x12, 0x##x13, 0x##x14, 0x##x15,\ + 0x##x16, 0x##x17, 0x##x18, 0x##x19, 0x##x20, 0x##x21, 0x##x22, 0x##x23,\ + 0x##x24, 0x##x25, 0x##x26, 0x##x27, 0x##x28, 0x##x29, 0x##x30, 0x##x31,\ + 0x##x32 } +#define HASH_BYTEARRAY(...) HASH_TO_ARRAY(__VA_ARGS__) + +/* This structure contains the CSE RW version and hash details which are filled during the + * compile time. + * Makefile will extract the following details and updates the structure variable via the + * compile time flags. + * CSE RW version: Extract the version string from the SOC_INTEL_CSE_RW_VERSION config and + * assign the major, minor, hotfix and build versions. + * CSE RW hash: Compute the hash of CSE RW binary in hex format using the openssl and use the + * HASH_BYTEARRAY macro to convert the 64 character hex values into the array. + */ +struct cse_rw_metadata metadata = { + .version = { + .major = CSE_RW_MAJOR, + .minor = CSE_RW_MINOR, + .build = CSE_RW_BUILD, + .hotfix = CSE_RW_HOTFIX, + }, + .sha256 = HASH_BYTEARRAY(CSE_RW_SHA256), +}; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f554933..c9aaf31 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -42,6 +42,8 @@ #define ME_HFS3_FW_SKU_CORPORATE 0x3 #define ME_HFS3_FW_SKU_LITE 0x5 +#define SHA256_DIGEST_SIZE 32 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40, @@ -61,6 +63,24 @@ uint8_t result; } __packed; +/* CSE FW Version */ +struct fw_version { + uint16_t major; + uint16_t minor; + uint16_t hotfix; + uint16_t build; +} __packed; + +/* + * CSE RW metadata structure + * fw_version - CSE RW firmware version + * sha256 - Hash of the CSE RW binary. + */ +struct cse_rw_metadata { + struct fw_version version; + uint8_t sha256[SHA256_DIGEST_SIZE]; +}; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412581400a9606fa17cf4398faffda923f07b320 Gerrit-Change-Number: 47431 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: soc/intel/common: Add Kconfig to enable the CSE FW Update feature
by V Sowmya (Code Review) 18 Nov '20

18 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47523 ) Change subject: soc/intel/common: Add Kconfig to enable the CSE FW Update feature ...................................................................... soc/intel/common: Add Kconfig to enable the CSE FW Update feature Add the Kconfig to enable the CSE FW Update feature and also to ensure all teh configs are set by the mainboards to enable this feature. BUG=b:169077783 Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47523/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 62e6334..76307ec 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -20,6 +20,14 @@ help Enables CSE Lite SKU +config SOC_INTEL_CSE_RW_UPDATE + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + This config will enable CSE RW firmware update feature and also will be used ensure + all the required configs are provided by mainboard. + config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" depends on SOC_INTEL_CSE_LITE_SKU @@ -34,18 +42,18 @@ help CBFS entry name for Intel CSE CBFS RW blob +if SOC_INTEL_CSE_RW_UPDATE config SOC_INTEL_CSE_RW_FILE string "Intel CSE CBFS RW path and filename" - depends on SOC_INTEL_CSE_LITE_SKU default "" help Intel CSE CBFS RW blob path and file name config SOC_INTEL_CSE_RW_VERSION string "Intel CSE RW firmware version" - depends on SOC_INTEL_CSE_LITE_SKU default "" help This config contains the Intel CSE RW version of the blob that is provided by SOC_INTEL_CSE_RW_FILE config and the version must be set in the format major.minor.hotfix.build. +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12810031224f79aba8a4057725ae0ed5a9b36d7e Gerrit-Change-Number: 47523 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/common: Add Kconfig for CSE RW firmware version
by V Sowmya (Code Review) 18 Nov '20

18 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47430 ) Change subject: soc/intel/common: Add Kconfig for CSE RW firmware version ...................................................................... soc/intel/common: Add Kconfig for CSE RW firmware version This patch adds a kconfig SOC_INTEL_CSE_RW_VERSION to pass the CSE RW firmware version from the maiboard. This will be extracted by makefile to update the cse_rw_metadata structure. BUG=b:169077783 Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47430/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index a651198..9d781f9 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -40,3 +40,10 @@ default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_VERSION + string "Intel CSE RW firmware version" + depends on SOC_INTEL_CSE_LITE_SKU + default "" + help + Intel CSE RW firmware version -- To view, visit https://review.coreboot.org/c/coreboot/+/47430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62691ee3ede7d4cd21f821381f5d1519f9061fd9 Gerrit-Change-Number: 47430 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Lock down P2SB SBI
by Christian Walter (Code Review) 17 Nov '20

17 Nov '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46499 ) Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Gerrit-Change-Number: 46499 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Nov 2020 23:42:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020