coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Caveh Jalali (Code Review) 18 Nov '20

18 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 ) Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/early_tcss.h: https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… PS1, Line 103: 0x09000000 > I see, it's a chipset-specific constant, thanks Brandon! […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Nov 2020 06:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 18 Nov '20

18 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#9). Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/Makefile.inc M src/mainboard/google/volteer/variants/volteer2/gpio.c A src/mainboard/google/volteer/variants/volteer2/variant.c 7 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 9 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Caveh Jalali (Code Review) 18 Nov '20

18 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47653 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... soc/intel/tigerlake: Define TCSS AUX pin bias control This adds definitions for controlling the TCSS AUX pins biasing and port orientation. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations in combination with following patches Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/tigerlake/include/soc/early_tcss.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47653/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Source Memory strap GPIOs from variant
by Aamir Bohra (Code Review) 18 Nov '20

18 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46234 ) Change subject: mb/google/volteer: Source Memory strap GPIOs from variant ...................................................................... mb/google/volteer: Source Memory strap GPIOs from variant Allow memory strap GPIOs to be sourced from variant gpio.h. This is done to fix compilation issue of macro redefinition when one of the variant uses a different set of memory strap GPIOs. Change-Id: I5c1ebfb39b2a56ca94a92941e8beed1acc28e655 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/volteer/variants/baseboard/memory.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46234/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h index 4e2733e..26308cf1 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -12,12 +12,6 @@ /* BIOS Flash Write Protect */ #define GPIO_PCH_WP GPP_B11 -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_D15 - /* EC wake is LAN_WAKE# */ #define GPE_EC_WAKE GPE0_LAN_WAK diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c index dafeb3b..d5a99a9 100644 --- a/src/mainboard/google/volteer/variants/baseboard/memory.c +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <baseboard/gpio.h> +#include <variant/gpio.h> #include <baseboard/variants.h> #include <gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/46234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1ebfb39b2a56ca94a92941e8beed1acc28e655 Gerrit-Change-Number: 46234 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/asurada: Configure pins mode for SD
by Wenbin Mei (Code Review) 18 Nov '20

18 Nov '20

Wenbin Mei has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47008 ) Change subject: mb/google/asurada: Configure pins mode for SD ...................................................................... mb/google/asurada: Configure pins mode for SD Configure the pins for SD to msdc1 mode and change the driving value to 8mA. Enable VCC and VCCQ power supply for SD. Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I11151c659b251db987f797a6ae4a08a07971144b --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47008/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index f7521fe..ac94662 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -8,6 +8,7 @@ #include <soc/gpio.h> #include <soc/spm.h> #include <soc/usb.h> +#include <soc/regulator.h> #include "gpio.h" @@ -16,7 +17,15 @@ #define MSDC0_DRV_MASK 0x3fffffff #define MSDC1_DRV_MASK 0x3ffff000 #define MSDC0_DRV_VALUE 0x24924924 -#define MSDC1_DRV_VALUE 0x24924000 +#define MSDC1_DRV_VALUE 0x1b6db000 + +#define MSDC1_GPIO_MODE0_BASE 0x10005360 +#define MSDC1_GPIO_MODE0_MASK 0x77777000 +#define MSDC1_GPIO_MODE0_VALUE 0x11111000 + +#define MSDC1_GPIO_MODE1_BASE 0x10005370 +#define MSDC1_GPIO_MODE1_MASK 0x7 +#define MSDC1_GPIO_MODE1_VALUE 0x1 static void register_reset_to_bl31(void) { @@ -59,6 +68,9 @@ static void configure_sdcard(void) { void *gpio_base = (void *)IOCFG_RM_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + uint8_t enable = 1; int i; const gpio_t sdcard_pu_pin[] = { @@ -77,8 +89,19 @@ for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - /* set sdcard cmd/dat/clk pins driving to 10mA */ + /* set sdcard cmd/dat/clk pins driving to 8mA */ clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE); + + if (!mainboard_regulator_is_enabled(MTK_REGULATOR_VCC)) + mainboard_enable_requlator(MTK_REGULATOR_VCC, enable); + if (!mainboard_regulator_is_enabled(MTK_REGULATOR_VCCQ)) + mainboard_enable_requlator(MTK_REGULATOR_VCCQ, enable); } static void mainboard_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/47008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11151c659b251db987f797a6ae4a08a07971144b Gerrit-Change-Number: 47008 Gerrit-PatchSet: 1 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/asurada: Implement enable_requlator and regulator_is_enabled
by Yidi Lin (Code Review) 18 Nov '20

18 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46687 ) Change subject: mb/google/asurada: Implement enable_requlator and regulator_is_enabled ...................................................................... mb/google/asurada: Implement enable_requlator and regulator_is_enabled SD Card driver needs to access two regulators - MT6360_LDO5 and MT6360_LDO3. These two regulators are disabled by default. Two APIs are implemented, mainboard_enable_requlator - Configure the regulator as enabled / disabled. mainboard_regulator_is_enabled - Query if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/mainboard/google/asurada/regulator.c M src/soc/mediatek/common/include/soc/regulator.h 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46687/1 diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c index 740d98b..ecfe4ef 100644 --- a/src/mainboard/google/asurada/regulator.c +++ b/src/mainboard/google/asurada/regulator.c @@ -25,6 +25,10 @@ return MT6360_LDO7; case MTK_REGULATOR_VMDDR: return MT6360_LDO6; + case MTK_REGULATOR_VCC: + return MT6360_LDO5; + case MTK_REGULATOR_VCCQ: + return MT6360_LDO3; default: break; } @@ -96,3 +100,32 @@ return 0; } + +void mainboard_enable_requlator(enum mtk_regulator regulator, uint8_t enable) +{ + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + google_chromeec_regulator_enable(id, enable); + return; + } + + printk(BIOS_WARNING, "Invalid regualtor ID: %d\n", regulator); +} + +uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator) +{ + int id; + + id = get_mt6360_regulator_id(regulator); + if (id >= 0) { + uint8_t enabled = 0; + google_chromeec_regulator_is_enabled(id, &enabled); + return enabled; + } + + printk(BIOS_WARNING, "Invalid regualtor ID: %d\n", regulator); + + return 0; +} diff --git a/src/soc/mediatek/common/include/soc/regulator.h b/src/soc/mediatek/common/include/soc/regulator.h index 6d9ff4e..35ce1ac 100644 --- a/src/soc/mediatek/common/include/soc/regulator.h +++ b/src/soc/mediatek/common/include/soc/regulator.h @@ -11,10 +11,15 @@ MTK_REGULATOR_VDDQ, MTK_REGULATOR_VMDDR, MTK_REGULATOR_VCORE, + MTK_REGULATOR_VCC, + MTK_REGULATOR_VCCQ, }; void mainboard_set_regulator_vol(enum mtk_regulator regulator, uint32_t voltage_uv); uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator); +void mainboard_enable_requlator(enum mtk_regulator regulator, uint8_t enable); +uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator); + #endif /* SOC_MEDIATEK_COMMON_REGULATOR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4 Gerrit-Change-Number: 46687 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Add more wrappers for regulator control
by Yidi Lin (Code Review) 18 Nov '20

18 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46686 ) Change subject: ec/google/chromeec: Add more wrappers for regulator control ...................................................................... ec/google/chromeec: Add more wrappers for regulator control google_chromeec_regulator_enable is for enabling/disabling the regulator. google_chromeec_regulator_is_enabled is for querying if the regulator is enabled. BUG=b:168863056,b:147789962 BRANCH=none TEST=emerge-asurada coreboot Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46686/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 39cf895..ec32df0 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1617,6 +1617,53 @@ return 0; } +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable) +{ + struct ec_params_regulator_enable params = { + .index = index, + .enable = enable, + }; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_ENABLE, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} + +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled) +{ + + struct ec_params_regulator_is_enabled params = { + .index = index, + }; + struct ec_response_regulator_is_enabled resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_REGULATOR_IS_ENABLED, + .cmd_version = 0, + .cmd_data_in = &params, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + *enabled = resp.enabled; + + return 0; +} + int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv, uint32_t max_mv) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c2ceff8..f081b89 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -354,6 +354,22 @@ int google_chromeec_ap_reset(void); /** + * Configure the regulator as enabled / disabled. + * @param index Regulator ID + * @param enable Set to enable / disable the regulator + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_enable(uint32_t index, uint8_t enable); + +/** + * Query if the regulator is enabled. + * @param index Regulator ID + * @param *enabled If successful, enabled indicates enable/disable status. + * @return 0 on success, -1 on error + */ +int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled); + +/** * Set voltage for the voltage regulator within the range specified. * @param index Regulator ID * @param min_mv Minimum voltage -- To view, visit https://review.coreboot.org/c/coreboot/+/46686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia804242042b0026af19025a0c4a74b3ab8475dab Gerrit-Change-Number: 46686 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/asurada: Implement regulator control for vdd2, vddq and vmddr
by Yidi Lin (Code Review) 18 Nov '20

18 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46406 ) Change subject: mb/google/asurada: Implement regulator control for vdd2, vddq and vmddr ...................................................................... mb/google/asurada: Implement regulator control for vdd2, vddq and vmddr These three requlators are controlled via EC. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/regulator.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/46406/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index 02fb830..d3f8ce6 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -13,6 +13,7 @@ romstage-y += chromeos.c romstage-y += romstage.c romstage-y += sdram_configs.c +romstage-y += regulator.c ramstage-y += memlayout.ld ramstage-y += boardid.c diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c new file mode 100644 index 0000000..514c423 --- /dev/null +++ b/src/mainboard/google/asurada/regulator.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <soc/regulator.h> + +enum mt6360_regulator_id { + MT6360_LDO3, + MT6360_LDO5, + MT6360_LDO6, + MT6360_LDO7, + MT6360_BUCK1, + MT6360_BUCK2, + + MT6360_REGULATOR_COUNT, +}; + +void mainboard_set_vdd2_vol(uint32_t voltage_uv) +{ + uint32_t voltage_mv = voltage_uv / 1000; + + google_chromeec_regulator_set_voltage(MT6360_BUCK1, + voltage_mv, + voltage_mv); +} + +void mainboard_set_vddq_vol(uint32_t voltage_uv) +{ + uint32_t voltage_mv = voltage_uv / 1000; + + google_chromeec_regulator_set_voltage(MT6360_LDO7, + voltage_mv, + voltage_mv); +} + +void mainboard_set_vmddr_vol(uint32_t voltage_uv) +{ + uint32_t voltage_mv = voltage_uv / 1000; + + google_chromeec_regulator_set_voltage(MT6360_LDO6, + voltage_mv, + voltage_mv); +} + +uint32_t mainboard_get_vdd2_vol(void) +{ + uint32_t voltage_mv = 0; + + google_chromeec_regulator_get_voltage(MT6360_BUCK1, &voltage_mv); + + return voltage_mv * 1000; +} + +uint32_t mainboard_get_vddq_vol(void) +{ + uint32_t voltage_mv = 0; + + google_chromeec_regulator_get_voltage(MT6360_LDO7, &voltage_mv); + + return voltage_mv * 1000; +} + +uint32_t mainboard_get_vmddr_vol(void) +{ + uint32_t voltage_mv = 0; + + google_chromeec_regulator_get_voltage(MT6360_LDO6, &voltage_mv); + + return voltage_mv * 1000; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b Gerrit-Change-Number: 46406 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: add pmic MT6315 driver
by CK HU (Code Review) 18 Nov '20

18 Nov '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45400 to review the following change. Change subject: soc/mediatek/mt8192: add pmic MT6315 driver ...................................................................... soc/mediatek/mt8192: add pmic MT6315 driver Add pmic MT6315 driver. BUG=None TEST=boot asurada. BRANCH=None Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/include/soc/mt6315.h A src/soc/mediatek/mt8192/mt6315.c 4 files changed, 415 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/45400/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 0f54c10..9e3f884 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += mt6315.c bootblock-y += mt6359p.c verstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index d9cb684..7987b1c 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/pll.h> #include <soc/pmif.h> @@ -14,4 +15,5 @@ mt_pll_init(); mtk_pmif_init(); mt6359p_init(); + mt6315_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/mt6315.h b/src/soc/mediatek/mt8192/include/soc/mt6315.h new file mode 100644 index 0000000..51b719f --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6315.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6315_H__ +#define __SOC_MEDIATEK_MT6315_H__ + +#include <types.h> + +enum { + PMIC_HWCID_L = 0x0008, + PMIC_HWCID_H = 0x0009, + PMIC_SWCID_L = 0x000A, + PMIC_SWCID_H = 0x000B, +}; + +struct mt6315_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +#define MT6315_SWCID_H_CODE 0x15 +#define MT6315_SWCID_L_E1_CODE 0x10 +#define MT6315_SWCID_L_E2_CODE 0x20 +#define MT6315_SWCID_L_E3_CODE 0x30 + +enum spmi_slave { + SPMI_SLAVE_0 = 0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15 +}; + +enum { + MT6315_CPU = SPMI_SLAVE_6, + MT6315_GPU = SPMI_SLAVE_7, + MT6315_MAX, +}; + +enum { + MT6315_BUCK_1 = 0, + MT6315_BUCK_2, + MT6315_BUCK_3, + MT6315_BUCK_4, + MT6315_BUCK_max, +}; + +enum { + MT6315_BUCK_TOP_ELR0 = 0x1449, + MT6315_BUCK_TOP_ELR3 = 0x144d, + MT6315_BUCK_VBUCK1_DBG0 = 0x1499, + MT6315_BUCK_VBUCK1_DBG3 = 0x1599, +}; + +void mt6315_init(void); +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uV); +unsigned int mt6315_buck_get_voltage(u32 slvid, u32 buck_id); +#endif /* __SOC_MEDIATEK_MT6315_H__ */ diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c new file mode 100644 index 0000000..5702bc4 --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6315.c @@ -0,0 +1,330 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/pmif.h> +#include <soc/mt6315.h> + +static struct pmif *pmif_arb = NULL; + +static struct mt6315_setting init_setting_A[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* clear boot status */ + {0x12A, 0x3, 0xFF, 0}, + {0xD, 1, 0x1, 0}, + {0xD, 0, 0x1, 0}, + {0x1416, 0xF, 0xF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x7, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x1, 0x1F, 0}, + {0x9A1, 0x1, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x1, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x2, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x2, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x2, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x20, 0x70, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0x80, 0xC1, 0}, + {0x169E, 0xF8, 0xF8, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xDB, 0xFF, 0}, + {0x16A3, 0xA1, 0xFF, 0}, + {0x16A4, 0x1, 0xF, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static struct mt6315_setting init_setting_B[] = { + /* disable magic key protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3a2, 0x2A, 0xFF, 0}, + {0x3a1, 0x7C, 0xFF, 0}, + /* init setting */ + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + {0x997, 0x2F, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0xB, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x1, 0x7F, 0}, + {0x148C, 0x4, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x1, 0x7F, 0}, + {0x150C, 0x4, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x1, 0x7F, 0}, + {0x158C, 0x4, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x1, 0x7F, 0}, + {0x160C, 0x4, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xE, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0x0, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x13, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xE, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0x0, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x13, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xE, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0x7F, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0x0, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x13, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xE, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0x0, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x13, 0x3F, 0}, + /* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */ + {0x1440, 0x0, 0x4, 0}, + /* enable magic key protection */ + {0x3A9, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A0, 0, 0xFF, 0}, + {0x39F, 0, 0xFF, 0}, + {0x993, 0, 0xFF, 0}, + {0x992, 0, 0xFF, 0}, + {0x1418, 0, 0xFF, 0}, + {0x1417, 0, 0xFF, 0}, + {0x3a2, 0, 0xFF, 0}, + {0x3a1, 0, 0xFF, 0}, +}; + +static int mt6315_read(u32 slvid, u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + return pmif_arb->read_cmd(pmif_arb, slvid, addr, rdata); +} + +static int mt6315_write(u32 slvid, u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + return pmif_arb->write_cmd(pmif_arb, slvid, addr, wdata); +} + +static unsigned int mt6315_read_field(u32 slvid, u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + mt6315_read(slvid, reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +static void mt6315_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + mt6315_read(slvid, reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + mt6315_write(slvid, reg, new); +} + +static void mt6315_wdt_enable(u32 slvid) +{ + mt6315_write_field(slvid, 0x3A9, 0x63, 0xFF, 0); + mt6315_write_field(slvid, 0x3A8, 0x15, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x2, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x1, 0xFF, 0); + mt6315_write_field(slvid, 0x127, 0x8, 0xFF, 0); + udelay(50); + mt6315_write_field(slvid, 0x128, 0x8, 0xFF, 0); + mt6315_write_field(slvid, 0x3A9, 0, 0xFF, 0); + mt6315_write_field(slvid, 0x3A8, 0, 0xFF, 0); +} + +static void mt6315_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting_A); i++) + mt6315_write_field(MT6315_CPU, + init_setting_A[i].addr, init_setting_A[i].val, + init_setting_A[i].mask, init_setting_A[i].shift); + + for (size_t i = 0; i < ARRAY_SIZE(init_setting_B); i++) + mt6315_write_field(MT6315_GPU, + init_setting_B[i].addr, init_setting_B[i].val, + init_setting_B[i].mask, init_setting_B[i].shift); +} + +void mt6315_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uV) +{ + unsigned int vol_reg, vol_val; + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_TOP_ELR0; + break; + + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_TOP_ELR3; + break; + + default: + assert(0); + return; + }; + + vol_val = buck_uV / 6250; + mt6315_write_field(slvid, vol_reg, vol_val, 0xFF, 0); + + return; +} + +unsigned int mt6315_buck_get_voltage(u32 slvid, u32 buck_id) +{ + u32 vol_reg, vol; + + switch (buck_id) { + case MT6315_BUCK_1: + vol_reg = MT6315_BUCK_VBUCK1_DBG0; + break; + + case MT6315_BUCK_3: + vol_reg = MT6315_BUCK_VBUCK1_DBG3; + break; + + default: + assert(0); + return 0; + }; + + vol = mt6315_read_field(slvid, vol_reg, 0xFF, 0); + return vol * 6250; +} + +void mt6315_init(void) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPMI, 0); + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi!"); + + mt6315_wdt_enable(MT6315_CPU); + mt6315_wdt_enable(MT6315_GPU); + mt6315_init_setting(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b47473ee5d56a197bd21d4ab9b539d9663b6636 Gerrit-Change-Number: 45400 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: soc/mediatek/mt8192: add pmic MT6359P driver
by CK HU (Code Review) 18 Nov '20

18 Nov '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45399 to review the following change. Change subject: soc/mediatek/mt8192: add pmic MT6359P driver ...................................................................... soc/mediatek/mt8192: add pmic MT6359P driver Add pmic MT6359P driver. TEST=Boots correctly on MT8192EVB. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I62f69490165539847b8b7260942644533b15285b --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/include/soc/mt6359p.h A src/soc/mediatek/mt8192/mt6359p.c 4 files changed, 507 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45399/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 0fc47c4..0f54c10 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -10,6 +10,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += mt6359p.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index 0852f0e..d9cb684 100644 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/mt6359p.h> #include <soc/pll.h> #include <soc/pmif.h> #include <soc/wdt.h> @@ -12,4 +13,5 @@ mtk_wdt_init(); mt_pll_init(); mtk_pmif_init(); + mt6359p_init(); } diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h new file mode 100644 index 0000000..e1465c8 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6359P_H__ +#define __SOC_MEDIATEK_MT6359P_H__ + +#include <types.h> + +enum { + PMIC_HWCID = 0x0008, + PMIC_SWCID = 0x000a, + PMIC_TOP_RST_MISC_SET = 0x014c, + PMIC_TOP_RST_MISC_CLR = 0x014e, + PMIC_PWRHOLD = 0x0a08, + PMIC_VGPU11_DBG0 = 0x15a6, + PMIC_VGPU11_ELR0 = 0x15b4, + PMIC_VS2_VOTER = 0x18aa, + PMIC_VS2_VOTER_CFG = 0x18b0, + PMIC_VS2_ELR0 = 0x18b4, + PMIC_VSRAM_PROC1_ELR = 0x1b44, + PMIC_VSRAM_PROC2_ELR = 0x1b46, + PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90, + PMIC_VSRAM_PROC2_VOSEL1 = 0x1eb0, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6359P_GPU11 = 0, + MT6359P_SRAM_PROC1, + MT6359P_SRAM_PROC2, + MT6359P_MAX, +}; + +void mt6359p_init(void); +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uV); +unsigned int mt6359p_buck_get_voltage(u32 buck_id); +#endif /* __SOC_MEDIATEK_MT6359P_H__ */ diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c new file mode 100644 index 0000000..5426421 --- /dev/null +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -0,0 +1,450 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/pmif.h> +#include <soc/mt6359p.h> + +static struct pmic_setting init_setting[] = { + {0x20, 0xA, 0xA, 0}, + {0x24, 0x1F00, 0x1F00, 0}, + {0x30, 0x1, 0x1, 0}, + {0x32, 0x1, 0x1, 0}, + {0x94, 0x0, 0xFFFF, 0}, + {0x10C, 0x10, 0x10, 0}, + {0x112, 0x4, 0x4, 0}, + {0x118, 0x8, 0x8, 0}, + {0x14A, 0x20, 0x20, 0}, + {0x198, 0x0, 0x1FF, 0}, + {0x1B2, 0x3, 0x3, 0}, + {0x3B0, 0x0, 0x300, 0}, + {0x790, 0x3, 0x3, 0}, + {0x7A6, 0xF800, 0xFC00, 0}, + {0x7A8, 0x0, 0x280, 0}, + {0x98A, 0x80, 0x80, 0}, + {0x992, 0xF00, 0xF00, 0}, + {0xA08, 0x1, 0x1, 0}, + {0xA0C, 0x300, 0x300, 0}, + {0xA10, 0x0, 0x4000, 0}, + {0xA12, 0x1E0, 0x1E0, 0}, + {0xA24, 0xFFFF, 0xFFFF, 0}, + {0xA26, 0xFFE0, 0xFFE0, 0}, + {0xA2C, 0xC0DF, 0xC0DF, 0}, + {0xA2E, 0xEBE0, 0xEBE0, 0}, + {0xA34, 0x8000, 0x8000, 0}, + {0xA3C, 0x1C00, 0x1F00, 0}, + {0xA3E, 0x341, 0x7FFF, 0}, + {0xA40, 0x1042, 0x7FFF, 0}, + {0xA42, 0xC05, 0x7FFF, 0}, + {0xA44, 0x20E5, 0x7FFF, 0}, + {0xA46, 0x2652, 0x7FFF, 0}, + {0xA48, 0x716A, 0x7FFF, 0}, + {0xA4A, 0x62EC, 0x7FFF, 0}, + {0xA4C, 0x5676, 0x7FFF, 0}, + {0xA4E, 0x6F34, 0x7FFF, 0}, + {0xA50, 0xC0, 0x7FFF, 0}, + {0xA9C, 0x4000, 0x4000, 0}, + {0xA9E, 0x2E11, 0xFF11, 0}, + {0xF8C, 0x115, 0x115, 0}, + {0x1188, 0x0, 0x8000, 0}, + {0x1198, 0x13, 0x3FF, 0}, + {0x119E, 0x6000, 0x7000, 0}, + {0x11D4, 0x0, 0x2, 0}, + {0x1212, 0x0, 0x2, 0}, + {0x1224, 0x0, 0x2, 0}, + {0x1238, 0x0, 0x2, 0}, + {0x124A, 0x0, 0x2, 0}, + {0x125C, 0x0, 0x2, 0}, + {0x125E, 0x0, 0x8000, 0}, + {0x1260, 0x1, 0xFFF, 0}, + {0x1262, 0x4, 0x4, 0}, + {0x1412, 0x8, 0x8, 0}, + {0x148E, 0x18, 0x7F, 0}, + {0x1492, 0x505, 0x7F7F, 0}, + {0x1514, 0x2, 0x2, 0}, + {0x1520, 0x0, 0x2, 0}, + {0x152C, 0x7F, 0x7F, 0}, + {0x158E, 0x18, 0x7F, 0}, + {0x1592, 0xC00, 0x7F00, 0}, + {0x160E, 0x18, 0x7F, 0}, + {0x1694, 0x2, 0x2, 0}, + {0x16A0, 0x0, 0x2, 0}, + {0x16AE, 0x50, 0x7F, 0}, + {0x170E, 0x18, 0x7F, 0}, + {0x178E, 0x18, 0x7F, 0}, + {0x198A, 0x5004, 0x502C, 0}, + {0x198C, 0x11, 0x3F, 0}, + {0x198E, 0x1E0, 0x1E0, 0}, + {0x1990, 0xFD, 0xFF, 0}, + {0x1994, 0x10, 0x38, 0}, + {0x1996, 0x2004, 0xA02C, 0}, + {0x1998, 0x11, 0x3F, 0}, + {0x199A, 0xFB78, 0xFF78, 0}, + {0x199E, 0x2, 0x7, 0}, + {0x19A0, 0x1050, 0x10F1, 0}, + {0x19A2, 0x18, 0x38, 0}, + {0x19A4, 0xF, 0xF, 0}, + {0x19A6, 0x30, 0xFF, 0}, + {0x19AC, 0x4200, 0x4680, 0}, + {0x19AE, 0x6E, 0x7E, 0}, + {0x19B0, 0x3C00, 0x3C00, 0}, + {0x19B4, 0x20FD, 0xFFFF, 0}, + {0x1A08, 0x4200, 0x4680, 0}, + {0x1A0A, 0x6E, 0x7E, 0}, + {0x1A0C, 0x3C00, 0x3C00, 0}, + {0x1A10, 0x20FD, 0xFFFF, 0}, + {0x1A14, 0x4208, 0x4698, 0}, + {0x1A16, 0x46, 0x7E, 0}, + {0x1A18, 0x3C00, 0x3C00, 0}, + {0x1A1C, 0x30FF, 0xFFFF, 0}, + {0x1A1E, 0x0, 0x200, 0}, + {0x1A20, 0x4208, 0x4698, 0}, + {0x1A22, 0x4A, 0x7E, 0}, + {0x1A24, 0x3C00, 0x3C00, 0}, + {0x1A28, 0x3000, 0xFF00, 0}, + {0x1A2C, 0x20, 0x74, 0}, + {0x1A2E, 0x1E, 0x1E, 0}, + {0x1A30, 0x42, 0xFF, 0}, + {0x1A32, 0x480, 0x7E0, 0}, + {0x1A34, 0x20, 0x74, 0}, + {0x1A36, 0x1E, 0x1E, 0}, + {0x1A38, 0x42, 0xFF, 0}, + {0x1A3A, 0x480, 0x7E0, 0}, + {0x1A3C, 0x14C, 0x3CC, 0}, + {0x1A3E, 0x23C, 0x3FC, 0}, + {0x1A40, 0xC400, 0xFF00, 0}, + {0x1A42, 0x80, 0xFF, 0}, + {0x1A44, 0x702C, 0xFF2C, 0}, + {0x1B0E, 0xF, 0xF, 0}, + {0x1B10, 0x1, 0x1, 0}, + {0x1B14, 0xFFFF, 0xFFFF, 0}, + {0x1B1A, 0x3FFF, 0x3FFF, 0}, + {0x1B32, 0x8, 0x8, 0}, + {0x1B8A, 0x30, 0x8030, 0}, + {0x1B9C, 0x10, 0x8010, 0}, + {0x1BA0, 0x4000, 0x4000, 0}, + {0x1BAE, 0x1410, 0x9C10, 0}, + {0x1BB2, 0x2, 0x2, 0}, + {0x1BC0, 0x10, 0x8010, 0}, + {0x1BD2, 0x13, 0x8013, 0}, + {0x1BE4, 0x10, 0x8010, 0}, + {0x1C0A, 0x10, 0x8010, 0}, + {0x1C1E, 0x10, 0x8010, 0}, + {0x1C30, 0x10, 0x8010, 0}, + {0x1C42, 0x10, 0x8010, 0}, + {0x1C54, 0x32, 0x8033, 0}, + {0x1C66, 0x10, 0x8010, 0}, + {0x1C8A, 0x10, 0x8010, 0}, + {0x1C8E, 0x4000, 0x4000, 0}, + {0x1C9C, 0x10, 0x8010, 0}, + {0x1CAE, 0x10, 0x8010, 0}, + {0x1CC0, 0x10, 0x8010, 0}, + {0x1CD2, 0x33, 0x8033, 0}, + {0x1CE4, 0x33, 0x8033, 0}, + {0x1D0A, 0x10, 0x8010, 0}, + {0x1D1E, 0x10, 0x8010, 0}, + {0x1D22, 0x4000, 0x4000, 0}, + {0x1D30, 0x10, 0x8010, 0}, + {0x1D34, 0x4000, 0x4000, 0}, + {0x1D42, 0x30, 0x8030, 0}, + {0x1D46, 0x4000, 0x4000, 0}, + {0x1D54, 0x30, 0x8030, 0}, + {0x1D66, 0x32, 0x8033, 0}, + {0x1D8A, 0x10, 0x8010, 0}, + {0x1D9C, 0x10, 0x8010, 0}, + {0x1E8A, 0x10, 0x8010, 0}, + {0x1E92, 0xC12, 0x7F7F, 0}, + {0x1EAA, 0x10, 0x8010, 0}, + {0x1EB2, 0xC1F, 0x7F7F, 0}, + {0x1F0A, 0x10, 0x8010, 0}, + {0x1F12, 0xC1F, 0x7F7F, 0}, + {0x1F30, 0x10, 0x8010, 0}, + {0x1F38, 0xF1F, 0x7F7F, 0}, + {0x200A, 0x8, 0xC, 0}, + {0x202C, 0x8, 0xC, 0}, + {0x208C, 0x100, 0xF00, 0}, + {0x209C, 0x80, 0x1E0, 0}, +}; + +static struct pmic_setting lp_setting[] = { + /* Suspend */ + {0x1520, 0x0, 0x1, 0x1}, + {0x1514, 0x1, 0x1, 0x1}, + {0x151a, 0x0, 0x1, 0x1}, + {0x14a0, 0x1, 0x1, 0x1}, + {0x1494, 0x1, 0x1, 0x1}, + {0x149a, 0x1, 0x1, 0x1}, + {0x1714, 0x1, 0x1, 0xf}, + {0x1794, 0x1, 0x1, 0xf}, + {0x15a0, 0x1, 0x1, 0x0}, + {0x1594, 0x1, 0x1, 0x0}, + {0x159a, 0x1, 0x1, 0x0}, + {0x1614, 0x1, 0x1, 0xf}, + {0x16a0, 0x0, 0x1, 0x1}, + {0x1694, 0x1, 0x1, 0x1}, + {0x169a, 0x0, 0x1, 0x1}, + {0x1820, 0x1, 0x1, 0x0}, + {0x1814, 0x1, 0x1, 0x0}, + {0x181a, 0x1, 0x1, 0x0}, + {0x18a0, 0x1, 0x1, 0x0}, + {0x1894, 0x1, 0x1, 0x0}, + {0x189a, 0x1, 0x1, 0x0}, + {0x1e96, 0x1, 0x1, 0xf}, + {0x1eb6, 0x1, 0x1, 0xf}, + {0x1f16, 0x1, 0x1, 0xf}, + {0x1f3c, 0x1, 0x1, 0xf}, + {0x1c58, 0x1, 0x1, 0xf}, + {0x1d8e, 0x1, 0x1, 0xf}, + {0x1c34, 0x1, 0x1, 0xf}, + {0x1c22, 0x1, 0x1, 0xf}, + {0x1bae, 0x0, 0x1, 0xb}, + {0x1bb2, 0x1, 0x1, 0x1}, + {0x1bb8, 0x0, 0x1, 0x1}, + {0x1cb2, 0x1, 0x1, 0xf}, + {0x1bd6, 0x1, 0x1, 0xf}, + {0x1bc0, 0x1, 0x1, 0xa}, + {0x1bc4, 0x1, 0x1, 0x0}, + {0x1bca, 0x1, 0x1, 0x0}, + {0x1d22, 0x1, 0x1, 0xe}, + {0x1d28, 0x0, 0x1, 0xe}, + {0x1c66, 0x1, 0x1, 0xa}, + {0x1c6a, 0x1, 0x1, 0x0}, + {0x1c70, 0x1, 0x1, 0x0}, + {0x1c42, 0x1, 0x1, 0xb}, + {0x1c46, 0x1, 0x1, 0x1}, + {0x1c4c, 0x1, 0x1, 0x1}, + {0x1d34, 0x1, 0x1, 0xe}, + {0x1d3a, 0x0, 0x1, 0xe}, + {0x1b8a, 0x0, 0x1, 0xb}, + {0x1b8e, 0x1, 0x1, 0x1}, + {0x1b94, 0x0, 0x1, 0x1}, + {0x1d42, 0x1, 0x1, 0xa}, + {0x1d46, 0x1, 0x1, 0x0}, + {0x1d4c, 0x0, 0x1, 0x0}, + {0x1ca0, 0x1, 0x1, 0xf}, + {0x1c8a, 0x1, 0x1, 0xa}, + {0x1c8e, 0x1, 0x1, 0x0}, + {0x1c94, 0x1, 0x1, 0x0}, + {0x1b9c, 0x1, 0x1, 0xa}, + {0x1ba0, 0x1, 0x1, 0x0}, + {0x1ba6, 0x1, 0x1, 0x0}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xa}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1cc4, 0x1, 0x1, 0xf}, + {0x1d6a, 0x1, 0x1, 0xf}, + {0x1cd6, 0x1, 0x1, 0xf}, + {0x1ce8, 0x1, 0x1, 0xf}, + {0x1da0, 0x1, 0x1, 0xf}, + {0x1d58, 0x1, 0x1, 0xf}, + + /* Deepidle */ + {0x15a0, 0x1, 0x1, 0x2}, + {0x1594, 0x1, 0x1, 0x2}, + {0x159a, 0x1, 0x1, 0x2}, + {0x1820, 0x1, 0x1, 0x2}, + {0x1814, 0x1, 0x1, 0x2}, + {0x181a, 0x1, 0x1, 0x2}, + {0x18a0, 0x1, 0x1, 0x2}, + {0x1894, 0x1, 0x1, 0x2}, + {0x189a, 0x1, 0x1, 0x2}, + {0x1bc0, 0x1, 0x1, 0xc}, + {0x1bc4, 0x1, 0x1, 0x2}, + {0x1bca, 0x1, 0x1, 0x2}, + {0x1c66, 0x1, 0x1, 0xc}, + {0x1c6a, 0x1, 0x1, 0x2}, + {0x1c70, 0x1, 0x1, 0x2}, + {0x1d42, 0x1, 0x1, 0xc}, + {0x1d46, 0x1, 0x1, 0x2}, + {0x1d4c, 0x0, 0x1, 0x2}, + {0x1c8a, 0x1, 0x1, 0xc}, + {0x1c8e, 0x1, 0x1, 0x2}, + {0x1c94, 0x1, 0x1, 0x2}, + {0x1b9c, 0x1, 0x1, 0xc}, + {0x1ba0, 0x1, 0x1, 0x2}, + {0x1ba6, 0x1, 0x1, 0x2}, + {0x1be8, 0x1, 0x1, 0xf}, + {0x1c0e, 0x1, 0x1, 0xf}, + {0x1d0a, 0x1, 0x1, 0xc}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, +}; + +static struct pmif *pmif_arb = NULL; +static s32 mt6359p_read(u32 addr, u32 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + return pmif_arb->read_cmd(pmif_arb, 0, addr, rdata); +} + +static s32 mt6359p_write(u32 addr, u32 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + return pmif_arb->write_cmd(pmif_arb, 0, addr, wdata); +} + +static u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + mt6359p_read(reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + return rdata; +} + +static void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + mt6359p_read(reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + mt6359p_write(reg, new); +} + +static void pmic_set_power_hold(void) +{ + mt6359p_write_field(PMIC_PWRHOLD, 1, 0x1, 0); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x20, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6359p_write_field(PMIC_TOP_RST_MISC_CLR, 0x02, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6359p_write_field(PMIC_TOP_RST_MISC_SET, 0x01, 0xFFFF, 0); +} + +static void pmic_init_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6359p_write_field( + init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); +} + +static void pmic_lp_setting(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(lp_setting); i++) + mt6359p_write_field( + lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} + +static void pmic_wk_vs2_voter_setting(void) +{ + /* + * 1. Set VS2_VOTER_VOSEL = 1.35V + * 2. Clear VS2_VOTER + * 3. Set VS2_VOSEL = 1.4V + **/ + mt6359p_write_field(PMIC_VS2_VOTER_CFG, 0x2C, 0x7F, 0); + mt6359p_write_field(PMIC_VS2_VOTER, 0, 0xFFF, 0); + mt6359p_write_field(PMIC_VS2_ELR0, 0x30, 0x7F, 0); +} + +void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uV) +{ + u32 vol_offset, vol_reg, vol; + + switch (buck_id) { + case MT6359P_GPU11: + vol_offset = 400000; + vol_reg = PMIC_VGPU11_ELR0; + break; + + case MT6359P_SRAM_PROC1: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_ELR; + break; + + case MT6359P_SRAM_PROC2: + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_ELR; + break; + + default: + /* assert(0); */ + return; + }; + + vol = (buck_uV - vol_offset) / 6250; + mt6359p_write_field(vol_reg, vol, 0x7F, 0); +} + +unsigned int mt6359p_buck_get_voltage(u32 buck_id) +{ + u32 vol_shift, vol_offset, vol_reg, vol; + + switch (buck_id) { + case MT6359P_GPU11: + vol_shift = 0; + vol_offset = 400000; + vol_reg = PMIC_VGPU11_DBG0; + break; + + case MT6359P_SRAM_PROC1: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC1_VOSEL1; + break; + + case MT6359P_SRAM_PROC2: + vol_shift = 8; + vol_offset = 500000; + vol_reg = PMIC_VSRAM_PROC2_VOSEL1; + break; + + default: + assert(0); + return 0; + }; + + vol = mt6359p_read_field(vol_reg, 0x7F, vol_shift); + return vol_offset + vol * 6250; +} + + +void mt6359p_init(void) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi!"); + + printk(BIOS_ERR, "[%s] SWCID(0x%x), HWCID(0x%x)\n", __func__, + mt6359p_read_field(PMIC_SWCID, 0xFFFF, 0), + mt6359p_read_field(PMIC_HWCID, 0xFFFF, 0)); + + pmic_set_power_hold(); + pmic_wdt_set(); + pmic_init_setting(); + pmic_lp_setting(); + pmic_wk_vs2_voter_setting(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62f69490165539847b8b7260942644533b15285b Gerrit-Change-Number: 45399 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020