coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Caveh Jalali (Code Review) 17 Nov '20

17 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 ) Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/early_tcss.h: https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… PS1, Line 103: 0x09000000 > Did you figure out where this 0x09 at the top byte comes from? or it just always appears here, even […] @brandon.breitenstein@intel.com needs to answer this one as he originally introduced this value. i have no visibility in this area. -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 21:05:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Add touchscreen settings
by Tim Chen (Code Review) 17 Nov '20

17 Nov '20

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47433 to review the following change. Change subject: mb/google/dedede/var/metaknight: Add touchscreen settings ...................................................................... mb/google/dedede/var/metaknight: Add touchscreen settings Add Elan and Goodix touchscreen settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57 --- M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47433/1 diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 556a44f..25bc866 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -44,6 +44,41 @@ device domain 0 on device pci 15.0 on end + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6915"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end # I2C 2 device pci 15.3 off end # I2C 3 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57 Gerrit-Change-Number: 47433 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy/v/atlas: Reset bluetooth during boot
by Tim Wawrzynczak (Code Review) 17 Nov '20

17 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46620 ) Change subject: mb/google/poppy/v/atlas: Reset bluetooth during boot ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/46620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c489963f7a353e8fc5f55b6cba7aaee0b347a37 Gerrit-Change-Number: 46620 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Nov 2020 20:39:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy: Add late_gpio support
by Tim Wawrzynczak (Code Review) 17 Nov '20

17 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46619 ) Change subject: mb/google/poppy: Add late_gpio support ...................................................................... Patch Set 3: Code-Review+1 seems slightly obnoxious to have to program GPIOs in bootblock, romstage, and twice in ramstage but hey, what can you do -- To view, visit https://review.coreboot.org/c/coreboot/+/46619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I847f90275740ca825e4c93e6b8d5650143228476 Gerrit-Change-Number: 46619 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Nov 2020 20:39:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Use SoC header for TCSS port control
by Tim Wawrzynczak (Code Review) 17 Nov '20

17 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47654 ) Change subject: mb/google/volteer: Use SoC header for TCSS port control ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ded34ad2316764ce42851b3d9b631ed5a30860e Gerrit-Change-Number: 47654 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 20:35:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control
by Tim Wawrzynczak (Code Review) 17 Nov '20

17 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 ) Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control ...................................................................... Patch Set 1: Code-Review+1 (1 comment) much more readable, thanks Caveh! https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… File src/soc/intel/tigerlake/include/soc/early_tcss.h: https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/in… PS1, Line 103: 0x09000000 Did you figure out where this 0x09 at the top byte comes from? or it just always appears here, even though they're marked reserved? -- To view, visit https://review.coreboot.org/c/coreboot/+/47653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I001aede139c2503ce9cae3af8d625624ff6e1af7 Gerrit-Change-Number: 47653 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 20:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Tim Wawrzynczak (Code Review) 17 Nov '20

17 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 129: /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= BIT(2); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : } > hmmm... can we update struct soc_intel_tigerlake_config from there? […] We can (using `config_of_soc()`), and if we trust the `GpioOverride` UPD in FSP-S, then we could move the boot state we call `fw_config_handle` from. Right now it's BS_DEV_ENABLE, but it could be earlier (BS_PRE_DEVICE) so that it definitely runs before FSP-S. I'll take a look at doing that in a followup. https://review.coreboot.org/c/coreboot/+/47501/7/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/7/src/mainboard/google/volte… PS7, Line 129: #if CONFIG(VARIANT_HAS_PASSIVE_USB_DB) : /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= IOM_TCSS_PORT_CTRL(1, : IOM_TCSS_ORI_NORMAL, IOM_TCSS_MUX_INTERNAL); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : } : #endif /* VARIANT_HAS_PASSIVE_USB_DB */ suggestion: add a new variant-specific function to handle this, e.g., `void variant_configure_usb_db(void)` with a __weak implementation here that does nothing. The #if goes away here, e.g. just call `variant_configure_usb_db()` then in variants/volteer2/variant.c (new file), implement it just like it is here, e.g. ``` void variant_configure_usb_db(void) { if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { /* * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 * section 3.6.10 * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN */ cfg->TcssAuxOri |= IOM_TCSS_PORT_CTRL(1, IOM_TCSS_ORI_NORMAL, IOM_TCSS_MUX_INTERNAL); cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; } } ``` Then the whole VARIANT_HAS_PASSIVE_DB goes away -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 7 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 17 Nov 2020 20:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Follow the Integration Guide recommendations
by Arthur Heymans (Code Review) 17 Nov '20

17 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47168 to look at the new patch set (#9). Change subject: soc/intel/xeon_sp: Follow the Integration Guide recommendations ...................................................................... soc/intel/xeon_sp: Follow the Integration Guide recommendations The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47168/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/47168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Gerrit-Change-Number: 47168 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Lock down P2SB SBI
by Arthur Heymans (Code Review) 17 Nov '20

17 Nov '20

Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46499 to look at the new patch set (#12). Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ...................................................................... soc/intel/xeon_sp/cpx: Lock down P2SB SBI This is required for CBnT. Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/p2sb.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46499/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/46499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Gerrit-Change-Number: 46499 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/volteer: enable early tcss chrome ec related code in mainboard
by Brandon Breitenstein (Code Review) 17 Nov '20

17 Nov '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45742 ) Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ...................................................................... mainboard/volteer: enable early tcss chrome ec related code in mainboard Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard. BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 23c3e92..80a04d0 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -5,9 +5,11 @@ #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> +#include <ec/google/chromeec/ec.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> +#include <soc/early_tcss.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -65,6 +67,78 @@ } } +void mainboard_early_tcss_enable(void) +{ + uint8_t dp_mode; + unsigned int num_ports; + int ret, i; + bool ufp, acc; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) { + printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); + return; + } + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); + continue; + } + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_port_info failed\n", i); + continue; + } + + mux_data.usb2_port = port_map & USB_2_PORT_MASK; + mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4; + + //Add check for connected maybe? + + ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: pd_control failed\n", i); + continue; + } + + mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_data.ufp = !!ufp; + mux_data.acc = !!acc; + mux_data.dp_mode = dp_mode; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "DP Mode = %x\n" + "dp = %d\n" + "usb = %d\n" + "cable = %d\n" + "polarity = %d\n" + "hpd_lvl = %d\n" + "hpd_irq = %d\n" + "ufp = %d\n" + "dbg_acc = %d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.dp_mode, mux_data.dp, + mux_data.usb, mux_data.cable, mux_data.polarity, + mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp, + mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 43ba255..179aeb0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -59,6 +59,8 @@ register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" + register "RMT" = "1" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/45742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Gerrit-Change-Number: 45742 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020