coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/reef/variants/: add Naya NT6AN256T32AV-J2
by James Chao (Code Review) 17 Nov '20

17 Nov '20

James Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47382 ) Change subject: mb/google/reef/variants/: add Naya NT6AN256T32AV-J2 ...................................................................... mb/google/reef/variants/: add Naya NT6AN256T32AV-J2 BUG=b:172843935 BRANCH=coral TEST=emerge-coral coreboot chromeos-bootimage Signed-off-by: James Chao <james_chao(a)asus.corp-partner.google.com> Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e --- M src/mainboard/google/reef/variants/baseboard/memory.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47382/1 diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c index aac160b..6b267c9 100644 --- a/src/mainboard/google/reef/variants/baseboard/memory.c +++ b/src/mainboard/google/reef/variants/baseboard/memory.c @@ -138,6 +138,13 @@ .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "K4F8E3S4HD-MGCL", }, + /* NT6AN256T32AV-J2 - both logical channels */ + [9] = { + .speed = LP4_SPEED_2400, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .part_num = "NT6AN256T32AV-J2", + }, }; static const struct lpddr4_cfg lp4cfg = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e Gerrit-Change-Number: 47382 Gerrit-PatchSet: 1 Gerrit-Owner: James Chao <james_chao(a)asus.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/zork: Assume VBOOT_STARTS_BEFORE_BOOTBLOCK
by Martin Roth (Code Review) 17 Nov '20

17 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47529 ) Change subject: mb/google/zork: Assume VBOOT_STARTS_BEFORE_BOOTBLOCK ...................................................................... mb/google/zork: Assume VBOOT_STARTS_BEFORE_BOOTBLOCK At this point, the zork platform will only use psp_verstage, so remove the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS- BEFORE_BOOTBLOCK to always be used. TEST=Build & Boot Morphius BRANCH=Zork BUG=b:172848137 Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/Makefile.inc M src/mainboard/google/zork/bootblock.c M src/mainboard/google/zork/variants/baseboard/Makefile.inc 4 files changed, 3 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/47529/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 320f668..0bad802 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -105,6 +105,7 @@ config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH + select VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_VBNV_OFFSET hex @@ -129,7 +130,7 @@ config PICASSO_FW_A_POSITION hex default 0xFF012040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_A region. This is the start of the RW-A region + 64 bytes for the cbfs header. @@ -137,7 +138,7 @@ config PICASSO_FW_B_POSITION hex default 0xFF312040 - depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on VBOOT_SLOTS_RW_AB help Location of the AMD firmware in the RW_B region. This is the start of the RW-A region + 64 bytes for the cbfs header. @@ -241,22 +242,6 @@ help Last board version that needs the extra delay for FPMCU init. -config VBOOT_STARTS_BEFORE_BOOTBLOCK - bool "PSP verstage" - default y if VBOOT - help - Firmware verification happens before the main processor is brought - online. - -config VBOOT_STARTS_IN_BOOTBLOCK - bool "X86 verstage (in bootblock)" - depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK - select VBOOT_SEPARATE_VERSTAGE - help - Firmware verification happens during the end of or right after the - bootblock. This implies that a static VBOOT2_WORK() buffer must be - allocated in memlayout. - config EFS_SPI_READ_MODE int default 0 if EM100 # Normal read mode diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 88aef86..96c97b6 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -9,11 +9,7 @@ ramstage-y += ec.c ramstage-y += sku_id.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-y += verstage.c -else -verstage-y += chromeos.c -endif smm-y += smihandler.c diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index ed05888..87e0285 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -12,10 +12,5 @@ gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); program_gpios(gpios, num_gpios); - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { - gpios = variant_early_gpio_table(&num_gpios); - program_gpios(gpios, num_gpios); - } - variant_pcie_gpio_configure(); } diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index c8d57ff..2764a89 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -7,10 +7,8 @@ verstage-y += gpio_baseboard_common.c verstage-y += helpers.c -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c verstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c -endif verstage-y += tpm_tis.c romstage-y += gpio_baseboard_common.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d Gerrit-Change-Number: 47529 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: skip reading EDID completely
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46580 to review the following change. Change subject: HACK: skip reading EDID completely ...................................................................... HACK: skip reading EDID completely Something goes terribly wrong when reading the EDID, and ANX7625 does not seem to be able to recover from it. BUG=b:155713214 TEST=boot asurada Change-Id: I2230af30b709667f9858f6144b14681686003f28 --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46580/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index eb7e661..e3f969c 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -854,7 +854,9 @@ int ret; u8 edid[FOUR_BLOCK_SIZE]; - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ + if (0) + block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); block_num=1; memcpy(edid, &edp_edid, sizeof(edp_edid)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2230af30b709667f9858f6144b14681686003f28 Gerrit-Change-Number: 46580 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: WIP: coreboot: Add eDP edid to skip get edid fail
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46579 ) Change subject: WIP: coreboot: Add eDP edid to skip get edid fail ...................................................................... WIP: coreboot: Add eDP edid to skip get edid fail Add eDP edid to skip get edid fail and start display development Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I58c7ea1fd45a2def87593f9436d2c513c5b502af --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 3 files changed, 67 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46579/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9f0b2e1..eb7e661 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -828,6 +828,26 @@ return ret; } +/*Add eDP EDID to skip get edid fail*/ +static const u8 edp_edid[128] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x0d, 0xae, 0x47, 0x12, 0x00, 0x00, 0x00, 0x00, + 0x13, 0x1c, 0x01, 0x04, 0x95, 0x19, 0x11, 0x78, + 0x02, 0x67, 0x75, 0x98, 0x59, 0x53, 0x90, 0x27, + 0x1c, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x61, 0x1f, + 0x56, 0x56, 0x50, 0x90, 0x0a, 0x30, 0x30, 0x20, + 0x36, 0x00, 0xfd, 0xa9, 0x00, 0x00, 0x00, 0x18, + 0x00, 0x00, 0x00, 0xfe, 0x00, 0x4e, 0x31, 0x32, + 0x30, 0x41, 0x43, 0x41, 0x2d, 0x45, 0x41, 0x31, + 0x0a, 0x20, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x43, + 0x4d, 0x4e, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfe, + 0x00, 0x4e, 0x31, 0x32, 0x30, 0x41, 0x43, 0x41, + 0x2d, 0x45, 0x41, 0x31, 0x0a, 0x20, 0x00, 0xea, +}; + int anx7625_dp_get_edid(uint8_t bus, struct edid *out) { int block_num; @@ -835,6 +855,9 @@ u8 edid[FOUR_BLOCK_SIZE]; block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + block_num=1; + + memcpy(edid, &edp_edid, sizeof(edp_edid)); if (block_num < 0) { ANXERROR("Failed to get eDP EDID.\n"); return -1; diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2505bbc..ac289c8 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -130,8 +130,11 @@ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) tmp_reg1 = SYNC_PULSE_MODE; } - +#if 1 //DSI pattern write32(&dsi0->dsi_mode_ctrl, tmp_reg1); + write32(&dsi0->dsi_bist_pattern, 0xff00); + write32(&dsi0->dsi_bist_con, 0x40); +#endif } static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) @@ -415,7 +418,7 @@ { u32 data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); - + data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); if (!data_rate) return -1; @@ -434,5 +437,38 @@ mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); + printk(BIOS_ERR, "dsi_start = 0x%08x\n", read32(&dsi0->dsi_start)); + printk(BIOS_ERR, "dsi_inten = 0x%08x\n", read32(&dsi0->dsi_inten)); + printk(BIOS_ERR, "dsi_intsta = 0x%08x\n", read32(&dsi0->dsi_intsta)); + printk(BIOS_ERR, "dsi_con_ctrl = 0x%08x\n", read32(&dsi0->dsi_con_ctrl)); + printk(BIOS_ERR, "dsi_mode_ctrl = 0x%08x\n", read32(&dsi0->dsi_mode_ctrl)); + printk(BIOS_ERR, "dsi_txrx_ctrl = 0x%08x\n", read32(&dsi0->dsi_txrx_ctrl)); + printk(BIOS_ERR, "dsi_psctrl = 0x%08x\n", read32(&dsi0->dsi_psctrl)); + printk(BIOS_ERR, "dsi_vsa_nl = 0x%08x\n", read32(&dsi0->dsi_vsa_nl)); + printk(BIOS_ERR, "dsi_vbp_nl = 0x%08x\n", read32(&dsi0->dsi_vbp_nl)); + printk(BIOS_ERR, "dsi_vfp_nl = 0x%08x\n", read32(&dsi0->dsi_vfp_nl)); + printk(BIOS_ERR, "dsi_vact_nl = 0x%08x\n", read32(&dsi0->dsi_vact_nl)); + printk(BIOS_ERR, "dsi_lfr_con = 0x%08x\n", read32(&dsi0->dsi_lfr_con)); + printk(BIOS_ERR, "dsi_lfr_sta = 0x%08x\n", read32(&dsi0->dsi_lfr_sta)); + printk(BIOS_ERR, "dsi_size_con = 0x%08x\n", read32(&dsi0->dsi_size_con)); + printk(BIOS_ERR, "dsi_vfp_early_stop = 0x%08x\n", read32(&dsi0->dsi_vfp_early_stop)); + printk(BIOS_ERR, "dsi_hsa_wc = 0x%08x\n", read32(&dsi0->dsi_hsa_wc)); + printk(BIOS_ERR, "dsi_hbp_wc = 0x%08x\n", read32(&dsi0->dsi_hbp_wc)); + printk(BIOS_ERR, "dsi_hfp_wc = 0x%08x\n", read32(&dsi0->dsi_hfp_wc)); + printk(BIOS_ERR, "dsi_bllp_wc = 0x%08x\n", read32(&dsi0->dsi_bllp_wc)); + printk(BIOS_ERR, "dsi_cmdq_size = 0x%08x\n", read32(&dsi0->dsi_cmdq_size)); + printk(BIOS_ERR, "dsi_hstx_cklp_wc = 0x%08x\n", read32(&dsi0->dsi_hstx_cklp_wc)); + printk(BIOS_ERR, "dsi_phy_lccon = 0x%08x\n", read32(&dsi0->dsi_phy_lccon)); + printk(BIOS_ERR, "dsi_phy_ld0con = 0x%08x\n", read32(&dsi0->dsi_phy_ld0con)); + printk(BIOS_ERR, "dsi_phy_timecon0 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon0)); + printk(BIOS_ERR, "dsi_phy_timecon1 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon1)); + printk(BIOS_ERR, "dsi_phy_timecon2 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon2)); + printk(BIOS_ERR, "dsi_phy_timecon3 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon3)); + printk(BIOS_ERR, "dsi_vm_cmd_con = 0x%08x\n", read32(&dsi0->dsi_vm_cmd_con)); + printk(BIOS_ERR, "dsi_bist_pattern = 0x%08x\n", read32(&dsi0->dsi_bist_pattern)); + printk(BIOS_ERR, "dsi_bist_con = 0x%08x\n", read32(&dsi0->dsi_bist_con)); + printk(BIOS_ERR, "dsi_force_commit = 0x%08x\n", read32(&dsi0->dsi_force_commit)); + return 0; } + diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7bacec1..edb597a 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -75,10 +75,13 @@ u32 dsi_phy_timecon2; u32 dsi_phy_timecon3; u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[92]; + u32 dsi_vm_cmd_con;/*0x130*/ + u8 reserved5[68]; + u32 dsi_bist_pattern; /*0x178*/ + u32 dsi_bist_con;/* 0x17c */ + u8 reserved6[16]; u32 dsi_force_commit; /* Available since MT8183 */ - u8 reserved6[108]; + u8 reserved7[108]; u32 dsi_cmdq[128]; }; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -- To view, visit https://review.coreboot.org/c/coreboot/+/46579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c7ea1fd45a2def87593f9436d2c513c5b502af Gerrit-Change-Number: 46579 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DEBUG: ANX read edid test
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46837 ) Change subject: DEBUG: ANX read edid test ...................................................................... DEBUG: ANX read edid test Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: Icaaf8d7a96d40839947beeb0b6d50521b314b91a --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 28 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46837/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 1f04346..121075a 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -848,24 +848,41 @@ 0x2d, 0x45, 0x41, 0x31, 0x0a, 0x20, 0x00, 0xea, }; +static void anx7625_read_ver(uint8_t bus) +{ + uint8_t version, revision; + + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version); + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision); + + ANXINFO("OCM : ver %#02x, rev %#02x.\n", version, revision); +} + int anx7625_dp_get_edid(uint8_t bus, struct edid *out) { int block_num; int ret; u8 edid[FOUR_BLOCK_SIZE]; - /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); - if (block_num <= 0) { - block_num = 1; - memcpy(edid, &edp_edid, sizeof(edp_edid)); - ANXINFO("Failed to get eDP EDID, test with hard code edied.\n"); - } + anx7625_read_ver(bus); + ANXINFO("first time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 1st time done.\n"); - if (block_num < 0) { - ANXERROR("Failed to get eDP EDID.\n"); - return -1; - } + anx7625_read_ver(bus); + ANXINFO("2nd time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 2nd time done.\n"); + + anx7625_read_ver(bus); + ANXINFO("3rd time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 3rd time done.\n"); + anx7625_read_ver(bus); + + ANXINFO("use fixed edid\n"); + block_num = 0; + memcpy(edid, &edp_edid, sizeof(edp_edid)); ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); if (ret != EDID_CONFORMANT) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaaf8d7a96d40839947beeb0b6d50521b314b91a Gerrit-Change-Number: 46837 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DEBUG: anx read edid test
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46827 ) Change subject: DEBUG: anx read edid test ...................................................................... DEBUG: anx read edid test Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: I3b880f69f3c0d987972bb6b337c636bfa130b9ce --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46827/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e3f969c..1f04346 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -855,11 +855,13 @@ u8 edid[FOUR_BLOCK_SIZE]; /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ - if (0) - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); - block_num=1; + block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + if (block_num <= 0) { + block_num = 1; + memcpy(edid, &edp_edid, sizeof(edp_edid)); + ANXINFO("Failed to get eDP EDID, test with hard code edied.\n"); + } - memcpy(edid, &edp_edid, sizeof(edp_edid)); if (block_num < 0) { ANXERROR("Failed to get eDP EDID.\n"); return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/46827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b880f69f3c0d987972bb6b337c636bfa130b9ce Gerrit-Change-Number: 46827 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: HACK: Enable display backlight
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46583 to review the following change. Change subject: HACK: Enable display backlight ...................................................................... HACK: Enable display backlight Change the polarity so that the backlight is at maximum. BUG=b:155713214 TEST=boot asurada Change-Id: I058af933e59be84cca77ea15b668be6efcc6539d --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46583/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 30e98e8..56ecc9e 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -56,8 +56,8 @@ /* Set up backlight control pins as output pin and power-off by default */ static void configure_panel_backlight(void) { - gpio_output(GPIO(KPROW1), 0); - gpio_output(GPIO(DISP_PWM), 0); + gpio_output(GPIO(KPROW1), 1); + gpio_output(GPIO(DISP_PWM), 1); } static void power_on_panel(struct panel_description *panel) -- To view, visit https://review.coreboot.org/c/coreboot/+/46583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058af933e59be84cca77ea15b668be6efcc6539d Gerrit-Change-Number: 46583 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: First set pwren to 0
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46581 to review the following change. Change subject: HACK: First set pwren to 0 ...................................................................... HACK: First set pwren to 0 Maybe not 100% necessary, but should still be good practise. BUG=b:155713214 TEST=boot asurada Change-Id: Ib8b3366795ae876227546be393681d8ac404e51b --- M src/mainboard/google/asurada/panel_anx7625.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46581/1 diff --git a/src/mainboard/google/asurada/panel_anx7625.c b/src/mainboard/google/asurada/panel_anx7625.c index 0145859..10aa305 100644 --- a/src/mainboard/google/asurada/panel_anx7625.c +++ b/src/mainboard/google/asurada/panel_anx7625.c @@ -18,6 +18,7 @@ gpio_output(GPIO_PP3300_PANEL, 1); /* Turn on bridge */ + gpio_output(GPIO_MIPIBRDG_PWREN, 0); gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); gpio_output(GPIO_MIPIBRDG_PP1000_EN, 1); gpio_output(GPIO_MIPIBRDG_PP1800_EN, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8b3366795ae876227546be393681d8ac404e51b Gerrit-Change-Number: 46581 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Move the MP2CFG checking to category of BIOS data
by Bao Zheng (Code Review) 17 Nov '20

17 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47587 to review the following change. Change subject: amdfwtool: Move the MP2CFG checking to category of BIOS data ...................................................................... amdfwtool: Move the MP2CFG checking to category of BIOS data Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/data_parse.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47587/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index b3470d5..c2ce32b 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -187,13 +187,6 @@ } else { fw_type = AMD_FW_SKIP; } - } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { - if (cb_config->load_mp2_fw == 1) { - fw_type = AMD_BIOS_MP2_CFG; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } } else if (strcmp(fw_name, "PSP_DRIVERS_FILE") == 0) { fw_type = AMD_DRIVER_ENTRIES; subprog = 0; @@ -267,6 +260,13 @@ fw_type = AMD_BIOS_PMUD; subprog = 1; instance = 4; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + if (cb_config->load_mp2_fw == 1) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else { fw_type = AMD_BIOS_INVALID; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf9c96dd0ed8c31bb50350d37646ca08a1bbff0 Gerrit-Change-Number: 47587 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector"
by Kyösti Mälkki (Code Review) 17 Nov '20

17 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47596 ) Change subject: Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" ...................................................................... Revert "arch|cpu/x86: Add Kconfig option for x86 reset vector" This partially reverts commit 67910db907fb3d5feacdbfaa40952a88f673795a. The symbol X86_RESET_VECTOR continues to live, for the time being, under soc/amd/picasso. Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/id.ld M src/arch/x86/memlayout.ld M src/cpu/x86/16bit/reset16.ld 4 files changed, 9 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47596/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 900c9c1..b5e52e6 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -88,16 +88,6 @@ default n depends on ARCH_X86 && SMP -config X86_RESET_VECTOR - hex - depends on ARCH_X86 - default 0xfffffff0 - help - Specify the location of the x86 reset vector. In traditional devices - this must match the architectural reset vector to produce a bootable - image. Nontraditional designs may use this to position the reset - vector into its desired location. - config RESET_VECTOR_IN_RAM bool depends on ARCH_X86 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld index ea8d7e9..b69a8dc 100644 --- a/src/arch/x86/id.ld +++ b/src/arch/x86/id.ld @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ SECTIONS { - . = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start); + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; .id (.): { KEEP(*(.id)) } diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 3659cc9..cbf887c 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -28,7 +28,7 @@ #include "car.ld" #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, + BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) #include "car.ld" diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index b90dd04..e00e0b4 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* _RESET_VECTOR: typically the top of the ROM */ +/* + * _ROMTOP : The top of the ROM used where we + * need to put the reset vector. + */ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - - . = CONFIG_X86_RESET_VECTOR; + _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + _ROMTOP = 0xfffffff0; + . = _ROMTOP; .reset . : { *(.reset); . = 15; -- To view, visit https://review.coreboot.org/c/coreboot/+/47596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6b2cc2b17133b3207758c72a54abe80fc6356b5 Gerrit-Change-Number: 47596 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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