coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Fix skx NVME drive boot issue
by Marc Jones (Code Review) 17 Nov '20

17 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47579 ) Change subject: soc/intel/xeon_sp: Fix skx NVME drive boot issue ...................................................................... soc/intel/xeon_sp: Fix skx NVME drive boot issue Skx FSP doesn't support x2apic setup, but cpx does. The skx DMAR table needs the X2API opt out flag set. This fixes an issue with the NVME driver loading on a kexec'd kernel. The change is easy to see in the coreboot output: [DMA Remapping table] Flags: 0x3 or in the DMAR ACPI table. Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47579/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 55c3d82..1b28f2d 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -443,9 +443,13 @@ if (config->vtd_support) { current = ALIGN(current, 8); dmar = (acpi_dmar_t *)current; + enum dmar_flags flags = DMAR_INTR_REMAP; +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + flags |= DMAR_X2APIC_OPT_OUT; +#endif printk(BIOS_DEBUG, "ACPI: * DMAR\n"); - printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", DMAR_INTR_REMAP); - acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", flags); + acpi_create_dmar(dmar, flags, acpi_fill_dmar); current += dmar->header.length; current = acpi_align_current(current); acpi_add_table(rsdp, dmar); -- To view, visit https://review.coreboot.org/c/coreboot/+/47579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e Gerrit-Change-Number: 47579 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

8 15

Change in coreboot[master]: [WIP] plot 2D read margins
by Angel Pons (Code Review) 17 Nov '20

17 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47681 ) Change subject: [WIP] plot 2D read margins ...................................................................... [WIP] plot 2D read margins Change-Id: I7cda8d19b78f6265c8e5919ce942f709738e5e44 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.asus_p8h61-m_pro.debug_read_2d_margins M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c 3 files changed, 141 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47681/1 diff --git a/configs/config.asus_p8h61-m_pro.debug_read_2d_margins b/configs/config.asus_p8h61-m_pro.debug_read_2d_margins new file mode 100644 index 0000000..8a46605 --- /dev/null +++ b/configs/config.asus_p8h61-m_pro.debug_read_2d_margins @@ -0,0 +1,6 @@ +CONFIG_VENDOR_ASUS=y +CONFIG_BOARD_ASUS_P8H61_M_PRO=y +CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y +CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +CONFIG_RAMINIT_PLOT_READ_MARGINS=y +CONFIG_DEBUG_RAM_SETUP=y diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..8f53656 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -105,6 +105,13 @@ help Enable ECC if supported by both, host and RAM. +config RAMINIT_PLOT_READ_MARGINS + bool "Plot 2D read margins for DQS edges" + depends on DEBUG_RAM_SETUP + default n + help + Plot 2D margins instead of doing aggressive read training. + endif # USE_NATIVE_RAMINIT if !USE_NATIVE_RAMINIT diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 8f60b8c..8276ba1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2440,6 +2440,8 @@ { const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; + const bool sweep_vref = CONFIG(RAMINIT_PLOT_READ_MARGINS); + u32 raw_stats[MAX_EDGE_TIMING + 1]; int lower[NUM_LANES]; int upper[NUM_LANES]; @@ -2450,16 +2452,39 @@ upper[lane] = MAX_EDGE_TIMING; } - for (i = 0; i < ARRAY_SIZE(rd_vref_offsets); i++) { + const int max_vref_idx = sweep_vref ? 63 : ARRAY_SIZE(rd_vref_offsets); + for (i = 0; i < max_vref_idx; i++) { + const int vref = i >= 32 ? i : 31 - i; const union gdcr_training_mod_reg training_mod = { - .vref_gen_ctl = rd_vref_offsets[i], + .vref_gen_ctl = sweep_vref ? vref : rd_vref_offsets[i], }; MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); + if (sweep_vref) + printram("% 5d:\t", 31 - i); + for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - printram("using pattern %d\n", pat); + + if (!sweep_vref) + printram("using pattern %d\n", pat); + + /* Center read timing to ensure memory is correctly written */ + read_pi = MAX_EDGE_TIMING / 2; + + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].rising = read_pi; + ctrl->timings[channel][slotrank].lanes[lane].falling = read_pi; + } + program_timings(ctrl, channel); + + /* Write test pattern to memory */ + iosav_write_data_write_sequence(ctrl, channel, slotrank); + + iosav_run_once(channel); + + wait_for_iosav(channel); for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { @@ -2474,22 +2499,100 @@ MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } - wait_for_iosav(channel); - iosav_write_data_write_sequence(ctrl, channel, slotrank); + /* Program read sequence */ + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 0, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PREA */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); - /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); + FOR_ALL_LANES { MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } /* FIXME: This register only exists on Ivy Bridge */ raw_stats[read_pi] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); + + if (!sweep_vref) + continue; + + if (i == 31 && read_pi == (MAX_EDGE_TIMING + 1) / 2) + printram("%c", raw_stats[read_pi] & 0xff ? 'X' : '+'); + else + printram("%c", raw_stats[read_pi] & 0xff ? '#' : '.'); } + if (sweep_vref) + printram(" "); + FOR_ALL_LANES { int stats[MAX_EDGE_TIMING + 1]; struct run rn; @@ -2499,18 +2602,26 @@ rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " - "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, - rn.middle, rn.end, rn.start + ctrl->edge_offset[i], - rn.end - ctrl->edge_offset[i]); + const int edge_offset = sweep_vref ? 0 : ctrl->edge_offset[i]; - lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); - upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); + if (!sweep_vref) { + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " + "0x%02x-0x%02x\n", channel, slotrank, i, + rn.start, rn.middle, rn.end, + rn.start + edge_offset, rn.end - edge_offset); + } + + if (!sweep_vref || i == 0) { + lower[lane] = MAX(rn.start + edge_offset, lower[lane]); + upper[lane] = MIN(rn.end - edge_offset, upper[lane]); + } edges[lane] = (lower[lane] + upper[lane]) / 2; - if (rn.all || (lower[lane] > upper[lane])) { + + if (!sweep_vref && (rn.all || lower[lane] > upper[lane])) { printk(BIOS_EMERG, "edge write discovery failed: " - "%d, %d, %d\n", channel, slotrank, lane); + "%d, %d, %d, %d, %d, %d\n", channel, slotrank, + lane, rn.all, lower[lane], upper[lane]); return MAKE_ERR; } @@ -2518,6 +2629,9 @@ } } + if (sweep_vref) + printram("\n"); + /* Restore nominal Vref after training */ MCHBAR32(GDCRTRAININGMOD_ch(channel)) = 0; printram("CPA\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cda8d19b78f6265c8e5919ce942f709738e5e44 Gerrit-Change-Number: 47681 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Power off fingerprint sensor on shutdown
by Martin Roth (Code Review) 17 Nov '20

17 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47311 ) Change subject: mb/google/zork: Power off fingerprint sensor on shutdown ...................................................................... mb/google/zork: Power off fingerprint sensor on shutdown When the system shuts down, turn the fingerprint sensor off. This sets the GPIOs correctly for the next boot. The fingerprint sensor was previously left on, and was just powering down when the rails went low. On suspend, the fingerprint sensor stays awake and puts itself in a low powerstate mode based on the SLP_Sx_L pin states. BUG=b:171837716 TEST=Fingerprint sensor still works after S3, GPIO state on the boot following a shutdown is low. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I4b292181d67c08c20fa4c473b363cfe2f934bff0 Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47311/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index bf27622..389ff5b 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -337,8 +337,25 @@ PAD_GPO(GPIO_76, LOW), }; +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), + + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) { + if (slp_typ == SLP_TYP_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + *size = ARRAY_SIZE(gpio_sleep_table); return gpio_sleep_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995 Gerrit-Change-Number: 47311 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats
by Angel Pons (Code Review) 17 Nov '20

17 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47578 ) Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ...................................................................... [WIP] nb/intel/sandybridge: Simplify rcven coarse stats Change-Id: Ief17dbd7633b010f2775bf4b5ed9151a139540b2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 101 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47578/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index f20181e..03ae877 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -909,6 +909,11 @@ LANEBASE_ECC }; +static u32 gdcr_read32(const int offset, const int lane) +{ + return MCHBAR32(lane_base[lane] + offset); +} + void program_timings(ramctr_timing *ctrl, int channel) { u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; @@ -1115,26 +1120,112 @@ return ret; } +static void print_raw_statistics(ramctr_timing *ctrl, u32 statistics[NUM_LANES][4], int sz) +{ + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + + for (int j = 0; j < sz; j++) { + for (int i = 0; i < 32; i++) { + printk(BIOS_ERR, "% 5d\t", i + j * 32); + + int lane; + FOR_ALL_LANES { + const bool pass = !!(statistics[lane][j] & 1 << i); + printk(BIOS_ERR, "%c", pass ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + } +} + +static struct run get_passing_region(u32 *statistics, int sz) +{ + /* Initialize all variables depending on whether the first point passed or not */ + const int init_value = statistics[0] & 1 ? 0 : -1; + + int initial_lower = init_value; + int initial_upper = init_value; + int current_lower = init_value; + int current_upper = init_value; + int largest_lower = init_value; + int largest_upper = init_value; + + for (int j = 0; j < sz; j++) { + for (int i = 0; i < 32; i++) { + + const int idx = i + j * 32; + + if (idx == 0) + continue; + + if (!(statistics[j] & 1 << i)) + continue; + + /* Update initial region upper limit */ + if (initial_upper == idx - 1) + initial_upper = idx; + + /* If this pass is not contiguous, start a new pass region */ + if (current_upper != idx - 1) + current_lower = idx; + + /* Update current region upper limit */ + current_upper = idx; + + /* Update largest variables */ + if (current_upper - current_lower > largest_upper - largest_lower) { + largest_lower = current_lower; + largest_upper = current_upper; + } + } + } + + printk(BIOS_ERR, "\nStats: IL: %d, IU: %d, CL: %d, CU: %d, LL: %d, LU: %d\n", + initial_lower, initial_upper, + current_lower, current_upper, + largest_upper, largest_upper); + + printk(BIOS_ERR, "\n"); + + return (struct run) { + .middle = (largest_upper + largest_lower) / 2, + .end = largest_upper, + .start = largest_lower, + .length = largest_upper - largest_lower, + }; +} + +static u32 get_stats(int channel, int lane, int idx) +{ + return gdcr_read32(GDCRTRAININGRESULT(channel, idx), lane); +} + static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA; - int statistics[NUM_LANES][128]; + u32 statistics[NUM_LANES][4]; int lane; - for (timA = 0; timA < 128; timA++) { - FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA = timA; + for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { + for (timA = 0; timA < 64; timA++) { + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timA = + timA + logic_delay * 64; + } + program_timings(ctrl, channel); + + test_timA(ctrl, channel, slotrank); } - program_timings(ctrl, channel); - - test_timA(ctrl, channel, slotrank); - FOR_ALL_LANES { - statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); + statistics[lane][logic_delay * 2 + 0] = get_stats(channel, lane, 0); + statistics[lane][logic_delay * 2 + 1] = get_stats(channel, lane, 1); } } + printk(BIOS_ERR, "Channel %d results:\n", channel); + print_raw_statistics(ctrl, statistics, 4); + FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], 128); + struct run rn = get_passing_region(statistics[lane], 4); ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; upperA[lane] = rn.end; if (upperA[lane] < rn.middle) -- To view, visit https://review.coreboot.org/c/coreboot/+/47578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief17dbd7633b010f2775bf4b5ed9151a139540b2 Gerrit-Change-Number: 47578 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Michael Niewöhner (Code Review) 17 Nov '20

17 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: > Patch Set 1: Code-Review-1 > > Denverton-NS maintainers list update is planned this week. > I`ll update it when it will be confirmed and let you know. It's not only about updating the maintainers list but also *actually* maintain it ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 15:12:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Michael Niewöhner (Code Review) 17 Nov '20

17 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: Code-Review+1 > > > > What is the downside of this announcement? It directly says, that if a maintainer steps up, and hardware can be tested, that it will be left in the tree. So, please include it. > > It's currently full of unresolved comments and collides with other patches. I don't really mind the change per se. Mimimimimimiiii ;) I already said I wait until people wake up ;) -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Nov 2020 15:12:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by build bot (Jenkins) (Code Review) 17 Nov '20

17 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46881 ) Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46881/6/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46881/6/src/soc/intel/common/block… PS6, Line 537: uint8_t clnt_addr = (p->group_id == MCHI_GROUP_ID_MCA) ? \ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 13:36:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add functions to support setting DAM state
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46882 ) Change subject: soc/intel/common/block/cse: Add functions to support setting DAM state ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46882/5/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46882/5/src/soc/intel/common/block… PS5, Line 986: -1 > ret instead of -1 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If42eb150577e9f76318e77ae31eb6f5844a4143d Gerrit-Change-Number: 46882 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 13:31:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46880 ) Change subject: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46880/5/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46880/5/src/soc/intel/common/block… PS5, Line 859: memcpy(data_buffer, resp.data, resp.data_size); > You may also want to *data_size = resp. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Gerrit-Change-Number: 46880 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 13:31:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI ...
by Maulik V Vaghela (Code Review) 17 Nov '20

17 Nov '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46881 ) Change subject: soc/intel/common/block/cse: Modify heci_send_receive to support MCHI address ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/46881/5/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/46881/5/src/soc/intel/common/block… PS5, Line 537: p = snd_msg > This can be initialized in the previous line itself. Done https://review.coreboot.org/c/coreboot/+/46881/5/src/soc/intel/common/block… PS5, Line 539: MCHI_GROUP_ID_MCA > MCHI_GROUP_ID_MCA should be defined as part of this CL. […] Done https://review.coreboot.org/c/coreboot/+/46881/5/src/soc/intel/common/block… PS5, Line 539: if (p->group_id == MCHI_GROUP_ID_MCA) { : if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MCHI_ADDR)) { : printk(BIOS_ERR, "HECI: send Failed\n"); : return 0; : } : } else { : if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, HECI_MKHI_ADDR)) { : printk(BIOS_ERR, "HECI: send Failed\n"); : return 0; : } : } > This can be simplified further: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice6f6bb0069080b9ac75a5323475c002e03eb751 Gerrit-Change-Number: 46881 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Nov 2020 13:31:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2020