coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: libpayload/usb: Add format string checking to usb_debug
by Tim Wawrzynczak (Code Review) 16 Nov '20

16 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45025 ) Change subject: libpayload/usb: Add format string checking to usb_debug ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892 Gerrit-Change-Number: 45025 Gerrit-PatchSet: 7 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 21:17:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/usb: Fix printf format string mismatches in debug messages
by Tim Wawrzynczak (Code Review) 16 Nov '20

16 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 ) Change subject: libpayload/usb: Fix printf format string mismatches in debug messages ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Gerrit-Change-Number: 45024 Gerrit-PatchSet: 7 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 21:16:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#54). Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... mb/kontron: Add Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/kontron/mal10.md A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/cpld.asl A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc A src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt A src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c A src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h A src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/data.vbt A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/mal10/Makefile.inc A src/mainboard/kontron/mal10/variants/mal10/board_info.txt A src/mainboard/kontron/mal10/variants/mal10/devicetree.cb A src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/variants/mal10/gpio.c A src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h 27 files changed, 1,044 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 54 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/picasso/acpi.h: include missing header files
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47627 ) Change subject: soc/amd/picasso/acpi.h: include missing header files ...................................................................... soc/amd/picasso/acpi.h: include missing header files In the file uintptr_t that is defined in stdint.h and struct device that is defined in device/device.h are used, so include them directly to avoid having to rely on them being included in the file that includes this header file. Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/acpi.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47627/1 diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d347..0345e23 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -6,6 +6,8 @@ #include <acpi/acpi.h> #include <amdblocks/acpi.h> #include <amdblocks/gpio_banks.h> +#include <device/device.h> +#include <stdint.h> unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -- To view, visit https://review.coreboot.org/c/coreboot/+/47627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486 Gerrit-Change-Number: 47627 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Tim Wawrzynczak (Code Review) 16 Nov '20

16 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/47501/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47501/3//COMMIT_MSG@10 PS3, Line 10: volteer > 75 doesn't look right in gerrit. I think it's supposed to be 72 chars? https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 34: #define TGL_GPIO_ID_GPP_E22 0x090E0016 : #define TGL_GPIO_ID_GPP_E23 0x090E0017 : I think we can do a little better here too 😊 suggestion: ``` #define VW_SHIFT 0x16 #define IOM_AUX_ORIENTATION_BIAS_GPIO(vw, bit, gid) ((vw & 0xff) << 0x16) | ((bit & 0x7) << 8) | ((gid & 0xff)) #define TGL_IOM_GPIO_E22 IOM_AUX_ORIENTATION_BIAS_GPIO(0xE, 0, 0x16) #define TGL_IOM_GPIO_E23 IOM_AUX_ORIENTATION_BIAS_GPIO(0xE, 0, 0x17) ``` except that I'm not sure where you get the 0x09 from the high byte. I see those as "Reserved" bits in the EDS (v 1.2) -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 19:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Tim Wawrzynczak (Code Review) 16 Nov '20

16 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/Kconfig: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 153: VARIANT_HAS_PASSIVE_USB_DB I don't think this is necessary. The weak `variant_usb3_passive_gpio_table` returns 0 pads to configure, so devices w/o the passive DB aren't affected. https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 136: BIT(2) I think we could make a nice set of #define for this, here's my suggestion: ``` #define RETIMER 0 #define PLATFORM 1 #define TCSS_PORT_SBU_ORIENTATION_CONTROL(port, cntrl) ((cntrl) << ((port) - 1) << 1) ``` then this would look like: ``` cfg->TcssAuxOri |= TCSS_PORT_SBU_ORIENTATION_CONTROL(2, PLATFORM) ``` https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 129: /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= BIT(2); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : } I think this should go in fw_config.c as well. Then there's only one place to change any configurations that depend on FW_CONFIG values. -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 19:01:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 16 Nov '20

16 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/c/coreboot/+/47501/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47501/3//COMMIT_MSG@10 PS3, Line 10: volteer > Nit: Should fit in the line above (75 characters per line). 75 doesn't look right in gerrit. https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/Kconfig: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 153: config VARIANT_HAS_PASSIVE_USB_DB > I wonder why this is board specific, and not put into some common code, or at least the chipset code […] at this point, this is a volteer specific feature. https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 154: bool > Some description/help would be nice. Ack https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 128: #if CONFIG(VARIANT_HAS_PASSIVE_USB_DB) > Please use the C if, and not the preprocessor one, if possible. GPIO_ID_TCP1_AUXx_DC isn't necessarily defined, so this needs to be conditionally compiled. -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 18:58:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 16 Nov '20

16 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#5). Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h 9 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 16 Nov '20

16 Nov '20

Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Brandon Breitenstein, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47501 to look at the new patch set (#4). Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/include/variant/gpio.h 9 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: libpayload/usb: Fix printf format string mismatches in debug messages
by build bot (Jenkins) (Code Review) 16 Nov '20

16 Nov '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 ) Change subject: libpayload/usb: Fix printf format string mismatches in debug messages ...................................................................... Patch Set 7: (8 comments) https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/ehci.c: https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 56: usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 58: usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/ohci.c: https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 73: usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 77: usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 94: usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 510: usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/uhci.c: https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 83: usb_debug("|:| O | PID CODE | [%04"PRIx32"] |:|\n", td->token & 0xFF); line over 96 characters https://review.coreboot.org/c/coreboot/+/45024/7/payloads/libpayload/driver… PS7, Line 84: usb_debug("|:| K | Endpoint | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/45024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Gerrit-Change-Number: 45024 Gerrit-PatchSet: 7 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 16 Nov 2020 18:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020