coreboot-gerrit November 2020

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Change in coreboot[master]: nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usage
by Angel Pons (Code Review) 16 Nov '20

16 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47484 ) Change subject: nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usage ...................................................................... nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usage It is usually written to right after programming a pattern, because its lower byte contains the number of cachelines of the programmed pattern. The other cases merely reset the WDB data write and compare pointers. Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/47484/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..3ab8df2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1953,6 +1953,12 @@ return ret; } +/* Each cacheline is 64 bits long */ +static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) +{ + MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; +} + static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) { unsigned int j; @@ -1962,6 +1968,8 @@ write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); + + program_wdb_pattern_length(channel, 8); } static int num_of_channels(const ramctr_timing *ctrl) @@ -1985,6 +1993,8 @@ write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); sfence(); + + program_wdb_pattern_length(channel, 16); } static void precharge(ramctr_timing *ctrl) @@ -2370,10 +2380,10 @@ MCHBAR32(GDCRTRAININGMOD) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { + /* Reset read and write WDB pointers */ MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; wait_for_iosav(channel); @@ -2728,7 +2738,6 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2770,6 +2779,7 @@ MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; } + /* Reset read WDB pointer */ MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; wait_for_iosav(channel); @@ -2937,6 +2947,8 @@ } sfence(); } + + program_wdb_pattern_length(channel, 256); } static void reprogram_320c(ramctr_timing *ctrl) @@ -3104,7 +3116,6 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern5(ctrl, channel, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; } FOR_ALL_POPULATED_CHANNELS { @@ -3312,7 +3323,6 @@ FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } @@ -3563,7 +3573,6 @@ } fill_pattern0(ctrl, channel, 0, 0xffffffff); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } /* @@ -3631,7 +3640,6 @@ for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { @@ -4000,7 +4008,6 @@ stats[MAX_TIMC] = 1; fill_pattern5(ctrl, channel, pat); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES { @@ -4130,8 +4137,6 @@ } FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); - - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } for (slotrank = 0; slotrank < 4; slotrank++) @@ -4272,7 +4277,6 @@ FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); fill_pattern0(ctrl, channel, 0, 0); - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6 Gerrit-Change-Number: 47484 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: libpayload/i8042: Increase response timeout to 1.5s
by Nico Huber (Code Review) 16 Nov '20

16 Nov '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47588 ) Change subject: libpayload/i8042: Increase response timeout to 1.5s ...................................................................... libpayload/i8042: Increase response timeout to 1.5s The current timeout of 500ms is too low. For instance self-test of the KBC integrated into IT8516E took almost 1s in tests. We already check for presence of the KBC before the self-test. So the timeout should only trigger on a hardware defect and we can leave some margin. Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M payloads/libpayload/drivers/i8042/i8042.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47588/1 diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c index 50d013d..84bad55 100644 --- a/payloads/libpayload/drivers/i8042/i8042.c +++ b/payloads/libpayload/drivers/i8042/i8042.c @@ -159,7 +159,7 @@ */ static u8 i8042_wait_data_rdy(void) { - int retries = 10000; + int retries = 30000; while (retries-- && !(read_status() & OBF)) udelay(50); -- To view, visit https://review.coreboot.org/c/coreboot/+/47588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95f01a4e605a9c7deb894a71e102c3a881759bb1 Gerrit-Change-Number: 47588 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: util/intelp2m: Clean up SCI, SMI macro generation and update comments
by Patrick Georgi (Code Review) 16 Nov '20

16 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47314 ) Change subject: util/intelp2m: Clean up SCI, SMI macro generation and update comments ...................................................................... util/intelp2m: Clean up SCI, SMI macro generation and update comments Simplify macro generation and fix up "DEEP,EDGE_SINGLE" bug introduced by commit 7bb756f (util/intelp2m: Update macros). Also update legacy macro comments. Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47314 Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 6 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 43d373e..fb530c5 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -90,12 +90,12 @@ macro.Add("_APIC") if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL { if dw0.GetRxInvert() != 0 { - // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) + // PAD_CFG_GPI_APIC_LOW(pad, pull, rst) macro.Add("_LOW") } else { + // PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) macro.Add("_HIGH") } - // PAD_CFG_GPI_APIC(pad, pull, rst) macro.Add("(").Id().Pull().Rstsrc().Add("),") return true } @@ -123,18 +123,8 @@ if dw0.GetGPIOInputRouteSCI() == 0 { return false } - macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - macro.Trig() - } - // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), - // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ - // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - macro.Add(",").Add("EDGE_SINGLE") - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } @@ -145,16 +135,8 @@ if dw0.GetGPIOInputRouteSMI() == 0 { return false } - macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { - // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), - macro.Add(",").Add("EDGE_SINGLE") - } - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - // e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), - macro.Trig() - } - macro.Invert().Add("),") + // PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") return true } -- To view, visit https://review.coreboot.org/c/coreboot/+/47314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Gerrit-Change-Number: 47314 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Felix Singer (Code Review) 16 Nov '20

16 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/47539/1/Documentation/releases/cor… File Documentation/releases/coreboot-4.13-relnotes.md: https://review.coreboot.org/c/coreboot/+/47539/1/Documentation/releases/cor… PS1, Line 75: > I'd suggest sending an email to the mailing list. […] Unfortunately, I wasn't able to get coreboot booting on mine. Even with Julien's new patches it didn't work. -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Nov 2020 11:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's
by Arthur Heymans (Code Review) 16 Nov '20

16 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47302 ) Change subject: soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's ...................................................................... soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id's Add a soc specific callback for getting the IIO IOAPIC enumeration ID. Tested on ocp/deltalake. Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 6 files changed, 47 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47302/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index c70945a..46f9c5f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -90,23 +90,19 @@ /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif #if (CONFIG(SOC_INTEL_SKYLAKE_SP)) const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 }; - const int ioapic_ids[] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0x10, 0x11, 0x12 }; #endif /* Local APICs */ current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; { - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, 0, 0, ioapic_id, + current += add_madt_ioapic(current, 0, 0, PCH_IOAPIC_ID, hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, gsi_base); ++cur_index; @@ -117,9 +113,8 @@ const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (ri->Personality != TYPE_UBOX_IIO) continue; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; + int ioapic_id = soc_get_iio_ioapicid(socket, stack); int gsi_base = gsi_bases[cur_index]; uint32_t ioapic_base = ri->IoApicBase; /* diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 07c454e..2ebc9f1 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -12,7 +12,7 @@ }; void get_iiostack_info(struct iiostack_resource *info); - +uint8_t soc_get_iio_ioapicid(int socket, int stack); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 9e7072e..c8f52f2 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -336,3 +336,24 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 6cb6828..f14064d 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -190,15 +190,6 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - int IoApicID[] = { - // socket 0 - PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, - PC04_IOAPIC_ID, PC05_IOAPIC_ID, - // socket 1 - PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, - PC10_IOAPIC_ID, PC11_IOAPIC_ID, - }; - uint32_t enum_id; unsigned long tmp = current; @@ -237,7 +228,7 @@ } // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = soc_get_iio_ioapicid(socket, stack); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 93481c9..ef48485 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -12,7 +12,7 @@ }; void get_iiostack_info(struct iiostack_resource *info); - +uint8_t soc_get_iio_ioapicid(int socket, int stack); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); void config_reset_cpl3_csrs(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index f9eddb2..97950d4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -421,4 +421,25 @@ else return -1; } + +uint8_t soc_get_iio_ioapicid(int socket, int stack) +{ + uint8_t ioapic_id = socket ? 0xf : 0x9; + switch (stack) { + case CSTACK: + break; + case PSTACK0: + ioapic_id += 1; + break; + case PSTACK1: + ioapic_id += 2; + break; + case PSTACK2: + ioapic_id += 3; + break; + default: + return 0xff; + } + return ioapic_id; +} #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Gerrit-Change-Number: 47302 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c`
by Angel Pons (Code Review) 16 Nov '20

16 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46797 ) Change subject: soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c` ...................................................................... soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c` Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc R src/soc/intel/broadwell/northbridge.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46797/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7ee6990..7d21665 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -17,11 +17,11 @@ romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +ramstage-y += northbridge.c ramstage-y += pei_data.c romstage-y += pei_data.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += systemagent.c CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/northbridge.c similarity index 100% rename from src/soc/intel/broadwell/systemagent.c rename to src/soc/intel/broadwell/northbridge.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a Gerrit-Change-Number: 46797 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: arch/x86/car.ld: Do cosmetic fixes
by Frans Hendriks (Code Review) 16 Nov '20

16 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47561 ) Change subject: arch/x86/car.ld: Do cosmetic fixes ...................................................................... arch/x86/car.ld: Do cosmetic fixes Make the code follow the coding style. Replace 8 spaces by TAB Move comment between the corresponding #if #endif Tested on Facebook FBG1701 Change-Id: I55cb071eb58a24f78e231cd36e6575fd13817e86 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/arch/x86/car.ld 1 file changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47561/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index eabe873..641d892 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -11,18 +11,17 @@ /* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB * aligned when using this option. */ _pagetables = . ; - . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; + . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES; _epagetables = . ; #endif +#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) /* Vboot work buffer only needs to be available when verified boot * starts in bootblock. */ -#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) VBOOT2_WORK(., 12K) #endif - /* Vboot measured boot TCPA log measurements. - * Needs to be transferred until CBMEM is available - */ #if CONFIG(TPM_MEASURED_BOOT) + /* Vboot measured boot TCPA log measurements. + * Needs to be transferred until CBMEM is available */ TPM_TCPA_LOG(., 2K) #endif /* Stack for CAR stages. Since it persists across all stages that @@ -33,8 +32,8 @@ _ecar_stack = .; /* The pre-ram cbmem console as well as the timestamp region are fixed * in size. Therefore place them above the car global section so that - * multiple stages (romstage and verstage) have a consistent - * link address of these shared objects. */ + * multiple stages (romstage and verstage) have a consistent + * link address of these shared objects. */ PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG(PAGING_IN_CACHE_AS_RAM) . = ALIGN(32); @@ -55,8 +54,8 @@ _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ - . += 80; - _ecar_ehci_dbg_info = .; + . += 80; + _ecar_ehci_dbg_info = .; /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram @@ -110,7 +109,7 @@ . = 0xffffff00; .illegal_globals . : { *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55cb071eb58a24f78e231cd36e6575fd13817e86 Gerrit-Change-Number: 47561 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Initialize mem_cfg in one line
by Angel Pons (Code Review) 16 Nov '20

16 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47566 ) Change subject: mb/supermicro/x11-lga1151-series: Initialize mem_cfg in one line ...................................................................... mb/supermicro/x11-lga1151-series: Initialize mem_cfg in one line Change-Id: I50390f66d9570eb0fd703e3ad8a2735125d76b61 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47566/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c index fd1c715..6763657 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/romstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c @@ -6,8 +6,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; - mem_cfg = &mupd->FspmConfig; + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50390f66d9570eb0fd703e3ad8a2735125d76b61 Gerrit-Change-Number: 47566 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: dedede: Create lantis variant
by Tony Huang (Code Review) 16 Nov '20

16 Nov '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47510 ) Change subject: dedede: Create lantis variant ...................................................................... dedede: Create lantis variant Create the lantis variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171546871 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_LANTIS Change-Id: Ie3d15a687b870afc7d8bbeb6b5cab0792650da31 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/lantis/include/variant/ec.h A src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h A src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc A src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/lantis/overridetree.cb 8 files changed, 185 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47510/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6da6505..095a575 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -96,6 +96,7 @@ default "Wheelie" if BOARD_GOOGLE_WHEELIE default "Magolor" if BOARD_GOOGLE_MAGOLOR default "Metaknight" if BOARD_GOOGLE_METAKNIGHT + default "Lantis" if BOARD_GOOGLE_LANTIS config MAX_CPUS int @@ -126,5 +127,6 @@ default "wheelie" if BOARD_GOOGLE_WHEELIE default "magolor" if BOARD_GOOGLE_MAGOLOR default "metaknight" if BOARD_GOOGLE_METAKNIGHT + default "lantis" if BOARD_GOOGLE_LANTIS endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 31495a1..4e107bc 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -72,3 +72,8 @@ bool "-> Metaknight" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_LANTIS + bool "-> Lantis" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt new file mode 100644 index 0000000..59381dc --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb new file mode 100644 index 0000000..25e29a1 --- /dev/null +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -0,0 +1,150 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Discrete Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Integrated Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)" + device usb 2.7 on end + end + end + end + end # USB xHCI + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end + end + end #I2C 0 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + end # I2C 2 + device pci 1c.7 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/47510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3d15a687b870afc7d8bbeb6b5cab0792650da31 Gerrit-Change-Number: 47510 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer
by Yidi Lin (Code Review) 16 Nov '20

16 Nov '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46401 to review the following change. Change subject: soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer ...................................................................... soc/mediatek/mt8192: Reserved 44K SRAM for mcupm working buffer Reserved region is 0x00115000 ~ 0x0011ffff and reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5 --- M src/soc/mediatek/mt8192/include/soc/memlayout.ld 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46401/1 diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 3bef5b1..20aa431 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -21,12 +21,12 @@ TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) - PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) - TIMESTAMP(0x00113c00, 1K) - STACK(0x00114000, 16K) - TTB(0x00118000, 28K) - DMA_COHERENT(0x0011f000, 4K) - SRAM_END(0x00120000) + PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4) + TIMESTAMP(0x00108c00, 1K) + STACK(0x00109000, 16K) + TTB(0x0010d000, 28K) + DMA_COHERENT(0x00114000, 4K) + SRAM_END(0x00115000) SRAM_L2C_START(0x00200000) BOOTBLOCK(0x00201000, 64K) -- To view, visit https://review.coreboot.org/c/coreboot/+/46401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5 Gerrit-Change-Number: 46401 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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