coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: util/cbfstool/amdcompress: fix short option for maxsize
by Felix Held (Code Review) 15 Nov '20

15 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47574 ) Change subject: util/cbfstool/amdcompress: fix short option for maxsize ...................................................................... util/cbfstool/amdcompress: fix short option for maxsize Both the help and the maxsize option had the same short option character assigned. Change the short option for maxsize to m to fix this and to make it consistent with the rest of the code. Change-Id: Icac1a7d4906345c37a5c7bed2b4995fea25f860e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/cbfstool/amdcompress.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47574/1 diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c index eae347f..2a1d5c6 100644 --- a/util/cbfstool/amdcompress.c +++ b/util/cbfstool/amdcompress.c @@ -30,7 +30,7 @@ {"infile", required_argument, 0, 'i' }, {"outfile", required_argument, 0, 'o' }, {"compress", no_argument, 0, 'c' }, - {"maxsize", required_argument, 0, 'h' }, + {"maxsize", required_argument, 0, 'm' }, {"uncompress", no_argument, 0, 'u' }, {"help", no_argument, 0, 'h' }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icac1a7d4906345c37a5c7bed2b4995fea25f860e Gerrit-Change-Number: 47574 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [WIP] soc/amd/common: factor out SMU code from Picasso
by Felix Held (Code Review) 15 Nov '20

15 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47483 ) Change subject: [WIP] soc/amd/common: factor out SMU code from Picasso ...................................................................... [WIP] soc/amd/common: factor out SMU code from Picasso The SMU mailbox access code from Picasso can be reused in the next generation, so factor out the code to soc/amd/common/block/smu. The message ID argument of the send_smu_message function is changed from the SoC specific smu_message_id enum to an uint32_t to avoid including the SoC-specific header file in the common SMU header file. The patch is still WIP, since I'm still undecided if it's a bad idea to include the SoC's pci_devs.h in the common SMU code for the definition of SOC_GNB_DEV. It's also still untested on google/zork. Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/include/amdblocks/smu.h A src/soc/amd/common/block/smu/Kconfig A src/soc/amd/common/block/smu/Makefile.inc A src/soc/amd/common/block/smu/smu.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/smu.h M src/soc/amd/picasso/smu.c 7 files changed, 117 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47483/1 diff --git a/src/soc/amd/common/block/include/amdblocks/smu.h b/src/soc/amd/common/block/include/amdblocks/smu.h new file mode 100644 index 0000000..ffc0d7a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/smu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __AMDBLOCKS_SMU_H__ +#define __AMDBLOCKS_SMU_H__ + +#include <types.h> + +/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ +#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ +#define SMU_DATA_ADDR 0xbc /* 32 bit */ + +#define REG_ADDR_MESG_ID 0x3b10528 +#define REG_ADDR_MESG_RESP 0x3b10564 +#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 + +/* Argument 0-5 indexed locations are contiguous */ +#define SMU_NUM_ARGS 6 +#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) + +struct smu_payload { + uint32_t msg[SMU_NUM_ARGS]; +}; + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if + * any, is returned via arg. Returns 0 if success or -1 on failure. + */ +enum cb_err send_smu_message(uint32_t message_id, struct smu_payload *arg); + +#endif /* __AMDBLOCKS_SMU_H__ */ diff --git a/src/soc/amd/common/block/smu/Kconfig b/src/soc/amd/common/block/smu/Kconfig new file mode 100644 index 0000000..60c231f --- /dev/null +++ b/src/soc/amd/common/block/smu/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SMU + bool + default n + help + Select this option to add functions to communicate with the SMU to the build. diff --git a/src/soc/amd/common/block/smu/Makefile.inc b/src/soc/amd/common/block/smu/Makefile.inc new file mode 100644 index 0000000..2afd81a --- /dev/null +++ b/src/soc/amd/common/block/smu/Makefile.inc @@ -0,0 +1 @@ +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_SMU) += smu.c diff --git a/src/soc/amd/common/block/smu/smu.c b/src/soc/amd/common/block/smu/smu.c new file mode 100644 index 0000000..0d7b82b --- /dev/null +++ b/src/soc/amd/common/block/smu/smu.c @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <amdblocks/smu.h> +#include <types.h> + +static uint32_t smu_read32(uint32_t reg) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); +} + +static void smu_write32(uint32_t reg, uint32_t val) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); +} + +#define SMU_MESG_RESP_TIMEOUT 0x00 +#define SMU_MESG_RESP_OK 0x01 + +/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ +static int32_t smu_poll_response(bool print_command_duration) +{ + struct stopwatch sw; + const long timeout_ms = 10 * MSECS_PER_SEC; + int32_t result; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + result = smu_read32(REG_ADDR_MESG_RESP); + if (result) { + if (print_command_duration) + printk(BIOS_SPEW, "SMU command consumed %ld usecs\n", + stopwatch_duration_usecs(&sw)); + return result; + } + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + return SMU_MESG_RESP_TIMEOUT; +} + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via + * arg. + */ +enum cb_err send_smu_message(uint32_t message_id, struct smu_payload *arg) +{ + size_t i; + + /* wait until SMU can process a new request; don't care if an old request failed */ + if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT) + return CB_ERR; + + /* clear response register */ + smu_write32(REG_ADDR_MESG_RESP, 0); + + /* populate arguments */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); + + /* send message to SMU */ + smu_write32(REG_ADDR_MESG_ID, message_id); + + /* wait until SMU has processed the message and check if it was successful */ + if (smu_poll_response(true) != SMU_MESG_RESP_OK) + return CB_ERR; + + /* copy returned values */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); + + return CB_SUCCESS; +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5ae0a2a..9ebc651 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index eb7573c..b00a941 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -3,34 +3,10 @@ #ifndef __PICASSO_SMU_H__ #define __PICASSO_SMU_H__ -#include <types.h> - -/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ -#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ -#define SMU_DATA_ADDR 0xbc /* 32 bit */ - -#define REG_ADDR_MESG_ID 0x3b10528 -#define REG_ADDR_MESG_RESP 0x3b10564 -#define REG_ADDR_MESG_ARGS_BASE 0x3b10998 - -/* Argument 0-5 indexed locations are contiguous */ -#define SMU_NUM_ARGS 6 -#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) - enum smu_message_id { SMC_MSG_S3ENTRY = 0x0c, }; -struct smu_payload { - uint32_t msg[SMU_NUM_ARGS]; -}; - -/* - * Send a message and bi-directional payload to the SMU. SMU response, if - * any, is returned via arg. Returns 0 if success or -1 on failure. - */ -enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg); - /* * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines * S-State and SlpTypeEn is clear. Function does not return if successful. diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c index 4a373ce..34be4e8 100644 --- a/src/soc/amd/picasso/smu.c +++ b/src/soc/amd/picasso/smu.c @@ -1,82 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <timer.h> #include <console/console.h> -#include <device/pci_ops.h> -#include <soc/pci_devs.h> +#include <amdblocks/smu.h> #include <soc/smu.h> -#include <types.h> - -static uint32_t smu_read32(uint32_t reg) -{ - pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); - return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); -} - -static void smu_write32(uint32_t reg, uint32_t val) -{ - pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); - pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); -} - -#define SMU_MESG_RESP_TIMEOUT 0x00 -#define SMU_MESG_RESP_OK 0x01 - -/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ -static int32_t smu_poll_response(bool print_command_duration) -{ - struct stopwatch sw; - const long timeout_ms = 10 * MSECS_PER_SEC; - int32_t result; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - result = smu_read32(REG_ADDR_MESG_RESP); - if (result) { - if (print_command_duration) - printk(BIOS_SPEW, "SMU command consumed %ld usecs\n", - stopwatch_duration_usecs(&sw)); - return result; - } - } while (!stopwatch_expired(&sw)); - - printk(BIOS_ERR, "Error: timeout sending SMU message\n"); - return SMU_MESG_RESP_TIMEOUT; -} - -/* - * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via - * arg. - */ -enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) -{ - size_t i; - - /* wait until SMU can process a new request; don't care if an old request failed */ - if (smu_poll_response(false) == SMU_MESG_RESP_TIMEOUT) - return CB_ERR; - - /* clear response register */ - smu_write32(REG_ADDR_MESG_RESP, 0); - - /* populate arguments */ - for (i = 0 ; i < SMU_NUM_ARGS ; i++) - smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); - - /* send message to SMU */ - smu_write32(REG_ADDR_MESG_ID, id); - - /* wait until SMU has processed the message and check if it was successful */ - if (smu_poll_response(true) != SMU_MESG_RESP_OK) - return CB_ERR; - - /* copy returned values */ - for (i = 0 ; i < SMU_NUM_ARGS ; i++) - arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); - - return CB_SUCCESS; -} /* * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and -- To view, visit https://review.coreboot.org/c/coreboot/+/47483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7 Gerrit-Change-Number: 47483 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: [WIP] nb/intel/sandybridge: Add debug prints on fine rcven
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47618 ) Change subject: [WIP] nb/intel/sandybridge: Add debug prints on fine rcven ...................................................................... [WIP] nb/intel/sandybridge: Add debug prints on fine rcven Change-Id: Icad4db68b738d30d4b450b32af8ea7557f20a454 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/47618/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ec45a8e..9e60cf8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1281,6 +1281,17 @@ } } } + + printk(BIOS_ERR, "Channel %d results:\n", channel); + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (i = -25; i <= 25; i++) { + printk(BIOS_ERR, "% 5d\t", i); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", statistics[lane][i + 25] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { int last_zero, first_all; @@ -2424,6 +2435,16 @@ } } + printk(BIOS_ERR, "Channel %d results:\n", channel); + printk(BIOS_ERR, "DqsPI\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { + printk(BIOS_ERR, "% 5d\t", dqs_pi); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", stats[lane][dqs_pi] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; -- To view, visit https://review.coreboot.org/c/coreboot/+/47618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icad4db68b738d30d4b450b32af8ea7557f20a454 Gerrit-Change-Number: 47618 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/x86/smbios.c: Split out weak functions
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44023 ) Change subject: arch/x86/smbios.c: Split out weak functions ...................................................................... arch/x86/smbios.c: Split out weak functions The `smbios.c` file is rather long. To improve navigability, place weak function definitions on a separate compilation unit. Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/smbios.c A src/arch/x86/smbios_weak.c 3 files changed, 140 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44023/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00690ba0..f652ce1 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -255,6 +255,7 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c +ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios_weak.c ramstage-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index b572624..b2da33c 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -206,18 +206,6 @@ t->manufacturer = smbios_add_string(t->eos, string_buffer); } } -/* this function will fill the corresponding locator */ -__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) -{ - char locator[40]; - - snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", - dimm->channel_num, dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); - - snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); - t->bank_locator = smbios_add_string(t->eos, locator); -} static void trim_trailing_whitespace(char *buffer, size_t buffer_size) { @@ -405,11 +393,6 @@ return coreboot_version; } -__weak const char *smbios_mainboard_bios_version(void) -{ - return NULL; -} - static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -459,121 +442,6 @@ return len; } -__weak const char *smbios_mainboard_serial_number(void) -{ - return CONFIG_MAINBOARD_SERIAL_NUMBER; -} - -__weak const char *smbios_mainboard_version(void) -{ - return CONFIG_MAINBOARD_VERSION; -} - -__weak const char *smbios_mainboard_manufacturer(void) -{ - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; -} - -__weak const char *smbios_mainboard_product_name(void) -{ - return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; -} - -__weak const char *smbios_mainboard_asset_tag(void) -{ - return ""; -} - -__weak u8 smbios_mainboard_feature_flags(void) -{ - return 0; -} - -__weak const char *smbios_mainboard_location_in_chassis(void) -{ - return ""; -} - -__weak smbios_board_type smbios_mainboard_board_type(void) -{ - return SMBIOS_BOARD_TYPE_UNKNOWN; -} - -/* - * System Enclosure or Chassis Types as defined in SMBIOS specification. - * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, - * convertible, or tablet enclosure will be used if the appropriate - * system type is selected. - */ -__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) -{ - if (CONFIG(SYSTEM_TYPE_LAPTOP)) - return SMBIOS_ENCLOSURE_LAPTOP; - else if (CONFIG(SYSTEM_TYPE_TABLET)) - return SMBIOS_ENCLOSURE_TABLET; - else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) - return SMBIOS_ENCLOSURE_CONVERTIBLE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) - return SMBIOS_ENCLOSURE_DETACHABLE; - else - return SMBIOS_ENCLOSURE_DESKTOP; -} - -__weak const char *smbios_system_serial_number(void) -{ - return smbios_mainboard_serial_number(); -} - -__weak const char *smbios_system_version(void) -{ - return smbios_mainboard_version(); -} - -__weak const char *smbios_system_manufacturer(void) -{ - return smbios_mainboard_manufacturer(); -} - -__weak const char *smbios_system_product_name(void) -{ - return smbios_mainboard_product_name(); -} - -__weak void smbios_system_set_uuid(u8 *uuid) -{ - /* leave all zero */ -} - -__weak unsigned int smbios_cpu_get_max_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -__weak unsigned int smbios_cpu_get_current_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -__weak const char *smbios_system_sku(void) -{ - return ""; -} - -__weak const char *smbios_chassis_version(void) -{ - return ""; -} - -__weak const char *smbios_chassis_serial_number(void) -{ - return ""; -} - -__weak const char *smbios_processor_serial_number(void) -{ - return ""; -} - static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) diff --git a/src/arch/x86/smbios_weak.c b/src/arch/x86/smbios_weak.c new file mode 100644 index 0000000..22ce7a5 --- /dev/null +++ b/src/arch/x86/smbios_weak.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memory_info.h> +#include <smbios.h> +#include <stdint.h> +#include <string.h> + +/* this function will fill the corresponding locator */ +__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char locator[40]; + + snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", + dimm->channel_num, dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); + t->bank_locator = smbios_add_string(t->eos, locator); +} + +__weak const char *smbios_mainboard_bios_version(void) +{ + return NULL; +} + +__weak const char *smbios_mainboard_serial_number(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} + +__weak const char *smbios_mainboard_version(void) +{ + return CONFIG_MAINBOARD_VERSION; +} + +__weak const char *smbios_mainboard_manufacturer(void) +{ + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; +} + +__weak const char *smbios_mainboard_product_name(void) +{ + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +__weak const char *smbios_mainboard_asset_tag(void) +{ + return ""; +} + +__weak u8 smbios_mainboard_feature_flags(void) +{ + return 0; +} + +__weak const char *smbios_mainboard_location_in_chassis(void) +{ + return ""; +} + +__weak smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_UNKNOWN; +} + +/* + * System Enclosure or Chassis Types as defined in SMBIOS specification. + * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, + * convertible, or tablet enclosure will be used if the appropriate + * system type is selected. + */ +__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (CONFIG(SYSTEM_TYPE_LAPTOP)) + return SMBIOS_ENCLOSURE_LAPTOP; + else if (CONFIG(SYSTEM_TYPE_TABLET)) + return SMBIOS_ENCLOSURE_TABLET; + else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) + return SMBIOS_ENCLOSURE_DETACHABLE; + else + return SMBIOS_ENCLOSURE_DESKTOP; +} + +__weak const char *smbios_system_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +__weak const char *smbios_system_version(void) +{ + return smbios_mainboard_version(); +} + +__weak const char *smbios_system_manufacturer(void) +{ + return smbios_mainboard_manufacturer(); +} + +__weak const char *smbios_system_product_name(void) +{ + return smbios_mainboard_product_name(); +} + +__weak void smbios_system_set_uuid(u8 *uuid) +{ + /* leave all zero */ +} + +__weak unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak const char *smbios_system_sku(void) +{ + return ""; +} + +__weak const char *smbios_chassis_version(void) +{ + return ""; +} + +__weak const char *smbios_chassis_serial_number(void) +{ + return ""; +} + +__weak const char *smbios_processor_serial_number(void) +{ + return ""; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd2a4ba52b6b23aad8fd63e66ffa747d49ea713d Gerrit-Change-Number: 44023 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: Revert "arch/x86/smbios.c: Split out weak functions"
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47455 to review the following change. Change subject: Revert "arch/x86/smbios.c: Split out weak functions" ...................................................................... Revert "arch/x86/smbios.c: Split out weak functions" This reverts commit bea5ce7a4b5faf0a8c12565eb133456db1c099da. Reason for revert: Breaks some people's workflow. Change-Id: Ia09f25e64dfc46d230e7ec6faf335b1d04ee6f78 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/smbios.c D src/arch/x86/smbios_defaults.c 3 files changed, 132 insertions(+), 140 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47455/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 17ab3dc..00690ba0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -255,7 +255,6 @@ ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c -ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios_defaults.c ramstage-y += tables.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8c7f92c..1b51d90 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -205,6 +205,18 @@ t->manufacturer = smbios_add_string(t->eos, string_buffer); } } +/* this function will fill the corresponding locator */ +__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) +{ + char locator[40]; + + snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", + dimm->channel_num, dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); + t->bank_locator = smbios_add_string(t->eos, locator); +} static void trim_trailing_whitespace(char *buffer, size_t buffer_size) { @@ -392,6 +404,11 @@ return coreboot_version; } +__weak const char *smbios_mainboard_bios_version(void) +{ + return NULL; +} + static int smbios_write_type0(unsigned long *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; @@ -441,6 +458,121 @@ return len; } +__weak const char *smbios_mainboard_serial_number(void) +{ + return CONFIG_MAINBOARD_SERIAL_NUMBER; +} + +__weak const char *smbios_mainboard_version(void) +{ + return CONFIG_MAINBOARD_VERSION; +} + +__weak const char *smbios_mainboard_manufacturer(void) +{ + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; +} + +__weak const char *smbios_mainboard_product_name(void) +{ + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +__weak const char *smbios_mainboard_asset_tag(void) +{ + return ""; +} + +__weak u8 smbios_mainboard_feature_flags(void) +{ + return 0; +} + +__weak const char *smbios_mainboard_location_in_chassis(void) +{ + return ""; +} + +__weak smbios_board_type smbios_mainboard_board_type(void) +{ + return SMBIOS_BOARD_TYPE_UNKNOWN; +} + +/* + * System Enclosure or Chassis Types as defined in SMBIOS specification. + * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, + * convertible, or tablet enclosure will be used if the appropriate + * system type is selected. + */ +__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + if (CONFIG(SYSTEM_TYPE_LAPTOP)) + return SMBIOS_ENCLOSURE_LAPTOP; + else if (CONFIG(SYSTEM_TYPE_TABLET)) + return SMBIOS_ENCLOSURE_TABLET; + else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) + return SMBIOS_ENCLOSURE_CONVERTIBLE; + else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) + return SMBIOS_ENCLOSURE_DETACHABLE; + else + return SMBIOS_ENCLOSURE_DESKTOP; +} + +__weak const char *smbios_system_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +__weak const char *smbios_system_version(void) +{ + return smbios_mainboard_version(); +} + +__weak const char *smbios_system_manufacturer(void) +{ + return smbios_mainboard_manufacturer(); +} + +__weak const char *smbios_system_product_name(void) +{ + return smbios_mainboard_product_name(); +} + +__weak void smbios_system_set_uuid(u8 *uuid) +{ + /* leave all zero */ +} + +__weak unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + return 0; /* Unknown */ +} + +__weak const char *smbios_system_sku(void) +{ + return ""; +} + +__weak const char *smbios_chassis_version(void) +{ + return ""; +} + +__weak const char *smbios_chassis_serial_number(void) +{ + return ""; +} + +__weak const char *smbios_processor_serial_number(void) +{ + return ""; +} + static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c deleted file mode 100644 index 22ce7a5..0000000 --- a/src/arch/x86/smbios_defaults.c +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memory_info.h> -#include <smbios.h> -#include <stdint.h> -#include <string.h> - -/* this function will fill the corresponding locator */ -__weak void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t) -{ - char locator[40]; - - snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", - dimm->channel_num, dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); - - snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); - t->bank_locator = smbios_add_string(t->eos, locator); -} - -__weak const char *smbios_mainboard_bios_version(void) -{ - return NULL; -} - -__weak const char *smbios_mainboard_serial_number(void) -{ - return CONFIG_MAINBOARD_SERIAL_NUMBER; -} - -__weak const char *smbios_mainboard_version(void) -{ - return CONFIG_MAINBOARD_VERSION; -} - -__weak const char *smbios_mainboard_manufacturer(void) -{ - return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; -} - -__weak const char *smbios_mainboard_product_name(void) -{ - return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; -} - -__weak const char *smbios_mainboard_asset_tag(void) -{ - return ""; -} - -__weak u8 smbios_mainboard_feature_flags(void) -{ - return 0; -} - -__weak const char *smbios_mainboard_location_in_chassis(void) -{ - return ""; -} - -__weak smbios_board_type smbios_mainboard_board_type(void) -{ - return SMBIOS_BOARD_TYPE_UNKNOWN; -} - -/* - * System Enclosure or Chassis Types as defined in SMBIOS specification. - * The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop, - * convertible, or tablet enclosure will be used if the appropriate - * system type is selected. - */ -__weak smbios_enclosure_type smbios_mainboard_enclosure_type(void) -{ - if (CONFIG(SYSTEM_TYPE_LAPTOP)) - return SMBIOS_ENCLOSURE_LAPTOP; - else if (CONFIG(SYSTEM_TYPE_TABLET)) - return SMBIOS_ENCLOSURE_TABLET; - else if (CONFIG(SYSTEM_TYPE_CONVERTIBLE)) - return SMBIOS_ENCLOSURE_CONVERTIBLE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE)) - return SMBIOS_ENCLOSURE_DETACHABLE; - else - return SMBIOS_ENCLOSURE_DESKTOP; -} - -__weak const char *smbios_system_serial_number(void) -{ - return smbios_mainboard_serial_number(); -} - -__weak const char *smbios_system_version(void) -{ - return smbios_mainboard_version(); -} - -__weak const char *smbios_system_manufacturer(void) -{ - return smbios_mainboard_manufacturer(); -} - -__weak const char *smbios_system_product_name(void) -{ - return smbios_mainboard_product_name(); -} - -__weak void smbios_system_set_uuid(u8 *uuid) -{ - /* leave all zero */ -} - -__weak unsigned int smbios_cpu_get_max_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -__weak unsigned int smbios_cpu_get_current_speed_mhz(void) -{ - return 0; /* Unknown */ -} - -__weak const char *smbios_system_sku(void) -{ - return ""; -} - -__weak const char *smbios_chassis_version(void) -{ - return ""; -} - -__weak const char *smbios_chassis_serial_number(void) -{ - return ""; -} - -__weak const char *smbios_processor_serial_number(void) -{ - return ""; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/47455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia09f25e64dfc46d230e7ec6faf335b1d04ee6f78 Gerrit-Change-Number: 47455 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
by Srinidhi N Kaushik (Code Review) 15 Nov '20

15 Nov '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47555 ) Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ...................................................................... vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425. BUG=b:173160613 BRANCH=none TEST=build and boot delbin Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47555/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 6038b13..35cc43b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@ /** Offset 0x091C - Reserved **/ - UINT8 Reserved45[36]; + UINT8 Reserved45[44]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0940 +/** Offset 0x0948 **/ UINT8 UnusedUpdSpace27[6]; -/** Offset 0x0946 +/** Offset 0x094E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b7ef000..276ac79 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1058,10 +1058,10 @@ UINT16 ITbtDmaLtr[2]; /** Offset 0x04E2 - Enable/Disable CrashLog - Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + Deprecated. Move to PreMem $EN_DIS **/ - UINT8 CpuCrashLogEnable; + UINT8 DeprecatedCpuCrashLogEnable; /** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -2838,7 +2838,7 @@ /** Offset 0x0B95 - Configuration for boot TDP selection Deprecated. Move to premem. **/ - UINT8 ConfigTdpLevel; + UINT8 DeprecatedConfigTdpLevel; /** Offset 0x0B96 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F -- To view, visit https://review.coreboot.org/c/coreboot/+/47555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a Gerrit-Change-Number: 47555 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: enable ACPI CPPC entries
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47543 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: enable ACPI CPPC entries ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/47543/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47543/6//COMMIT_MSG@10 PS6, Line 10: > How would the test look like? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Gerrit-Change-Number: 47543 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Nov 2020 19:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: enable ACPI CPPC entries
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47543 to look at the new patch set (#8). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: enable ACPI CPPC entries ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: enable ACPI CPPC entries Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47543/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/47543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Gerrit-Change-Number: 47543 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/apl: enable ACPI CPPC entries
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Hello Felix Singer, build bot (Jenkins), Matt Delco, Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47542 to look at the new patch set (#8). Change subject: [UNTESTED] soc/intel/apl: enable ACPI CPPC entries ...................................................................... [UNTESTED] soc/intel/apl: enable ACPI CPPC entries Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: Ic94d95413d2f7f6743507824d47d5afd9fdfbbb9 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/apollolake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47542/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/47542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94d95413d2f7f6743507824d47d5afd9fdfbbb9 Gerrit-Change-Number: 47542 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/cnl: enable ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47541 ) Change subject: soc/intel/cnl: enable ACPI CPPC entries generation ...................................................................... soc/intel/cnl: enable ACPI CPPC entries generation Enable CPPC entries generation, needed for Intel SpeedShift. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7b9b88b..f427340 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -103,6 +103,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU -- To view, visit https://review.coreboot.org/c/coreboot/+/47541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6 Gerrit-Change-Number: 47541 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020