coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... soc/intel/common/block: add code for ACPI CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 5951b30..f0ff898 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpigen.h> +#include <arch/cpu.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <bootstate.h> @@ -9,6 +10,7 @@ #include <acpi/acpi_gnvs.h> #include <console/console.h> #include <cpu/intel/turbo.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/smm.h> #include <intelblocks/acpi.h> #include <intelblocks/msr.h> @@ -20,6 +22,8 @@ #include <soc/pm.h> #include <string.h> +#define CPUID_6_EAX_ISST (1 << 7) + __attribute__((weak)) unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -391,6 +395,23 @@ acpigen_write_TSS_package(entries, soc_tss_table); } +static void generate_cppc_entries(int core_id) +{ + if (!(CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && + cpuid_eax(6) & CPUID_6_EAX_ISST)) + return; + + /* Generate GCPC package in first logical core */ + if (core_id == 0) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, CPPC_VERSION_2); + acpigen_write_CPPC_package(&cppc_config); + } + + /* Write _CPC entry for each logical core */ + acpigen_write_CPPC_method(); +} + __weak void soc_power_states_generation(int core_id, int cores_per_package) { @@ -421,6 +442,8 @@ /* Generate C-state tables */ generate_c_state_entries(); + generate_cppc_entries(core_id); + /* Soc specific power states generation */ soc_power_states_generation(core_id, cores_per_package); -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 40 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Angel Pons (Code Review) 14 Nov '20

14 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 39: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 39 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Sat, 14 Nov 2020 18:42:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 14 Nov '20

14 Nov '20

Hello Felix Singer, Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#39). Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... soc/intel/common/block: add code for ACPI CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 39 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Angel Pons (Code Review) 14 Nov '20

14 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 53: (1 comment) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/acpi/cpld.asl: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 14: 0x0A80 > Increment this and the length so that you only need a single IO entry. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 53 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Nov 2020 16:56:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 14 Nov '20

14 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 53: (10 comments) > Patch Set 52: > > Yeah, no worries. I really meant "take over" not "run over" ^^ > Just wanted to let you know that you have more resources at > your disposal. We wouldn't want to start the review from > scratch. In any case, we'll add our variants on top of this. > > Beside the comments here, it would be nice if you could > rebase this change (and the reviewed one about carrier dirs) > directly on master. Other patches don't look absolutely > necessary (e.g. testing SMBus on windows... oO). > > Anyway, take your time. I just wanted to make sure this > doesn't stall indefinitely :) I really don't have a lot of time as I have high priority work on another project right now. Sorry if I hold down your research, but I should show this patch to Customer's company afther merged. I've made some fixes and suggest to add this "as it is" to continue working on the Kontron boards together in the next patches. What do you think about it? Thanks. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/Kconfig: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 28: This option sets the type of carrier board to be used with > https://doc.coreboot.org/coding_style. […] Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 29: kontron mal10 > Capitalize accordingly? This help text is meant for human consumption Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 29: come > COMe Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/ramstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 9: size_t > <stddef. […] Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/romstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 3: include <string.h> > not used Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/variants/mal10/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 5: # Enable VT-d > These comments say nothing useful. […] Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 101: # Set LPC Serial IRQ mode > Not much is gained from this comment either. Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 103: register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" : register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" > nit: place these within the corresponding devices? Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 115: register "sensor_mode.local_sensor_enable" = "1" : register "sensor_mode.rtd3" = "RTD_VOLTAGE_MODE" : register "sensor_mode.rtd2" = "RTD_VOLTAGE_MODE" : register "sensor_mode.rtd1" = "RTD_THERMISTOR_MODE" > I think something like this should work: […] Done https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 127: 0x5F > I've never seen a weather forecast specify temperatures in hex. I wonder why. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 53 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Nov 2020 16:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 14 Nov '20

14 Nov '20

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entry
by Arthur Heymans (Code Review) 14 Nov '20

14 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47301 ) Change subject: soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entry ...................................................................... soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entry The PCH IOAPIC ID is 0x8 so it needs to be generated before the IIO IOAPICs. Since we will get rid of the ioapic_id array this makes it more readable. Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/acpi.c 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47301/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index fcd5f00..c70945a 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -101,6 +101,16 @@ current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; + { + assert(cur_index < ARRAY_SIZE(ioapic_ids)); + assert(cur_index < ARRAY_SIZE(gsi_bases)); + int ioapic_id = ioapic_ids[cur_index]; + int gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, 0, 0, ioapic_id, + hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase, + gsi_base); + ++cur_index; + } for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { @@ -111,22 +121,17 @@ assert(cur_index < ARRAY_SIZE(gsi_bases)); int ioapic_id = ioapic_ids[cur_index]; int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, socket, stack, ioapic_id, ri->IoApicBase, gsi_base); - ++cur_index; - + uint32_t ioapic_base = ri->IoApicBase; /* * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. * Add entry for PCH IOAPIC. */ - if (stack == 0 && socket == 0) { /* PCH IOAPIC */ - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, socket, stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); - ++cur_index; - } + if (stack == 0 && socket == 0) + ioapic_base += 0x1000; + + current += add_madt_ioapic(current, socket, stack, ioapic_id, ioapic_base, + gsi_base); + ++cur_index; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf Gerrit-Change-Number: 47301 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: util/intelp2m: Clean up SCI, SMI macro generation and update comments
by Maxim Polyakov (Code Review) 14 Nov '20

14 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47314 ) Change subject: util/intelp2m: Clean up SCI, SMI macro generation and update comments ...................................................................... Patch Set 5: Code-Review+2 Tested in CB:43411 -- To view, visit https://review.coreboot.org/c/coreboot/+/47314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Gerrit-Change-Number: 47314 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Nov 2020 11:18:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Angel Pons (Code Review) 14 Nov '20

14 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 38: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… PS37, Line 400: GCPC > no, see https://review.coreboot.org/c/coreboot/+/46465/22/src/acpi/acpigen. […] Then I'd say "GCPC package". -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 38 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Sat, 14 Nov 2020 10:44:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 14 Nov '20

14 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 27: > Patch Set 27: > > Arthur, > Which piece of code is not working for CPU save state? You can also email me directly. rphagura(a)fb.com. Thx Coreboot has some code to access the save state per CPU, but makes some assumptions on where that save state is located (smmloaderv1). https://review.coreboot.org/c/coreboot/+/47081/ is a naive attempt on fixing it. Those save state accessors are not used on xeon_sp at the moment so it is not urgent to fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 27 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Nov 2020 08:59:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020