coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/volteer: Goodix touch panel power-on sequence tuning
by Nick Chen (Code Review) 16 Nov '20

16 Nov '20

Nick Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47502 ) Change subject: mb/google/volteer: Goodix touch panel power-on sequence tuning ...................................................................... mb/google/volteer: Goodix touch panel power-on sequence tuning 1. GPP_E3 PAD_CFG_GPO(GPP_E3, 0, DEEP) 2. generic.reset_delay_ms change to 30 Signed-off-by: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Change-Id: I90ca39312252c668da6298183e598392bc9f9f28 --- M src/mainboard/google/volteer/variants/eldrid/gpio.c M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47502/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 3d627e3..24f80a0 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -80,7 +80,7 @@ /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), /* E3 : CPU_GP0 ==> USI_REPORT_EN */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ PAD_CFG_GPI(GPP_E4, NONE, DEEP), /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 91fbbea..4ec9f37 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -123,7 +123,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "30" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" register "generic.enable_delay_ms" = "12" -- To view, visit https://review.coreboot.org/c/coreboot/+/47502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ca39312252c668da6298183e598392bc9f9f28 Gerrit-Change-Number: 47502 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: arch/x86/smbios: Update memory_array_handle for SMBIOS type 19
by Tim Chu (Code Review) 16 Nov '20

16 Nov '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47156 ) Change subject: arch/x86/smbios: Update memory_array_handle for SMBIOS type 19 ...................................................................... arch/x86/smbios: Update memory_array_handle for SMBIOS type 19 Update memory array handle for SMBIOS type 19. TEST=Execute "dmidecode -t 19" to check if memory array handle is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I49078b870bac3c6162913b91651ec09632800f1f --- M src/arch/x86/smbios.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47156/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 2995ece..e50e5ae 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -1023,7 +1023,7 @@ return totallen; } -static int smbios_write_type19(unsigned long *current, int *handle) +static int smbios_write_type19(unsigned long *current, int *handle, int type16) { struct smbios_type19 *t = (struct smbios_type19 *)*current; int len = sizeof(struct smbios_type19); @@ -1039,6 +1039,7 @@ t->type = SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS; t->length = len - 2; t->handle = *handle; + t->memory_array_handle = type16; for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) { if (meminfo->dimm[i].dimm_size > 0) { @@ -1290,7 +1291,7 @@ const int type16 = handle; update_max(len, max_struct_size, smbios_write_type16(&current, &handle)); update_max(len, max_struct_size, smbios_write_type17(&current, &handle, type16)); - update_max(len, max_struct_size, smbios_write_type19(&current, &handle)); + update_max(len, max_struct_size, smbios_write_type19(&current, &handle, type16)); update_max(len, max_struct_size, smbios_write_type32(&current, handle++)); update_max(len, max_struct_size, smbios_walk_device_tree(all_devices, -- To view, visit https://review.coreboot.org/c/coreboot/+/47156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49078b870bac3c6162913b91651ec09632800f1f Gerrit-Change-Number: 47156 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/zork: Init fingerprint GPIOs for boot vs resume
by Martin Roth (Code Review) 16 Nov '20

16 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47308 ) Change subject: mb/google/zork: Init fingerprint GPIOs for boot vs resume ...................................................................... mb/google/zork: Init fingerprint GPIOs for boot vs resume Add a function that initializes GPIOs based on the sleep type that the system is coming back from. This allows initialization of the fingerprint GPIOs which need to be handled differently between wake from S3 and boot from S5. If fingerprint is disabled on the trembyle board, set the pins to no-connect. Dalboz doesn't have fingerprint and the GPIOS are configured differently due to the FT5 chip having fewer GPIOS than FP5, so nothing needs to be initialized there. There were also a couple of trivial comment clean ups regarding the FPMCU GPIOS. BUG=b:171837716 TEST=Boot & Check GPIO states. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Id40bc952b4f6b87493a637e0bf12a5579c736b87 Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a --- M src/mainboard/google/zork/bootblock.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/ezkinil/gpio.c M src/mainboard/google/zork/variants/woomax/gpio.c 6 files changed, 47 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47308/1 diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index a7636de..af071b2 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -2,12 +2,16 @@ #include <bootblock_common.h> #include <baseboard/variants.h> +#include <acpi/acpi.h> void bootblock_mainboard_early_init(void) { size_t num_gpios; const struct soc_amd_gpio *gpios; + gpios=variant_poweron_gpio_table(&num_gpios, acpi_get_sleep_type()); + program_gpios(gpios, num_gpios); + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { gpios = variant_early_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 2398d07..e538aef 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,7 +30,7 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ + /* S0iX SLP - (unused - goes to EC */ PAD_NC(GPIO_10), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), @@ -291,6 +291,12 @@ wifi_power_reset_configure_pre_v3(); } +const __weak struct soc_amd_gpio *variant_poweron_gpio_table(size_t *size, int slp_typ) +{ + *size = 0; + return NULL; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a436d1c..74e7ed2 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <delay.h> #include <gpio.h> @@ -32,8 +33,6 @@ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_NC(GPIO_10), - /* FPMCU_RST_L */ - PAD_GPO(GPIO_11, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -71,8 +70,6 @@ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), - /* EN_PWR_FP */ - PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -87,7 +84,7 @@ PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic /* EMMC_RESET_L */ PAD_GPO(GPIO_68, HIGH), - /* FPMCU_BOOT0 - TODO: Check this */ + /* FPMCU_BOOT0 */ PAD_GPO(GPIO_69, LOW), /* EMMC_CLK */ PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), @@ -300,6 +297,34 @@ wifi_power_reset_configure_pre_v3(); } +static const struct soc_amd_gpio gpio_fingerprint_poweron_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_poweron_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_poweron_gpio_table(size_t *size, int slp_typ) +{ + if (variant_init_fingerprint()) { + if (slp_typ != ACPI_S0) { + return NULL; + } + *size = ARRAY_SIZE(gpio_fingerprint_poweron_table); + return gpio_fingerprint_poweron_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_poweron_table); + return gpio_no_fingerprint_poweron_table; +} + static const struct soc_amd_gpio gpio_sleep_table[] = { /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 338b918..5c040d3 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -25,6 +25,12 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); /* + * This function provides GPIO table for the pads that need to be configured when + * powering on because of reset, powering on, or resuming from S3. + */ +const struct soc_amd_gpio *variant_poweron_gpio_table(size_t *size, int slp_typ); + +/* * This function provides GPIO table for the pads that need to be configured when entering * sleep. */ diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index d2dd104..f86d926 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -37,8 +37,6 @@ PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* DMIC_SEL */ PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* EN_PWR_WIFI */ @@ -62,8 +60,6 @@ PAD_NC(GPIO_4), /* PEN_POWER_EN - Not connected */ PAD_NC(GPIO_5), - /* FPMCU_RST_L Change NC */ - PAD_NC(GPIO_11), /* FPMCU_BOOT0 Change NC */ PAD_NC(GPIO_69), /* EN_DEV_BEEP_L */ diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index cb98df7..329e7dd 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -10,10 +10,6 @@ PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ @@ -37,10 +33,6 @@ PAD_NC(GPIO_5), /* GPIO_6 NC */ PAD_NC(GPIO_6), - /* GPIO_11 NC */ - PAD_NC(GPIO_11), - /* GPIO_32 NC */ - PAD_NC(GPIO_32), /* GPIO_69 NC */ PAD_NC(GPIO_69), /* RAM_ID_4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a Gerrit-Change-Number: 47308 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 28

Change in coreboot[master]: src: Change bare 'unsigned' to 'unsigned int'
by Martin Roth (Code Review) 16 Nov '20

16 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47482 ) Change subject: src: Change bare 'unsigned' to 'unsigned int' ...................................................................... src: Change bare 'unsigned' to 'unsigned int' This fixes all of the current code in coreboot/src where a bare unsigned is used incorrectly. A follow-on will fix the comments so that we can enable the unsigned lint checker for src/coreboot. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb --- M src/include/device/dram/ddr2.h M src/soc/rockchip/rk3399/include/soc/sdram.h 2 files changed, 51 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47482/1 diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 9acf794..6200fde 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -47,35 +47,35 @@ * We do not care how these bits are ordered */ struct { /* Module can work at 5.00V */ - unsigned operable_5_00V:1; + unsigned int operable_5_00V:1; /* Module can work at 3.33V */ - unsigned operable_3_33V:1; + unsigned int operable_3_33V:1; /* Module can work at 2.50V */ - unsigned operable_2_50V:1; + unsigned int operable_2_50V:1; /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ - unsigned operable_1_80V:1; + unsigned int operable_1_80V:1; /* Module can work at 1.50V */ - unsigned operable_1_50V:1; + unsigned int operable_1_50V:1; /* Module can work at 1.35V */ - unsigned operable_1_35V:1; + unsigned int operable_1_35V:1; /* Module can work at 1.20V */ - unsigned operable_1_25V:1; + unsigned int operable_1_25V:1; /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ - unsigned is_ecc:1; + unsigned int is_ecc:1; /* Supports weak driver */ - unsigned weak_driver:1; + unsigned int weak_driver:1; /* Supports terminating at 50 Ohm */ - unsigned terminate_50ohms:1; + unsigned int terminate_50ohms:1; /* Partial Array Self Refresh */ - unsigned pasr:1; + unsigned int pasr:1; /* Supports burst length 8 */ - unsigned bl8:1; + unsigned int bl8:1; /* Supports burst length 4 */ - unsigned bl4:1; + unsigned int bl4:1; /* DIMM Package is stack */ - unsigned stacked:1; + unsigned int stacked:1; /* the assembly supports self refresh */ - unsigned self_refresh:1; + unsigned int self_refresh:1; }; unsigned int raw; }; diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 29d1452..c00766a 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -27,66 +27,66 @@ union noc_ddrtiminga0 { u32 d32; struct { - unsigned acttoact : 6; - unsigned reserved0 : 2; - unsigned rdtomiss : 6; - unsigned reserved1 : 2; - unsigned wrtomiss : 6; - unsigned reserved2 : 2; - unsigned readlatency : 8; + unsigned int acttoact : 6; + unsigned int reserved0 : 2; + unsigned int rdtomiss : 6; + unsigned int reserved1 : 2; + unsigned int wrtomiss : 6; + unsigned int reserved2 : 2; + unsigned int readlatency : 8; } b; }; union noc_ddrtimingb0 { u32 d32; struct { - unsigned rdtowr : 5; - unsigned reserved0 : 3; - unsigned wrtord : 5; - unsigned reserved1 : 3; - unsigned rrd : 4; - unsigned reserved2 : 4; - unsigned faw : 6; - unsigned reserved3 : 2; + unsigned int rdtowr : 5; + unsigned int reserved0 : 3; + unsigned int wrtord : 5; + unsigned int reserved1 : 3; + unsigned int rrd : 4; + unsigned int reserved2 : 4; + unsigned int faw : 6; + unsigned int reserved3 : 2; } b; }; union noc_ddrtimingc0 { u32 d32; struct { - unsigned burstpenalty : 4; - unsigned reserved0 : 4; - unsigned wrtomwr : 6; - unsigned reserved1 : 18; + unsigned int burstpenalty : 4; + unsigned int reserved0 : 4; + unsigned int wrtomwr : 6; + unsigned int reserved1 : 18; } b; }; union noc_devtodev0 { u32 d32; struct { - unsigned busrdtord : 3; - unsigned reserved0 : 1; - unsigned busrdtowr : 3; - unsigned reserved1 : 1; - unsigned buswrtord : 3; - unsigned reserved2 : 1; - unsigned buswrtowr : 3; - unsigned reserved3 : 17; + unsigned int busrdtord : 3; + unsigned int reserved0 : 1; + unsigned int busrdtowr : 3; + unsigned int reserved1 : 1; + unsigned int buswrtord : 3; + unsigned int reserved2 : 1; + unsigned int buswrtowr : 3; + unsigned int reserved3 : 17; } b; }; union noc_ddrmode { u32 d32; struct { - unsigned autoprecharge : 1; - unsigned bypassfiltering : 1; - unsigned fawbank : 1; - unsigned burstsize : 2; - unsigned mwrsize : 2; - unsigned reserved2 : 1; - unsigned forceorder : 8; - unsigned forceorderstate : 8; - unsigned reserved3 : 8; + unsigned int autoprecharge : 1; + unsigned int bypassfiltering : 1; + unsigned int fawbank : 1; + unsigned int burstsize : 2; + unsigned int mwrsize : 2; + unsigned int reserved2 : 1; + unsigned int forceorder : 8; + unsigned int forceorderstate : 8; + unsigned int reserved3 : 8; } b; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f34a95bb1894e70cd9e076d4b81ebac665eaeb Gerrit-Change-Number: 47482 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch
by Johnny Lin (Code Review) 16 Nov '20

16 Nov '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47494 ) Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch ...................................................................... vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatch Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/47494/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index dc870f1..1a4023f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -147,7 +147,7 @@ UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved4[2213]; + UINT8 reserved4[2216]; MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved5[1603]; -- To view, visit https://review.coreboot.org/c/coreboot/+/47494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb Gerrit-Change-Number: 47494 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: commonlib: Add timestamp values for forced delays.
by Martin Roth (Code Review) 16 Nov '20

16 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47312 ) Change subject: commonlib: Add timestamp values for forced delays. ...................................................................... commonlib: Add timestamp values for forced delays. Add a timestamp entry to allow forced delays to to be seen and accounted for in the timestamp data. BUG=None TEST=Build only Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I26c9fa5c8599a349de2631ac24b9ea8858d8d6c8 --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47312/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index dd352ad..a572150 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -52,6 +52,8 @@ TS_SELFBOOT_JUMP = 99, TS_START_POSTCAR = 100, TS_END_POSTCAR = 101, + TS_DELAY_START = 110, + TS_DELAY_END = 111, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ TS_START_COPYVER = 501, @@ -177,6 +179,8 @@ { TS_LOAD_PAYLOAD, "load payload" }, { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, { TS_SELFBOOT_JUMP, "selfboot jump" }, + { TS_DELAY_START, "Forced delay start" }, + { TS_DELAY_END, "Forced delay end" }, { TS_START_COPYVER, "starting to load verstage" }, { TS_END_COPYVER, "finished loading verstage" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c9fa5c8599a349de2631ac24b9ea8858d8d6c8 Gerrit-Change-Number: 47312 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
by David Wu (Code Review) 16 Nov '20

16 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47351 ) Change subject: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs ...................................................................... mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. H9HCNNNCRMBLPR-NEE 2. H9HCNNNFBMBLPR-NEE 3. MT53D1G64D4NW-046 WT:A BUG=b:172751925 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34 --- M src/mainboard/google/volteer/variants/voema/memory/Makefile.inc M src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt 3 files changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/47351/1 diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc index 3c8ea48..7b69aa4 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -2,5 +2,6 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E -SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E, H9HCNNNFBMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53D1G64D4NW-046 WT:A diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt index 02e7443..840f71a 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -1,3 +1,6 @@ DRAM Part Name ID to assign MT53E512M64D4NW-046 WT:E 0 (0000) MT53E1G64D8NW-046 WT:E 1 (0001) +H9HCNNNCRMBLPR-NEE 0 (0000) +H9HCNNNFBMBLPR-NEE 1 (0001) +MT53D1G64D4NW-046 WT:A 2 (0010) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index b74da4a..c74fe43 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,2 +1,5 @@ MT53E512M64D4NW-046 WT:E MT53E1G64D8NW-046 WT:E +H9HCNNNCRMBLPR-NEE +H9HCNNNFBMBLPR-NEE +MT53D1G64D4NW-046 WT:A -- To view, visit https://review.coreboot.org/c/coreboot/+/47351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic832155448fb07152b906aa04ca49d384ec47b34 Gerrit-Change-Number: 47351 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs
by David Wu (Code Review) 16 Nov '20

16 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47350 ) Change subject: lp4x: Add new memory parts and generate SPDs ...................................................................... lp4x: Add new memory parts and generate SPDs This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. H9HCNNNCRMBLPR-NEE 2. H9HCNNNFBMBLPR-NEE 3. MT53D1G64D4NW-046 WT:A BUG=b:172751925 TEST=build. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I37702770f707fe078920694468552c5db59c478f --- M src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47350/1 diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index 70877d2..c7e9690 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -13,3 +13,6 @@ K4UBE3D4AA-MGCR,lp4x-spd-3.hex MT53E512M64D4NW-046 WT:E,lp4x-spd-1.hex MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex +H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex +H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex +MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 109fadb..91062d0 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -181,6 +181,42 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "H9HCNNNCRMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "H9HCNNNFBMBLPR-NEE", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } + }, + { + "name": "MT53D1G64D4NW-046 WT:A", + "attribs": { + "densityPerChannelGb": 16, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/47350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37702770f707fe078920694468552c5db59c478f Gerrit-Change-Number: 47350 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: drivers/i2c/dw: Check for TX_ABORT in transfer
by Kangheui Won (Code Review) 16 Nov '20

16 Nov '20

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47360 ) Change subject: drivers/i2c/dw: Check for TX_ABORT in transfer ...................................................................... drivers/i2c/dw: Check for TX_ABORT in transfer When the host sends data in i2c bus, device might not send ACK. It means that data is not processed on the device side, but for now we don't check for that condition thus wait for the response which will not come. Designware i2c detect such situation and set TX_ABORT bit. Checking for the bit will enable other layers to immediately retry rather than wait-timeout-retry cycle. BUG=b:168838505 BRANCH=zork TEST=test on zork devices, now we see "Tx abort detected" instead of I2C timeout for tpm initializtion. Change-Id: Ib0163fbce55ccc99f677dbb096f67a58d2ef2bda --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47360/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 3181e7a..5601bcf 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -419,6 +419,14 @@ /* Read to clear INTR_STAT_STOP_DET */ read32(&regs->clear_stop_det_intr); + /* Check TX abort */ + if (read32(&regs->raw_intr_stat) & INTR_STAT_TX_ABORT) { + printk(BIOS_ERR, "I2C TX abort detected\n"); + /* clear INTR_STAT_TX_ABORT */ + read32(&regs->clear_tx_abrt_intr); + goto out; + } + /* Wait for the bus to go idle */ if (dw_i2c_wait_for_bus_idle(regs)) { printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); @@ -747,8 +755,8 @@ write32(&regs->rx_thresh, 0); write32(&regs->tx_thresh, 0); - /* Enable stop detection interrupt */ - write32(&regs->intr_mask, INTR_STAT_STOP_DET); + /* Enable stop detection and TX abort interrupt */ + write32(&regs->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT); printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n", bus, regs, speed / KHz); -- To view, visit https://review.coreboot.org/c/coreboot/+/47360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0163fbce55ccc99f677dbb096f67a58d2ef2bda Gerrit-Change-Number: 47360 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/volteer/var/voxel: change elan touchscreen interrupt to LEV...
by Sheng-Liang Pan (Code Review) 16 Nov '20

16 Nov '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46624 ) Change subject: mb/google/volteer/var/voxel: change elan touchscreen interrupt to LEVEL trigger ...................................................................... mb/google/volteer/var/voxel: change elan touchscreen interrupt to LEVEL trigger change elan touchscreen interrupt to LEVEL trigger to pass uniformity test. BUG=b:169632772 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Id0272d9a4796da9479bd06c74d0c68b1ce6069b3 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46624/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b..5aa006b 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -116,7 +116,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" -- To view, visit https://review.coreboot.org/c/coreboot/+/46624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0272d9a4796da9479bd06c74d0c68b1ce6069b3 Gerrit-Change-Number: 46624 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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