coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: MAINTAINERS: add maintainers of soc/amd/picassso
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47577 ) Change subject: MAINTAINERS: add maintainers of soc/amd/picassso ...................................................................... MAINTAINERS: add maintainers of soc/amd/picassso Change-Id: Id39bd55a9a05b062892defadeb652980213b1e9c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M MAINTAINERS 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47577/1 diff --git a/MAINTAINERS b/MAINTAINERS index 9a31a3f..fa8b492 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,14 @@ # Systems on a Chip ################################################################################ +AMD Picasso +M: Marshall Dawson <marshalldawson3rd(a)gmail.com> +M: Felix Held <felix-coreboot(a)felixheld.de> +M: Jason Glenesk <jason.glenesk(a)gmail.com> +S: Maintained +F: /src/soc/amd/picasso +F: /src/vendorcode/amd/fsp/picasso + INTEL APOLLOLAKE_SOC M: Andrey Petrov <andrey.petrov(a)gmail.com> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/47577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id39bd55a9a05b062892defadeb652980213b1e9c Gerrit-Change-Number: 47577 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/amd/common/block: drop double underscores from include guards
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47583 ) Change subject: soc/amd/common/block: drop double underscores from include guards ...................................................................... soc/amd/common/block: drop double underscores from include guards Since coreboot is written in C and not C++, having the double underscores as a prefix is not an issue, but it also doesn't add much information, so drop them and the trailing ones as well. Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/common/block/include/amdblocks/agesawrapper.h M src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h M src/soc/amd/common/block/include/amdblocks/alink.h M src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/include/amdblocks/biosram.h M src/soc/amd/common/block/include/amdblocks/car.h M src/soc/amd/common/block/include/amdblocks/chip.h M src/soc/amd/common/block/include/amdblocks/dimm_spd.h M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/hda.h M src/soc/amd/common/block/include/amdblocks/image.h M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/include/amdblocks/pci_devs.h M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/include/amdblocks/s3_resume.h M src/soc/amd/common/block/include/amdblocks/sata.h M src/soc/amd/common/block/include/amdblocks/smu.h M src/soc/amd/common/block/include/amdblocks/spi.h 25 files changed, 75 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47583/1 diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 5422323..e7d3260 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CALLOUTS_AGESA_H__ -#define __AMD_BLOCK_CALLOUTS_AGESA_H__ +#ifndef AMD_BLOCK_CALLOUTS_AGESA_H +#define AMD_BLOCK_CALLOUTS_AGESA_H #include <amdblocks/agesawrapper.h> #include <stdint.h> @@ -69,4 +69,4 @@ extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; extern const int BiosCalloutsLen; -#endif /* __AMD_BLOCK_CALLOUTS_AGESA_H__ */ +#endif /* AMD_BLOCK_CALLOUTS_AGESA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 7a9206d..c6e242a 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ACPI_H__ -#define __AMD_BLOCK_ACPI_H__ +#ifndef AMD_BLOCK_ACPI_H +#define AMD_BLOCK_ACPI_H #include <types.h> #include <soc/nvs.h> @@ -44,4 +44,4 @@ void acpi_enable_sci(void); void acpi_disable_sci(void); -#endif /* __AMD_BLOCK_ACPI_H__ */ +#endif /* AMD_BLOCK_ACPI_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 6d96fcd..932ae47 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMD_BLOCK_ACPIMMIO_H__ -#define __AMD_BLOCK_ACPIMMIO_H__ +#ifndef AMD_BLOCK_ACPIMMIO_H +#define AMD_BLOCK_ACPIMMIO_H #include <device/mmio.h> #include <types.h> @@ -508,4 +508,4 @@ write8(acpimmio_aoac + reg, value); } -#endif /* __AMD_BLOCK_ACPIMMIO_H__ */ +#endif /* AMD_BLOCK_ACPIMMIO_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 0e80ff4..abf014c 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __AMD_BLOCK_ACPIMMIO_MAP_H__ -#define __AMD_BLOCK_ACPIMMIO_MAP_H__ +#ifndef AMD_BLOCK_ACPIMMIO_MAP_H +#define AMD_BLOCK_ACPIMMIO_MAP_H /* * The following AcpiMmio register block mapping represents definitions @@ -132,4 +132,4 @@ #endif -#endif /* __AMD_BLOCK_ACPIMMIO_MAP_H__ */ +#endif /* AMD_BLOCK_ACPIMMIO_MAP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index 85505d1c..8c08ba0 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_AGESAWRAPPER_H__ -#define __AMD_BLOCK_AGESAWRAPPER_H__ +#ifndef AMD_BLOCK_AGESAWRAPPER_H +#define AMD_BLOCK_AGESAWRAPPER_H #include <agesa_headers.h> @@ -39,4 +39,4 @@ void set_board_env_params(GNB_ENV_CONFIGURATION *params); void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly); -#endif /* __AMD_BLOCK_AGESAWRAPPER_H__ */ +#endif /* AMD_BLOCK_AGESAWRAPPER_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h index 7174f5e..45bb987 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper_call.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_AGESAWRAPPER_CALL_H__ -#define __AMD_BLOCK_AGESAWRAPPER_CALL_H__ +#ifndef AMD_BLOCK_AGESAWRAPPER_CALL_H +#define AMD_BLOCK_AGESAWRAPPER_CALL_H #include <amdblocks/agesawrapper.h> #include <stdint.h> @@ -41,4 +41,4 @@ return (u32)ret; } -#endif /* __AMD_BLOCK_AGESAWRAPPER_CALL_H__ */ +#endif /* AMD_BLOCK_AGESAWRAPPER_CALL_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h index be1917c..73373bd 100644 --- a/src/soc/amd/common/block/include/amdblocks/alink.h +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ALINK_H__ -#define __AMD_BLOCK_ALINK_H__ +#ifndef AMD_BLOCK_ALINK_H +#define AMD_BLOCK_ALINK_H #include <stdint.h> @@ -32,4 +32,4 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* __AMD_BLOCK_ALINK_H__ */ +#endif /* AMD_BLOCK_ALINK_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h index 067ff98..bcac45a 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_MMCONF_H__ -#define __AMD_BLOCK_PCI_MMCONF_H__ +#ifndef AMD_BLOCK_PCI_MMCONF_H +#define AMD_BLOCK_PCI_MMCONF_H void enable_pci_mmconf(void); -#endif /* __AMD_BLOCK_PCI_MMCONF_H__ */ +#endif /* AMD_BLOCK_PCI_MMCONF_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h index a37c1fd..46fcfbf 100644 --- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_UTIL_H__ -#define __AMD_BLOCK_PCI_UTIL_H__ +#ifndef AMD_BLOCK_PCI_UTIL_H +#define AMD_BLOCK_PCI_UTIL_H #include <stdint.h> #include <soc/amd_pci_int_defs.h> @@ -31,4 +31,4 @@ void write_pci_int_table(void); const struct irq_idx_name *sb_get_apic_reg_association(size_t *size); -#endif /* __AMD_BLOCK_PCI_UTIL_H__ */ +#endif /* AMD_BLOCK_PCI_UTIL_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index a7a73e0..934a244 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_BIOSRAM_H__ -#define __AMD_BLOCK_BIOSRAM_H__ +#ifndef AMD_BLOCK_BIOSRAM_H +#define AMD_BLOCK_BIOSRAM_H #include <stdint.h> @@ -26,4 +26,4 @@ /* Returns the saved UMA base */ uint64_t get_uma_base(void); -#endif /* __AMD_BLOCK_BIOSRAM_H__ */ +#endif /* AMD_BLOCK_BIOSRAM_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/car.h b/src/soc/amd/common/block/include/amdblocks/car.h index 055f294..2f58924 100644 --- a/src/soc/amd/common/block/include/amdblocks/car.h +++ b/src/soc/amd/common/block/include/amdblocks/car.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CAR_H__ -#define __AMD_BLOCK_CAR_H__ +#ifndef AMD_BLOCK_CAR_H +#define AMD_BLOCK_CAR_H #include <stdint.h> void ap_teardown_car(uint32_t flags); -#endif /* __AMD_BLOCK_CAR_H__ */ +#endif /* AMD_BLOCK_CAR_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 8794421..c1820e2 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_CHIP_H__ -#define __AMD_BLOCK_CHIP_H__ +#ifndef AMD_BLOCK_CHIP_H +#define AMD_BLOCK_CHIP_H #include <amdblocks/espi.h> #include <amdblocks/spi.h> @@ -28,4 +28,4 @@ */ const struct soc_amd_common_config *soc_get_common_config(void); -#endif /* __AMD_BLOCK_CHIP_H__ */ +#endif /* AMD_BLOCK_CHIP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h index 5bfb494..d5eb617 100644 --- a/src/soc/amd/common/block/include/amdblocks/dimm_spd.h +++ b/src/soc/amd/common/block/include/amdblocks/dimm_spd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_DIMM_SPD_H__ -#define __AMD_BLOCK_DIMM_SPD_H__ +#ifndef AMD_BLOCK_DIMM_SPD_H +#define AMD_BLOCK_DIMM_SPD_H #include <amdblocks/agesawrapper.h> #include <stddef.h> @@ -15,4 +15,4 @@ int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int sb_read_spd(uint8_t spdAddress, char *buf, size_t len); -#endif /* __AMD_BLOCK_DIMM_SPD_H__ */ +#endif /* AMD_BLOCK_DIMM_SPD_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index c2d822e..c593e02 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_ESPI_H__ -#define __AMD_BLOCK_ESPI_H__ +#ifndef AMD_BLOCK_ESPI_H +#define AMD_BLOCK_ESPI_H #include <stdint.h> #include <stddef.h> @@ -118,4 +118,4 @@ */ int espi_setup(void); -#endif /* __AMD_BLOCK_ESPI_H__ */ +#endif /* AMD_BLOCK_ESPI_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 4b2bfdd..b6162d7 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_GPIO_BANKS_H__ -#define __AMD_BLOCK_GPIO_BANKS_H__ +#ifndef AMD_BLOCK_GPIO_BANKS_H +#define AMD_BLOCK_GPIO_BANKS_H #include <types.h> @@ -361,4 +361,4 @@ /* May be implemented by soc to handle special cases */ void soc_gpio_hook(uint8_t gpio, uint8_t mux); -#endif /* __AMD_BLOCK_GPIO_BANKS_H__ */ +#endif /* AMD_BLOCK_GPIO_BANKS_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/hda.h b/src/soc/amd/common/block/include/amdblocks/hda.h index 55feb6b..a7a0b84 100644 --- a/src/soc/amd/common/block/include/amdblocks/hda.h +++ b/src/soc/amd/common/block/include/amdblocks/hda.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_HDA_H__ -#define __AMD_BLOCK_HDA_H__ +#ifndef AMD_BLOCK_HDA_H +#define AMD_BLOCK_HDA_H #include <device/device.h> /* SoC callback to add any quirks to HDA device node in SSDT. */ void hda_soc_ssdt_quirks(const struct device *dev); -#endif /* __AMD_BLOCK_HDA_H__ */ +#endif /* AMD_BLOCK_HDA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/image.h b/src/soc/amd/common/block/include/amdblocks/image.h index 92d4002..27c8991 100644 --- a/src/soc/amd/common/block/include/amdblocks/image.h +++ b/src/soc/amd/common/block/include/amdblocks/image.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_IMAGE_H__ -#define __AMD_BLOCK_IMAGE_H__ +#ifndef AMD_BLOCK_IMAGE_H +#define AMD_BLOCK_IMAGE_H #include <stdint.h> void *amd_find_image(const void *start_address, const void *end_address, uint32_t alignment, const char name[8]); -#endif /* __AMD_BLOCK_IMAGE_H__ */ +#endif /* AMD_BLOCK_IMAGE_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 1b69a5b3..fbedb71 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_LPC_H__ -#define __AMD_BLOCK_LPC_H__ +#ifndef AMD_BLOCK_LPC_H +#define AMD_BLOCK_LPC_H #include <types.h> @@ -198,4 +198,4 @@ /* Enable SPI ROM (SPI_ROM_ENABLE, SPI_ROM_ALT_ENABLE) */ void lpc_enable_spi_rom(uint32_t enable); -#endif /* __AMD_BLOCK_LPC_H__ */ +#endif /* AMD_BLOCK_LPC_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/pci_devs.h b/src/soc/amd/common/block/include/amdblocks/pci_devs.h index 8a38ac1..074bdd8 100644 --- a/src/soc/amd/common/block/include/amdblocks/pci_devs.h +++ b/src/soc/amd/common/block/include/amdblocks/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PCI_DEVS_H__ -#define __AMD_BLOCK_PCI_DEVS_H__ +#ifndef AMD_BLOCK_PCI_DEVS_H +#define AMD_BLOCK_PCI_DEVS_H #include <device/pci_def.h> @@ -12,4 +12,4 @@ #define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) #endif -#endif /* __AMD_BLOCK_PCI_DEVS_H__ */ +#endif /* AMD_BLOCK_PCI_DEVS_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index f509a5a..8cd8236 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_PSP_H__ -#define __AMD_BLOCK_PSP_H__ +#ifndef AMD_BLOCK_PSP_H +#define AMD_BLOCK_PSP_H /* Get the mailbox base address - specific to family of device. */ void *soc_get_mbox_address(void); @@ -74,4 +74,4 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name); -#endif /* __AMD_BLOCK_PSP_H__ */ +#endif /* AMD_BLOCK_PSP_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 7912bd2..b825f47 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_RESET_H__ -#define __AMD_BLOCK_RESET_H__ +#ifndef AMD_BLOCK_RESET_H +#define AMD_BLOCK_RESET_H #include <console/console.h> #include <arch/cache.h> @@ -26,4 +26,4 @@ halt(); } -#endif /* __AMD_BLOCK_RESET_H__ */ +#endif /* AMD_BLOCK_RESET_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/s3_resume.h b/src/soc/amd/common/block/include/amdblocks/s3_resume.h index 6931a5f..f7fce00 100644 --- a/src/soc/amd/common/block/include/amdblocks/s3_resume.h +++ b/src/soc/amd/common/block/include/amdblocks/s3_resume.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_S3_RESUME_H__ -#define __AMD_BLOCK_S3_RESUME_H__ +#ifndef AMD_BLOCK_S3_RESUME_H +#define AMD_BLOCK_S3_RESUME_H #include <agesa_headers.h> @@ -9,4 +9,4 @@ AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock); AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock); -#endif /* __AMD_BLOCK_S3_RESUME_H__ */ +#endif /* AMD_BLOCK_S3_RESUME_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h index 945b9cd..03e1577 100644 --- a/src/soc/amd/common/block/include/amdblocks/sata.h +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_SATA_H__ -#define __AMD_BLOCK_SATA_H__ +#ifndef AMD_BLOCK_SATA_H +#define AMD_BLOCK_SATA_H #include <device/device.h> void soc_enable_sata_features(struct device *dev); -#endif /* __AMD_BLOCK_SATA_H__ */ +#endif /* AMD_BLOCK_SATA_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/smu.h b/src/soc/amd/common/block/include/amdblocks/smu.h index 57ef3b3..ca5e37a 100644 --- a/src/soc/amd/common/block/include/amdblocks/smu.h +++ b/src/soc/amd/common/block/include/amdblocks/smu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_SMU_H__ -#define __AMD_BLOCK_SMU_H__ +#ifndef AMD_BLOCK_SMU_H +#define AMD_BLOCK_SMU_H #include <types.h> #include <soc/smu.h> /* SoC-dependent definitions for SMU access */ @@ -23,4 +23,4 @@ */ enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload *arg); -#endif /* __AMD_BLOCK_SMU_H__ */ +#endif /* AMD_BLOCK_SMU_H */ diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index 18940a3..7da1b24 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_BLOCK_SPI_H__ -#define __AMD_BLOCK_SPI_H__ +#ifndef AMD_BLOCK_SPI_H +#define AMD_BLOCK_SPI_H #include <types.h> @@ -108,4 +108,4 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); -#endif /* __AMD_BLOCK_SPI_H__ */ +#endif /* AMD_BLOCK_SPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9 Gerrit-Change-Number: 47583 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: soc/amd/stoneyridge: unify and align include guards with picasso
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47582 ) Change subject: soc/amd/stoneyridge: unify and align include guards with picasso ...................................................................... soc/amd/stoneyridge: unify and align include guards with picasso Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/soc/cpu.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/romstage.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 11 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47582/1 diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 9617b45..19f0c81 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef AMD_STONEYRIDGE_ACPI_H +#define AMD_STONEYRIDGE_ACPI_H #include <acpi/acpi.h> @@ -16,4 +16,4 @@ const char *soc_acpi_name(const struct device *dev); -#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index c327863..3b54076 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H +#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H /* * PIRQ and device routing - these define the index into the @@ -44,4 +44,4 @@ #define PIRQ_UART0 0x74 #define PIRQ_UART1 0x75 -#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index 8d25fb6..528daa4 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef AMD_STONEYRIDGE_CPU_H +#define AMD_STONEYRIDGE_CPU_H /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest @@ -16,4 +16,4 @@ void check_mca(void); -#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* AMD_STONEYRIDGE_CPU_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 02cc188..8bfb1f6 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef AMD_STONEYRIDGE_GPIO_H +#define AMD_STONEYRIDGE_GPIO_H #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -292,4 +292,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* AMD_STONEYRIDGE_GPIO_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 63db7d4..0b61329 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_I2C_H__ -#define __STONEYRIDGE_I2C_H__ +#ifndef AMD_STONEYRIDGE_I2C_H +#define AMD_STONEYRIDGE_I2C_H #include <types.h> #include <soc/gpio.h> @@ -29,4 +29,4 @@ void sb_reset_i2c_slaves(void); -#endif /* __STONEYRIDGE_I2C_H__ */ +#endif /* AMD_STONEYRIDGE_I2C_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 8056287..4328880 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef AMD_STONEYRIDGE_IOMAP_H +#define AMD_STONEYRIDGE_IOMAP_H /* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -51,4 +51,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* AMD_STONEYRIDGE_IOMAP_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 3b5fd22..d00f566 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H +#define AMD_STONEYRIDGE_NORTHBRIDGE_H #include <device/device.h> #include <types.h> @@ -89,4 +89,4 @@ void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 03a1233..6af657f 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef AMD_STONEYRIDGE_PCI_DEVS_H +#define AMD_STONEYRIDGE_PCI_DEVS_H #include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -201,4 +201,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/romstage.h b/src/soc/amd/stoneyridge/include/soc/romstage.h index 6dc0b72..1cbaeec 100644 --- a/src/soc/amd/stoneyridge/include/soc/romstage.h +++ b/src/soc/amd/stoneyridge/include/soc/romstage.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef AMD_STONEYRIDGE_ROMSTAGE_H +#define AMD_STONEYRIDGE_ROMSTAGE_H void mainboard_romstage_entry_s3(int s3_resume); -#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 15bba0f..60a91d0 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef AMD_STONEYRIDGE_SMI_H +#define AMD_STONEYRIDGE_SMI_H #define SMI_GEVENTS 24 #define SCIMAPS 58 @@ -218,4 +218,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* AMD_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 85df0b3..cbd9caa 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H +#define AMD_STONEYRIDGE_SOUTHBRIDGE_H #include <types.h> #include <device/device.h> @@ -349,4 +349,4 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); -#endif /* __STONEYRIDGE_H__ */ +#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac Gerrit-Change-Number: 47582 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/picasso/include: unify include guards to match coreboot style
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47580 ) Change subject: soc/amd/picasso/include: unify include guards to match coreboot style ...................................................................... soc/amd/picasso/include: unify include guards to match coreboot style Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/acp.h M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/memmap.h M src/soc/amd/picasso/include/soc/mrc_cache.h M src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/picasso/include/soc/psp_transfer.h M src/soc/amd/picasso/include/soc/reset.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/smu.h M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/include/soc/uart.h 21 files changed, 63 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47580/1 diff --git a/src/soc/amd/picasso/include/soc/acp.h b/src/soc/amd/picasso/include/soc/acp.h index 545a372..f812b32 100644 --- a/src/soc/amd/picasso/include/soc/acp.h +++ b/src/soc/amd/picasso/include/soc/acp.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_ACP_H__ -#define __PI_PICASSO_ACP_H__ +#ifndef AMD_PICASSO_ACP_H +#define AMD_PICASSO_ACP_H /* Bus A D0F5 - Audio Processor */ #define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ @@ -11,4 +11,4 @@ #define ACP_PME_EN 0x1418 #define PME_EN_MASK (1 << 0) -#endif /* __PI_PICASSO_ACP_H__ */ +#endif /* AMD_PICASSO_ACP_H */ diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index a21d347..bc444f8 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_PICASSO_ACPI_H__ -#define __SOC_PICASSO_ACPI_H__ +#ifndef AMD_PICASSO_ACPI_H +#define AMD_PICASSO_ACPI_H #include <acpi/acpi.h> #include <amdblocks/acpi.h> @@ -21,4 +21,4 @@ struct gpio_wake_state gpio_state; }; -#endif /* __SOC_PICASSO_ACPI_H__ */ +#endif /* AMD_PICASSO_ACPI_H */ diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index b423f79..0ffbe77 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __AMD_PCI_INT_DEFS_H__ -#define __AMD_PCI_INT_DEFS_H__ +#ifndef AMD_PICASSO_AMD_PCI_INT_DEFS_H +#define AMD_PICASSO_AMD_PCI_INT_DEFS_H /* * PIRQ and device routing - these define the index into the @@ -64,4 +64,4 @@ #define PIRQ_UART3 0x79 /* UART3 */ /* 0x7a-0x7f reserved */ -#endif /* __AMD_PCI_INT_DEFS_H__ */ +#endif /* AMD_PICASSO_AMD_PCI_INT_DEFS_H */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index cbc3929..3f6cd24 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_CPU_H__ -#define __PICASSO_CPU_H__ +#ifndef AMD_PICASSO_CPU_H +#define AMD_PICASSO_CPU_H int get_cpu_count(void); void check_mca(void); @@ -19,4 +19,4 @@ #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ #define RAVEN2_VBIOS_REV 0xc4 -#endif /* __PICASSO_CPU_H__ */ +#endif /* AMD_PICASSO_CPU_H */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 39906e8..842cb94 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_DATAFABRIC_H__ -#define __SOC_PICASSO_DATAFABRIC_H__ +#ifndef AMD_PICASSO_DATA_FABRIC_H +#define AMD_PICASSO_DATA_FABRIC_H #include <types.h> @@ -26,4 +26,4 @@ void data_fabric_set_mmio_np(void); -#endif /* __SOC_PICASSO_DATAFABRIC_H__ */ +#endif /* AMD_PICASSO_DATA_FABRIC_H */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 370b29f..4fbb937 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_GPIO_H__ -#define __PICASSO_GPIO_H__ +#ifndef AMD_PICASSO_GPIO_H +#define AMD_PICASSO_GPIO_H #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -297,4 +297,4 @@ #define GPIO_2_EVENT GEVENT_8 #endif /* __ACPI__ */ -#endif /* __PICASSO_GPIO_H__ */ +#endif /* AMD_PICASSO_GPIO_H */ diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index c1dd6ef..3e94a1a 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_I2C_H__ -#define __PICASSO_I2C_H__ +#ifndef AMD_PICASSO_I2C_H +#define AMD_PICASSO_I2C_H #include <types.h> #include <soc/gpio.h> @@ -26,4 +26,4 @@ /* Sets the base address for the specific I2C bus. */ void i2c_set_bar(unsigned int bus, uintptr_t bar); -#endif /* __PICASSO_I2C_H__ */ +#endif /* AMD_PICASSO_I2C_H */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 890b1c3..a49768f 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_PICASSO_IOMAP_H__ -#define __SOC_PICASSO_IOMAP_H__ +#ifndef AMD_PICASSO_IOMAP_H +#define AMD_PICASSO_IOMAP_H /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ @@ -90,4 +90,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_PICASSO_IOMAP_H__ */ +#endif /* AMD_PICASSO_IOMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/memmap.h b/src/soc/amd/picasso/include/soc/memmap.h index c27b165..53c9d31 100644 --- a/src/soc/amd/picasso/include/soc/memmap.h +++ b/src/soc/amd/picasso/include/soc/memmap.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOC_AMD_PICASSO_MEMMAP_H__ -#define __SOC_AMD_PICASSO_MEMMAP_H__ +#ifndef AMD_PICASSO_MEMMAP_H +#define AMD_PICASSO_MEMMAP_H #include <stdint.h> #include <symbols.h> @@ -16,4 +16,4 @@ void memmap_stash_early_dram_usage(void); const struct memmap_early_dram *memmap_get_early_dram_usage(void); -#endif /* __SOC_AMD_PICASSO_MEMMAP_H__ */ +#endif /* AMD_PICASSO_MEMMAP_H */ diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h index ed63ba8..c7fcedb 100644 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ b/src/soc/amd/picasso/include/soc/mrc_cache.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __PICASSO_MRC_CACHE_H__ -#define __PICASSO_MRC_CACHE_H__ +#ifndef AMD_PICASSO_MRC_CACHE_H +#define AMD_PICASSO_MRC_CACHE_H void *soc_fill_mrc_cache(void); void soc_update_mrc_cache(void); -#endif /* __PICASSO_MRC_CACHE_H__ */ +#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0743ba0..841e6a5 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -4,8 +4,8 @@ * The definitions come from the device's PPR. */ -#ifndef SOC_AMD_PICASSO_MSR_H -#define SOC_AMD_PICASSO_MSR_H +#ifndef AMD_PICASSO_MSR_H +#define AMD_PICASSO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ #define PSTATE_DEF_HI_ENABLE_SHIFT 31 @@ -25,4 +25,4 @@ #define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT) #define PSTATE_DEF_LO_CORE_FREQ_BASE 25 -#endif /* SOC_AMD_PICASSO_MSR_H */ +#endif /* AMD_PICASSO_MSR_H */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 2abcdd3..d5624d4 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -6,8 +6,8 @@ * */ -#ifndef __SOC_PICASSO_NVS_H__ -#define __SOC_PICASSO_NVS_H__ +#ifndef AMD_PICASSO_NVS_H +#define AMD_PICASSO_NVS_H #include <commonlib/helpers.h> #include <stdint.h> @@ -33,4 +33,4 @@ check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_PICASSO_NVS_H__ */ +#endif /* AMD_PICASSO_NVS_H */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 83c0bcc..3f18bd5 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_PCI_DEVS_H__ -#define __PI_PICASSO_PCI_DEVS_H__ +#ifndef AMD_PICASSO_PCI_DEVS_H +#define AMD_PICASSO_PCI_DEVS_H #include <device/pci_def.h> #include <amdblocks/pci_devs.h> @@ -118,4 +118,4 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) -#endif /* __PI_PICASSO_PCI_DEVS_H__ */ +#endif /* AMD_PICASSO_PCI_DEVS_H */ diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 0ea6f2b..fc7f140 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_PLATFORM_DESCRIPTORS_H__ -#define __PICASSO_PLATFORM_DESCRIPTORS_H__ +#ifndef AMD_PICASSO_PLATFORM_DESCRIPTORS_H +#define AMD_PICASSO_PLATFORM_DESCRIPTORS_H #include <types.h> #include <platform_descriptors.h> @@ -27,4 +27,4 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num); -#endif /* __PICASSO_PLATFORM_DESCRIPTORS_H__ */ +#endif /* AMD_PICASSO_PLATFORM_DESCRIPTORS_H */ diff --git a/src/soc/amd/picasso/include/soc/psp_transfer.h b/src/soc/amd/picasso/include/soc/psp_transfer.h index afc4d7d..ce197c1 100644 --- a/src/soc/amd/picasso/include/soc/psp_transfer.h +++ b/src/soc/amd/picasso/include/soc/psp_transfer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef PSP_VERSTAGE_PSP_TRANSFER_H -#define PSP_VERSTAGE_PSP_TRANSFER_H +#ifndef AMD_PICASSO_PSP_TRANSFER_H +#define AMD_PICASSO_PSP_TRANSFER_H # if (CONFIG_CMOS_RECOVERY_BYTE != 0) # define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE @@ -49,4 +49,4 @@ #endif -#endif /* PSP_VERSTAGE_PSP_TRANSFER_H */ +#endif /* AMD_PICASSO_PSP_TRANSFER_H */ diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h index bb2ee84..fb47068 100644 --- a/src/soc/amd/picasso/include/soc/reset.h +++ b/src/soc/amd/picasso/include/soc/reset.h @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PI_PICASSO_RESET_H__ -#define __PI_PICASSO_RESET_H__ +#ifndef AMD_PICASSO_RESET_H +#define AMD_PICASSO_RESET_H void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_PICASSO_RESET_H__ */ +#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index 6413c6a..1f08efe 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#ifndef AMD_PICASSO_SMI_H +#define AMD_PICASSO_SMI_H #include <types.h> @@ -221,4 +221,4 @@ void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); void soc_route_sci(uint8_t event); -#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ +#endif /* AMD_PICASSO_SMI_H */ diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h index c402508..2dd0e7b 100644 --- a/src/soc/amd/picasso/include/soc/smu.h +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SMU_H__ -#define __PICASSO_SMU_H__ +#ifndef AMD_PICASSO_SMU_H +#define AMD_PICASSO_SMU_H /* * SMU mailbox register offsets in indirect address space accessed by an index/data pair in @@ -23,4 +23,4 @@ */ void smu_sx_entry(void); -#endif /* __PICASSO_SMU_H__ */ +#endif /* AMD_PICASSO_SMU_H */ diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 0de0643..e03a78e 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SOC_UTIL_H__ -#define __PICASSO_SOC_UTIL_H__ +#ifndef AMD_PICASSO_SOC_UTIL_H +#define AMD_PICASSO_SOC_UTIL_H #include <types.h> @@ -39,4 +39,4 @@ /* function to determine the iGPU type */ bool soc_is_raven2(void); -#endif /* __PICASSO_SOC_UTIL_H__ */ +#endif /* AMD_PICASSO_SOC_UTIL_H */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 222858a..d193661 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_SB_H__ -#define __PICASSO_SB_H__ +#ifndef AMD_PICASSO_SOUTHBRIDGE_H +#define AMD_PICASSO_SOUTHBRIDGE_H #include <types.h> #include <device/device.h> @@ -294,4 +294,4 @@ /* Allow the board to change the default I2C pad configuration */ void mainboard_i2c_override(int bus, uint32_t *pad_settings); -#endif /* __PICASSO_SB_H__ */ +#endif /* AMD_PICASSO_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/picasso/include/soc/uart.h b/src/soc/amd/picasso/include/soc/uart.h index 4e5619f..051c8bf 100644 --- a/src/soc/amd/picasso/include/soc/uart.h +++ b/src/soc/amd/picasso/include/soc/uart.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __PICASSO_UART_H__ -#define __PICASSO_UART_H__ +#ifndef AMD_PICASSO_UART_H +#define AMD_PICASSO_UART_H #include <types.h> @@ -10,4 +10,4 @@ uintptr_t get_uart_base(unsigned int idx); /* get MMIO base address of FCH UART */ -#endif /* __PICASSO_UART_H__ */ +#endif /* AMD_PICASSO_UART_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5 Gerrit-Change-Number: 47580 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/amd/picasso/include/amd_pci_int_defs: remove duplicate comment
by Felix Held (Code Review) 16 Nov '20

16 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47581 ) Change subject: soc/amd/picasso/include/amd_pci_int_defs: remove duplicate comment ...................................................................... soc/amd/picasso/include/amd_pci_int_defs: remove duplicate comment This also reduces the difference to the equivalent file from stoneyridge. Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47581/1 diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index 0ffbe77..7f75de9 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -7,10 +7,7 @@ * PIRQ and device routing - these define the index into the * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ -/* - * PIRQ and device routing - these define the index into the - * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. - */ + #define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_A 0x00 /* INT A */ #define PIRQ_B 0x01 /* INT B */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531 Gerrit-Change-Number: 47581 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/kukui: Fix LCD sequence T3 fail issue
by Tao Xia (Code Review) 16 Nov '20

16 Nov '20

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47443 ) Change subject: mb/google/kukui: Fix LCD sequence T3 fail issue ...................................................................... mb/google/kukui: Fix LCD sequence T3 fail issue There is a delay between PPVARN_LCD_EN and PPVARN_LCD. An extra 9ms delay should be added on LCM_RST_1V8 in order to meet the Spec. BUG=b:172201138 BRANCH=kukui TEST=The LCD sequence T3 is larger than 5ms when power on. Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54 --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47443/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 268b7ca..cbcb5da 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -91,7 +91,7 @@ gpio_output(GPIO_PPVARN_LCD_EN, 1); gpio_output(GPIO_PP1800_LCM_EN, 1); gpio_output(GPIO_PP3300_LCM_EN, 1); - mdelay(6); + mdelay(15); gpio_output(GPIO_LCM_RST_1V8, 1); mdelay(6); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf7ae494e30c4c207103d949287b335288688c54 Gerrit-Change-Number: 47443 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: [WIP] plot TxDQ
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47626 ) Change subject: [WIP] plot TxDQ ...................................................................... [WIP] plot TxDQ Change-Id: I72089ac4f4ff272731032e77f246a57a30051334 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47626/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 1bf4673..8a2e7f7 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1613,6 +1613,17 @@ stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } + + printk(BIOS_ERR, "Channel %d results:\n", channel); + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { + printk(BIOS_ERR, "% 5d\t", tx_dq); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", stats[lane][tx_dq] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); -- To view, visit https://review.coreboot.org/c/coreboot/+/47626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72089ac4f4ff272731032e77f246a57a30051334 Gerrit-Change-Number: 47626 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [WIP] plot TxDQ aka timC
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47623 ) Change subject: [WIP] plot TxDQ aka timC ...................................................................... [WIP] plot TxDQ aka timC Change-Id: I6204c874ef616a20bffa305ffee4698a5e08bdc2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47623/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4f54016..14f7dad 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1613,6 +1613,17 @@ stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } + + printk(BIOS_ERR, "Channel %d results:\n", channel); + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + for (timC = 0; timC <= MAX_TIMC; timC++) { + printk(BIOS_ERR, "% 5d\t", timC); + FOR_ALL_LANES { + printk(BIOS_ERR, "%c", stats[lane][timC] ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + FOR_ALL_LANES { struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); -- To view, visit https://review.coreboot.org/c/coreboot/+/47623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6204c874ef616a20bffa305ffee4698a5e08bdc2 Gerrit-Change-Number: 47623 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [WIP] nb/intel/sandybridge: Derive initial timC from timB
by Angel Pons (Code Review) 15 Nov '20

15 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47624 ) Change subject: [WIP] nb/intel/sandybridge: Derive initial timC from timB ...................................................................... [WIP] nb/intel/sandybridge: Derive initial timC from timB The mysterious timB and timC values correspond to TxDQS and TxDQ PIs, respectively. TxDQS can be determined using JEDEC write leveling, but TxDQ needs another training step. However, the ideal skew between these two signals is 32 PI ticks, so we can apply this offset to uniformize all lanes. Change-Id: I3795a7f83280d538660fd1bb852435ab02e1f27c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47624/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 14f7dad..3ea4ff2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1592,6 +1592,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { + int start[NUM_LANES]; int timC; int stats[NUM_LANES][MAX_TIMC + 1]; int lane; @@ -1603,8 +1604,17 @@ /* Execute command queue */ iosav_run_once(channel); + FOR_ALL_LANES { + /* 32 ticks for ideal centering */ + start[lane] = (ctrl->timings[channel][slotrank].lanes[lane].timB + 32) % 128; + } + for (timC = 0; timC <= MAX_TIMC; timC++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timC = + (start[lane] + timC) % 128; + } + program_timings(ctrl, channel); test_timC(ctrl, channel, slotrank); @@ -1642,7 +1652,11 @@ return MAKE_ERR; } } - ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; + rn.start += start[lane]; + rn.middle += start[lane]; + rn.end += start[lane]; + ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle % 128; + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", channel, slotrank, lane, rn.start, rn.middle, rn.end); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3795a7f83280d538660fd1bb852435ab02e1f27c Gerrit-Change-Number: 47624 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: util/cbfstool/amdcompress: fix argument requirement
by Felix Held (Code Review) 15 Nov '20

15 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47573 ) Change subject: util/cbfstool/amdcompress: fix argument requirement ...................................................................... util/cbfstool/amdcompress: fix argument requirement The compress and uncompress options don't have arguments and shouldn't consume the next token. So replace required_argument with no_argument for the two options. Change-Id: Ib9b190f2cf606109f82a65d00327871d6ffb7082 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/cbfstool/amdcompress.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/47573/1 diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c index b4e10a2..eae347f 100644 --- a/util/cbfstool/amdcompress.c +++ b/util/cbfstool/amdcompress.c @@ -29,9 +29,9 @@ static struct option long_options[] = { {"infile", required_argument, 0, 'i' }, {"outfile", required_argument, 0, 'o' }, - {"compress", required_argument, 0, 'c' }, + {"compress", no_argument, 0, 'c' }, {"maxsize", required_argument, 0, 'h' }, - {"uncompress", required_argument, 0, 'u' }, + {"uncompress", no_argument, 0, 'u' }, {"help", no_argument, 0, 'h' }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b190f2cf606109f82a65d00327871d6ffb7082 Gerrit-Change-Number: 47573 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020