coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1
by Tim Wawrzynczak (Code Review) 13 Nov '20

13 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Config for passive USB-C DB on C1 ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… PS2, Line 131: x04; /* port2 retimer disable */ where did this value come from? https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… PS2, Line 146: : gpio_configure_pads_with_override(base_pads, base_num, : override_pads, override_num); : : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : const struct pad_config *pads; : size_t num; : : pads = variant_usb3_passive_gpio_table(&num); : gpio_configure_pads(pads, num); : } can this go in mb/google/volteer/fw_config.c instead? https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… PS2, Line 34: 0x090E0016 Where do these values come from? -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 20:00:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload/usb: Fix printf format string mismatches in debug messages
by Tim Wawrzynczak (Code Review) 13 Nov '20

13 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45024 ) Change subject: libpayload/usb: Fix printf format string mismatches in debug messages ...................................................................... Patch Set 5: > Patch Set 4: > > > > should we reflow the affected areas to fit within 96 columns > > > to keep buildbot happy? i'm not convinced that aggressively > > > splitting format strings improves this patch. > > > > It's either that or you can't get verified+1 the way things work right now > > No, that's not how this works (unless something changed very recently that I'm not aware of). The line comments Jenkins adds from checkpatch are always purely informational and do not affect Verified+1. We know checkpatch has false positives and it's perfectly valid to ignore them if reviewers agree on that -- they're just there to make sure you don't miss something, basically. In this case I totally agree with Caveh that it's probably more readable the existing way (and there's a "long strings" exception in the coding style for this, which checkpatch doesn't account for). > > Verified+1 is only affected by actual compiler failures, or by failures of linters that are marked as "stable" (which checkpatch is not). In this case, it looks like the PRIxPTR macro was not defined or the respective header not included somewhere. I see thanks Julius, somehow I got it in my head that line length was the one thing build bot was a stickler about. Caveh, I think you need to include <inttypes.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Gerrit-Change-Number: 45024 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 13 Nov 2020 19:49:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/43072/12/src/soc/intel/skylake/nhl… File src/soc/intel/skylake/nhlt/dmic.c: https://review.coreboot.org/c/coreboot/+/43072/12/src/soc/intel/skylake/nhl… PS12, Line 27: .device = 0x1, // NHLT_PDM_DEV on cAVS1.5 (KBL) based platforms > Why not apply CB:45010 first, then add support for 1ch DMIC? Done. I was updating this patchset, then I addressed CB:45010 and realised I had to come back here. -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 19:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Lock down P2SB SBI
by Arthur Heymans (Code Review) 13 Nov '20

13 Nov '20

Hello Philipp Deppenwiese, Patrick Rudolph, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46499 to look at the new patch set (#9). Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ...................................................................... soc/intel/xeon_sp/cpx: Lock down P2SB SBI This is required for CBnT. Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/p2sb.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46499/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/46499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Gerrit-Change-Number: 46499 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/xeon_sp/acpi.c Look over HOB stack for MADT generation
by Arthur Heymans (Code Review) 13 Nov '20

13 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47300 ) Change subject: soc/intel/xeon_sp/acpi.c Look over HOB stack for MADT generation ...................................................................... soc/intel/xeon_sp/acpi.c Look over HOB stack for MADT generation To align MADT generation with DMAR, we loop over HOB entries instead of over copied HOB entries fetched from get_iio_stacks(). This makes it easier to see what is going on. Tested on ocp/deltalake Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/acpi.c 1 file changed, 26 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47300/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index b7e20d4..fcd5f00 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -72,12 +72,12 @@ return current; } -static unsigned long add_madt_ioapic(unsigned long current, int stack, int ioapic_id, +static unsigned long add_madt_ioapic(unsigned long current, int socket, int stack, int ioapic_id, uint32_t ioapic_base, int gsi_base) { - printk(BIOS_DEBUG, "Adding MADT IOAPIC for stack: %d, ioapic_id: 0x%x, " + printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " "ioapic_base: 0x%x, gsi_base: 0x%x\n", - stack, ioapic_id, ioapic_base, gsi_base); + socket, stack, ioapic_id, ioapic_base, gsi_base); return acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, ioapic_id, ioapic_base, gsi_base); } @@ -85,7 +85,7 @@ unsigned long acpi_fill_madt(unsigned long current) { int cur_index; - struct iiostack_resource stack_info = {0}; + const IIO_UDS *hob = get_iio_uds(); /* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */ #if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) @@ -101,30 +101,32 @@ current = xeonsp_acpi_create_madt_lapics(current); cur_index = 0; - get_iiostack_info(&stack_info); - for (int stack = 0; stack < stack_info.no_of_stacks; ++stack) { - const STACK_RES *ri = &stack_info.res[stack]; - assert(cur_index < ARRAY_SIZE(ioapic_ids)); - assert(cur_index < ARRAY_SIZE(gsi_bases)); - int ioapic_id = ioapic_ids[cur_index]; - int gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, stack, ioapic_id, ri->IoApicBase, - gsi_base); - ++cur_index; - - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * Add entry for PCH IOAPIC. - */ - if (stack == 0) { /* PCH IOAPIC */ + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + if (ri->Personality != TYPE_UBOX_IIO) + continue; assert(cur_index < ARRAY_SIZE(ioapic_ids)); assert(cur_index < ARRAY_SIZE(gsi_bases)); - ioapic_id = ioapic_ids[cur_index]; - gsi_base = gsi_bases[cur_index]; - current += add_madt_ioapic(current, stack, ioapic_id, - ri->IoApicBase + 0x1000, gsi_base); + int ioapic_id = ioapic_ids[cur_index]; + int gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, socket, stack, ioapic_id, ri->IoApicBase, gsi_base); ++cur_index; + + /* + * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. + * Add entry for PCH IOAPIC. + */ + if (stack == 0 && socket == 0) { /* PCH IOAPIC */ + assert(cur_index < ARRAY_SIZE(ioapic_ids)); + assert(cur_index < ARRAY_SIZE(gsi_bases)); + ioapic_id = ioapic_ids[cur_index]; + gsi_base = gsi_bases[cur_index]; + current += add_madt_ioapic(current, socket, stack, ioapic_id, + ri->IoApicBase + 0x1000, gsi_base); + ++cur_index; + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288 Gerrit-Change-Number: 47300 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/xeon_sp: move get_iiostack_info() to a common place
by Arthur Heymans (Code Review) 13 Nov '20

13 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47522 ) Change subject: soc/intel/xeon_sp: move get_iiostack_info() to a common place ...................................................................... soc/intel/xeon_sp: move get_iiostack_info() to a common place All this function does is looping over IIO stacks in the FSP HOB. The only 'SOC/FSP specific' thing is the way to detect if the stack is an IIO stack so add a callback to determine this. Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/util.c 7 files changed, 31 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/47522/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index e3c971d..5ce3928 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -6,13 +6,6 @@ #include <hob_iiouds.h> #include <hob_memmap.h> -struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[MAX_SOCKET * MAX_LOGIC_IIO_STACK]; -}; - -void get_iiostack_info(struct iiostack_resource *info); - const struct SystemMemoryMapHob *get_system_memory_map(void); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index c35c248..599ccff 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_util.h> +#include <soc/util.h> /* TODO: Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 242fcfe..578f67c 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -27,21 +27,9 @@ return *memmap_addr; } -void get_iiostack_info(struct iiostack_resource *info) +bool is_iio_stack_res(const STACK_RES *res) { - const IIO_UDS *hob = get_iio_uds(); - - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - if (ri->Personality == TYPE_UBOX_IIO) { - assert(info->no_of_stacks < ARRAY_SIZE(info->res)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } - } - } + return res->Personality == TYPE_UBOX_IIO; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 014b238..fc0dee7 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -17,4 +17,12 @@ void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +void get_iiostack_info(struct iiostack_resource *info); +bool is_iio_stack_res(const STACK_RES *res); + #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 0f52811..526f5a6 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -6,13 +6,6 @@ #include <hob_iiouds.h> #include <hob_memmap.h> -struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; -}; - -void get_iiostack_info(struct iiostack_resource *info); - void config_reset_cpl3_csrs(void); const struct SystemMemoryMapHob *get_system_memory_map(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 767871b..cb818cb 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -55,24 +55,10 @@ return memmap_addr; } -void get_iiostack_info(struct iiostack_resource *info) +bool is_iio_stack_res(const STACK_RES *res) { - const IIO_UDS *hob = get_iio_uds(); - - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - // TODO: do we have situation with only bux 0 and one stack? - if (ri->BusBase >= ri->BusLimit) - continue; - assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } - } - - return hob->PlatformData.Pci64BitResourceAllocation; + // TODO: do we have situation with only bux 0 and one stack? + return ri->BusBase < ri->BusLimit; } uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 3104215..b4f7eaa 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -119,6 +119,23 @@ return hob; } +void get_iiostack_info(struct iiostack_resource *info) +{ + const IIO_UDS *hob = get_iio_uds(); + + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (!is_iio_stack_res(ri)) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } +} + unsigned int soc_get_num_cpus(void) { /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a Gerrit-Change-Number: 47522 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/xeon_sp: Change the return type of get_iio_stack_info()
by Arthur Heymans (Code Review) 13 Nov '20

13 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47298 ) Change subject: soc/intel/xeon_sp: Change the return type of get_iio_stack_info() ...................................................................... soc/intel/xeon_sp: Change the return type of get_iio_stack_info() This makes the function harder to understand and the return type is not consistently used. Use a different helper function to get the HOB Pci64BitResourceAllocation data. Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 5 files changed, 13 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47298/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 5c78780..dd37e48 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -403,6 +403,13 @@ } } +static uint8_t is_pci64bit_alloc(void) +{ + const IIO_UDS *hob = get_iio_uds(); + + return hob->PlatformData.Pci64BitResourceAllocation; +} + static void xeonsp_pci_domain_read_resources(struct device *dev) { struct bus *link; @@ -425,7 +432,8 @@ xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); struct iiostack_resource stack_info = {0}; - uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); + uint8_t pci64bit_alloc_flag = is_pci64bit_alloc(); + get_iiostack_info(&stack_info); if (!pci64bit_alloc_flag) { /* * Split 32 bit address space between prefetchable and diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 5f4a6f9..07c454e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -11,7 +11,7 @@ STACK_RES res[MAX_SOCKET * MAX_LOGIC_IIO_STACK]; }; -uint8_t get_iiostack_info(struct iiostack_resource *info); +void get_iiostack_info(struct iiostack_resource *info); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 1c5a737..9e7072e 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -163,7 +163,7 @@ } } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void get_iiostack_info(struct iiostack_resource *info) { const IIO_UDS *hob = get_iio_uds(); @@ -178,8 +178,6 @@ } } } - - return hob->PlatformData.Pci64BitResourceAllocation; } /* return true if command timed out else false */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index e0d66d6..93481c9 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -11,7 +11,7 @@ STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; }; -uint8_t get_iiostack_info(struct iiostack_resource *info); +void get_iiostack_info(struct iiostack_resource *info); void xeonsp_init_cpu_config(void); const IIO_UDS *get_iio_uds(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 6d511ea..f9eddb2 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -291,7 +291,7 @@ return soc_get_num_cpus() * get_threads_per_package(); } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void get_iiostack_info(struct iiostack_resource *info) { const IIO_UDS *hob = get_iio_uds(); @@ -311,8 +311,6 @@ memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); } } - - return hob->PlatformData.Pci64BitResourceAllocation; } #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/47298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e Gerrit-Change-Number: 47298 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43072 to look at the new patch set (#15). Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... soc/intel/skylake: Support NHLT 1ch DMIC Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/dmic.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/43072/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Add correct NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45010 to look at the new patch set (#6). Change subject: soc/intel/skylake: Add correct NHLT_PDM_DEV definition ...................................................................... soc/intel/skylake: Add correct NHLT_PDM_DEV definition According to the NHLT specification[1], PDM_DEV is defined as "1" on Kabylake based platforms. coreboot currently sets it to "0" on all platforms. Add an entry to the enum and use it to define NHLT_PDM_DEV for Kabylake. "Device Type" will resume from "2" on all platforms, but entries are currently reserved. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/include/nhlt.h M src/soc/intel/skylake/nhlt/dmic.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45010/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Add correct NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45010 ) Change subject: soc/intel/skylake: Add correct NHLT_PDM_DEV definition ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45010/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45010/3//COMMIT_MSG@7 PS3, Line 7: Fix NHLT_PDM_DEV definition > Ooooor simply add `config NHLT_PDM_DEV_VALUE`, make it default to zero, override it in KBL to be one […] The current solution guarantees that any future entries will remain correct, regardless of platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 19:10:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020