Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45952 )
Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
......................................................................
soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
Currently, the ACPI PM timer state gets set in devicetree by the option
PmTimerDisabled. However, it is not board design dependent. Thus, add a
user-selectable Kconfig option.
Disabling the PM ACPI Timer is only valid when PM Timer emulation is
supported and is only possible, when there is a hardware PM Timer (APL
does not have one for example). SoCs, where the hardware PM Timer can be
disabled must select `PM_ACPI_TIMER_OPTIONAL`.
This new Kconfig gets used in the follow-up commits of this series.
Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45952
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/soc/intel/common/block/pmc/Kconfig
1 file changed, 22 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index 5cb2bea..b420865 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -43,3 +43,25 @@
help
Enable this for PMC devices to perform registers programming
to ensure low power in active idle scenario.
+
+config PM_ACPI_TIMER_OPTIONAL
+ bool
+ default n
+ help
+ This needs to be selected by SoCs, where the hardware PM Timer
+ can be disabled, to show the ACPI PM Timer Kconfig in menuconfig.
+
+if PM_ACPI_TIMER_OPTIONAL
+
+config USE_PM_ACPI_TIMER
+ bool "Enable ACPI PM timer"
+ default y
+ help
+ This should be disabled for devices running on battery since
+ it can draw much power. Further, it must be disabled, if S0ix
+ is enabled.
+
+ Disabling this option also stops the hardware TCO timer and makes
+ the TCO watchdog unavailable.
+
+endif # PM_ACPI_TIMER_OPTIONAL
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917
Gerrit-Change-Number: 45952
Gerrit-PatchSet: 31
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
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Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de>
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Gerrit-MessageType: merged
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47195 )
Change subject: soc/intel/cnl: replace the remaints of HeciEnabled by device state in dt
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47195/9//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47195/9//COMMIT_MSG@7
PS9, Line 7: remaints
remains
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Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Gerrit-Comment-Date: Fri, 13 Nov 2020 16:58:21 +0000
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47444 )
Change subject: Doc/relnotes/4.13: Add several relevant changes
......................................................................
Doc/relnotes/4.13: Add several relevant changes
While some of these have little impact, they are worth mentioning here.
Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/releases/coreboot-4.13-relnotes.md
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47444/1
diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md
index 8d19067..efb45b0 100644
--- a/Documentation/releases/coreboot-4.13-relnotes.md
+++ b/Documentation/releases/coreboot-4.13-relnotes.md
@@ -13,6 +13,27 @@
Significant changes
-------------------
+### Native refcode implementation for Bay Trail
+
+Bay Trail no longer needs a refcode binary to function properly. The refcode
+was reimplemented as coreboot code, which should be functionally equivalent.
+Thus, MRC.bin is now the only required Bay Trail binary executed by coreboot.
+
+### Unusual config files to build test more code
+
+There's some new highly-unusual config files, whose only purpose is to coerce
+Jenkins into build-testing several disabled-by-default coreboot config options.
+This prevents them from silently decaying over time because of build failures.
+
+### Initial support for Intel Trusted eXecution Technology
+
+coreboot now supports enabling Intel TXT. Though it's not feature-complete yet,
+the code allows successfully launching tboot, a Measured Launch Environment. It
+was tested on Haswell using an Asrock B85M Pro4 mainboard with TPM 2.0 on LPC.
+Support for other platforms is still work in progress, but is being worked on.
+The Haswell MRC.bin needs to be patched so as to enable DPR. The only winning
+move is not to play with the MRC.bin, and instead write a replacement for it.
+
### Hidden PCI devices
This new functionality takes advantage of the existing 'hidden' keyword in the
--
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