coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/skylake: Add correct NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45010 to look at the new patch set (#5). Change subject: soc/intel/skylake: Add correct NHLT_PDM_DEV definition ...................................................................... soc/intel/skylake: Add correct NHLT_PDM_DEV definition According to the NHLT specification[1], PDM_DEV is defined as "1" on Kabylake based platforms. coreboot currently sets it to "0" on all platforms. Add an entry to the enum and use it to define NHLT_PDM_DEV for Kabylake. "Device Type" will resume from "2" on all platforms, but entries are currently reserved. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/include/nhlt.h M src/soc/intel/skylake/nhlt/dmic.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45010/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/43072/12/src/soc/intel/skylake/nhl… File src/soc/intel/skylake/nhlt/dmic.c: https://review.coreboot.org/c/coreboot/+/43072/12/src/soc/intel/skylake/nhl… PS12, Line 27: .device = 0x1, // NHLT_PDM_DEV on cAVS1.5 (KBL) based platforms Why not apply CB:45010 first, then add support for 1ch DMIC? -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 19:09:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43072 to look at the new patch set (#12). Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... soc/intel/skylake: Support NHLT 1ch DMIC Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/dmic.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/43072/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Fix NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 13 Nov '20

13 Nov '20

Hello build bot (Jenkins), Matt DeVillier, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45010 to look at the new patch set (#4). Change subject: soc/intel/skylake: Fix NHLT_PDM_DEV definition ...................................................................... soc/intel/skylake: Fix NHLT_PDM_DEV definition According to the NHLT specification[1], PDM is defined as "1" on Kabylake based platforms. coreboot sets it to "0" on all platforms. Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array DMIC, on Windows 10. 1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/include/nhlt.h M src/soc/intel/skylake/nhlt/dmic.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45010/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/acpi: add Kconfig for CPPC entries generation
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47540 ) Change subject: soc/intel/common/block/acpi: add Kconfig for CPPC entries generation ...................................................................... soc/intel/common/block/acpi: add Kconfig for CPPC entries generation Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47540 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index ff59172..d9a7a87 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -4,3 +4,12 @@ bool help Intel Processor common code for ACPI + +if SOC_INTEL_COMMON_BLOCK_ACPI + +config SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + bool + help + Generate CPPC entries for Intel SpeedShift + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieae9f221ffb27cf52cab21a130e18aa3929caea3 Gerrit-Change-Number: 47540 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/36/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/36/src/soc/intel/common/bloc… PS36, Line 14: #include <cpu/x86/msr.h> > I don't think you added anything from this header indeed, was from an earlier version -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 13 Nov 2020 18:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Hello Felix Singer, Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#37). Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... soc/intel/common/block: add code for ACPI CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update WWAN GPIO as per latest schematics
by Subrata Banik (Code Review) 13 Nov '20

13 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47519 ) Change subject: mb/intel/adlrvp: Update WWAN GPIO as per latest schematics ...................................................................... mb/intel/adlrvp: Update WWAN GPIO as per latest schematics WWAN_RST#: E10 -> F14 WWAN_PWR_EN: E13-> F21 Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/early_gpio.c M src/mainboard/intel/adlrvp/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/47519/1 diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c index d45bf8e..11938ed 100644 --- a/src/mainboard/intel/adlrvp/early_gpio.c +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -8,9 +8,9 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 0, PLTRST), + PAD_CFG_GPO(GPP_F14, 0, PLTRST), /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), }; void variant_configure_early_gpio_pads(void) diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index f91b94f..039a437 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -53,9 +53,9 @@ /* WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 1, PLTRST), + PAD_CFG_GPO(GPP_F14, 1, PLTRST), /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), + PAD_CFG_GPO(GPP_F21, 1, DEEP), /* WWAN_PERST# */ PAD_CFG_GPO(GPP_C5, 1, PLTRST), /* PEG_SLOT_WAKE_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7182f384eb7a404dfe623c64e29467b41c6b0bdd Gerrit-Change-Number: 47519 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454
by Subrata Banik (Code Review) 13 Nov '20

13 Nov '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47244 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454 ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454 List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 46 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index a4b885d..552f50a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -880,7 +880,17 @@ /** Offset 0x0797 - Reserved **/ - UINT8 Reserved38[50]; + UINT8 Reserved38[35]; + +/** Offset 0x07BA - Command Pins Mapping + BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller + 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. +**/ + UINT8 Lp5CccConfig; + +/** Offset 0x07BB - Reserved +**/ + UINT8 Reserved39[14]; /** Offset 0x07C9 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -891,7 +901,7 @@ /** Offset 0x07CA - Reserved **/ - UINT8 Reserved39; + UINT8 Reserved40; /** Offset 0x07CB - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -901,7 +911,7 @@ /** Offset 0x07CC - Reserved **/ - UINT8 Reserved40[129]; + UINT8 Reserved41[129]; /** Offset 0x084D - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -911,7 +921,7 @@ /** Offset 0x084E - Reserved **/ - UINT8 Reserved41[292]; + UINT8 Reserved42[292]; /** Offset 0x0972 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -922,7 +932,7 @@ /** Offset 0x0973 - Reserved **/ - UINT8 Reserved42[183]; + UINT8 Reserved43[183]; /** Offset 0x0A2A - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings @@ -933,7 +943,7 @@ /** Offset 0x0A2B - Reserved **/ - UINT8 Reserved43[349]; + UINT8 Reserved44[349]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 685eeeb..e78311c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -723,9 +723,9 @@ /** Offset 0x0A70 - Reserved **/ - UINT8 Reserved41[113]; + UINT8 Reserved41[89]; -/** Offset 0x0AE1 - Enable PS_ON. +/** Offset 0x0AC9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -733,29 +733,29 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0AE2 - Reserved +/** Offset 0x0ACA - Reserved **/ UINT8 Reserved42[310]; -/** Offset 0x0C18 - RpPtmBytes +/** Offset 0x0C00 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0C1C - Reserved +/** Offset 0x0C04 - Reserved **/ UINT8 Reserved43[99]; -/** Offset 0x0C7F - Enable/Disable IGFX PmSupport +/** Offset 0x0C67 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C80 - Reserved +/** Offset 0x0C68 - Reserved **/ UINT8 Reserved44; -/** Offset 0x0C81 - GT Frequency Limit +/** Offset 0x0C69 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -769,22 +769,22 @@ **/ UINT8 GtFreqMax; -/** Offset 0x0C82 - Reserved +/** Offset 0x0C6A - Reserved **/ UINT8 Reserved45[24]; -/** Offset 0x0C9A - Enable or Disable HWP +/** Offset 0x0C82 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C9B - Reserved +/** Offset 0x0C83 - Reserved **/ UINT8 Reserved46[8]; -/** Offset 0x0CA3 - TCC Activation Offset +/** Offset 0x0C8B - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -792,63 +792,63 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0CA4 - Reserved +/** Offset 0x0C8C - Reserved **/ UINT8 Reserved47[34]; -/** Offset 0x0CC6 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CAE - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CC7 - Reserved +/** Offset 0x0CAF - Reserved **/ - UINT8 Reserved48[197]; + UINT8 Reserved48[196]; -/** Offset 0x0D8C - Enable LOCKDOWN SMI +/** Offset 0x0D73 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D8D - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D74 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D8E - Unlock all GPIO pads +/** Offset 0x0D75 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D8F - Reserved +/** Offset 0x0D76 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved49[2]; -/** Offset 0x0D90 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D78 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DC8 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DB0 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0E00 - Reserved +/** Offset 0x0DE8 - Reserved **/ UINT8 Reserved50[313]; -/** Offset 0x0F39 - LpmStateEnableMask +/** Offset 0x0F21 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0F3A - Reserved +/** Offset 0x0F22 - Reserved **/ - UINT8 Reserved51[766]; + UINT8 Reserved51[702]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -867,11 +867,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1238 +/** Offset 0x11E0 **/ - UINT8 UnusedUpdSpace48[6]; + UINT8 UnusedUpdSpace45[6]; -/** Offset 0x123E +/** Offset 0x11E6 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/47244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Gerrit-Change-Number: 47244 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cnl: enable ACPI CPPC entries generation
by Tim Wawrzynczak (Code Review) 13 Nov '20

13 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47541 ) Change subject: soc/intel/cnl: enable ACPI CPPC entries generation ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6 Gerrit-Change-Number: 47541 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 17:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020