coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Hello Felix Singer, Elyes HAOUAS, build bot (Jenkins), Matt Delco, Nico Huber, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45535 to look at the new patch set (#38). Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... soc/intel/common/block: add code for ACPI CPPC entries generation Copy the code for CPPC entries generation, needed for Intel SpeedShift, from SKL to common ACPI code. SKL is going to use common ACPI code, too, in the future, so this code duplication will vanish soon. Test: dumped SSDT from Clevo L140CU and checked decompiled version after enabling CPPC entries via Kconfig Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/45535/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 38 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… PS37, Line 400: GCPC CPPC? -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:52:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Rocky Phagura (Code Review) 13 Nov '20

13 Nov '20

Rocky Phagura has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 27: Arthur, Which piece of code is not working for CPU save state? You can also email me directly. rphagura(a)fb.com. Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 27 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variant/lindar: Update devicetree settings for touc...
by Stanley Wu (Code Review) 13 Nov '20

13 Nov '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47390 ) Change subject: mb/google/volteer/variant/lindar: Update devicetree settings for touchscreen and trackpad ...................................................................... mb/google/volteer/variant/lindar: Update devicetree settings for touchscreen and trackpad Update I2C address for Goodix touchscreen and add ELAN touchscreen & Synaptics trackpad. BUG=b:160013582 TEST=emerge-puff coreboot and check system dmesg and evtest can get device. Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/volteer/variants/lindar/overridetree.cb 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47390/1 diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 87ca0a3..03cef1c 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -58,7 +58,19 @@ register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end + device i2c 5d on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end end end device ref i2c5 on @@ -70,6 +82,15 @@ register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E15_IRQ)" + register "generic.wake" = "GPE0_DW2_15" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end end device ref north_xhci on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/47390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84 Gerrit-Change-Number: 47390 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47195 ) Change subject: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt ...................................................................... soc/intel/cnl: replace the remains of HeciEnabled by device state in dt The option `HeciEnabled` was partly replaced by use of the device on/off state in the devicetree in commit 3de90d1. The option has been removed from the corresponding boards, so `HeciEnabled` is always 0 and ME always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM` is set. Replace the option in the finalize function by the same dt state check that sets the FSP option and drop the remaints of `HeciEnabled`. Devicetrees still having `HeciEnabled` have been adapted to keep the current behaviour. Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/variants/ambassador/overridetree.cb M src/mainboard/google/hatch/variants/genesis/overridetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/smihandler.c 7 files changed, 10 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index adb00e4..835a8aa 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -370,6 +367,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb index adb00e4..835a8aa 100644 --- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -1,7 +1,4 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" - # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -370,6 +367,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 5615554..b276919 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -24,9 +24,7 @@ device pci 14.2 on end # RAM controller device pci 14.5 off end # SDCard - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index cca8838..196cd81 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -48,9 +48,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index 3c9d968..6c5a306 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -100,9 +100,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on # Management Engine Interface 1 - register "HeciEnabled" = "1" - end + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2a52627..a084f67 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -253,9 +253,6 @@ * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 266c258..dd8db5b 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/pci_def.h> +#include <device/device.h> #include <intelblocks/cse.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> @@ -17,11 +17,11 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_cannonlake_config *config; + if (!CONFIG(HECI_DISABLE_USING_SMM)) + return; - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + if (!is_dev_enabled(dev)) heci_disable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Gerrit-Change-Number: 47195 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
by Felix Singer (Code Review) 13 Nov '20

13 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47195 ) Change subject: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Gerrit-Change-Number: 47195 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:29:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Michael Niewöhner (Code Review) 13 Nov '20

13 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… PS37, Line 442: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && isst_supported) > Nit, it would probably look better to move the checks inside […] Well, I did it this way because of https://review.coreboot.org/c/coreboot/+/45535/30/src/soc/intel/common/bloc… -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:27:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Nico Huber (Code Review) 13 Nov '20

13 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 37: (1 comment) https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 370: core > "no direct relation" is wrong imo, since the max value comes from dev_count_cpu ;) The point is, I d […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:20:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block: add code for ACPI CPPC entries generation
by Nico Huber (Code Review) 13 Nov '20

13 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block: add code for ACPI CPPC entries generation ...................................................................... Patch Set 37: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/37/src/soc/intel/common/bloc… PS37, Line 442: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPPC) && isst_supported) Nit, it would probably look better to move the checks inside the function (i.e. bail out if they fail). -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:18:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
by Nico Huber (Code Review) 13 Nov '20

13 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47195 ) Change subject: soc/intel/cnl: replace the remains of HeciEnabled by device state in dt ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Gerrit-Change-Number: 47195 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 13 Nov 2020 22:13:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020