coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Tim Wawrzynczak (Code Review) 18 Nov '20

18 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 9 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Nov 2020 20:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplem...
by Matthew Ziegelbaum (Code Review) 18 Nov '20

18 Nov '20

Matthew Ziegelbaum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47685 ) Change subject: mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented ...................................................................... mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented Ambassador is similar to puff. This change matches the PcieRpSlotImplemented configuration with Puff's, originally made for Puff in https://review.coreboot.org/c/coreboot/+/39986. Signed-off-by: Matt Ziegelbaum <ziegs(a)google.com> Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e --- M src/mainboard/google/hatch/variants/ambassador/overridetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47685/1 diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index 7b46153..7cc920d 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -402,8 +402,11 @@ register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/47685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e Gerrit-Change-Number: 47685 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ambassador: update fan table and usb configs
by Matthew Ziegelbaum (Code Review) 18 Nov '20

18 Nov '20

Matthew Ziegelbaum has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47556 ) Change subject: ambassador: update fan table and usb configs ...................................................................... ambassador: update fan table and usb configs BUG=b:173134210 TEST=flash to DUT Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5 Signed-off-by: Matt Ziegelbaum <ziegs(a)google.com> --- M src/mainboard/google/hatch/variants/ambassador/overridetree.cb 1 file changed, 97 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47556/1 diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb index adb00e4..71a1657 100644 --- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb @@ -1,6 +1,10 @@ chip soc/intel/cannonlake - # Enable heci communication - register "HeciEnabled" = "1" + register "tcc_offset" = "5" # TCC of 95C + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 51, + }" # Auto-switch between X4 NVMe and X2 NVMe. register "TetonGlacierMode" = "1" @@ -62,9 +66,6 @@ .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A port 0 - register "usb2_ports[6]" = "USB2_PORT_EMPTY" - register "usb2_ports[7]" = "USB2_PORT_EMPTY" - register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "{ .enable = 1, .ocpin = OC_SKIP, @@ -74,12 +75,76 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3 + register "usb3_ports[2]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x3d, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 0 + register "usb3_ports[5]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x00, + .tx_downscale_amp = 0x00, + .gen2_tx_rate0_uniq_tran_enable = 0, + .gen2_tx_rate0_uniq_tran = 0x00, + .gen2_tx_rate1_uniq_tran_enable = 0, + .gen2_tx_rate1_uniq_tran = 0x00, + .gen2_tx_rate2_uniq_tran_enable = 1, + .gen2_tx_rate2_uniq_tran = 0x4c, + .gen2_tx_rate3_uniq_tran_enable = 0, + .gen2_tx_rate3_uniq_tran = 0x00, + .gen2_rx_tuning_enable = 0x0f, + .gen2_rx_tuning_params = 0x45, + .gen2_rx_filter_sel = 0x44, + }" # Type-A Port 4 # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ @@ -208,29 +273,30 @@ chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" - register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1, + .thresholds={TEMP_PCT(70, 100), + TEMP_PCT(66, 90), + TEMP_PCT(62, 80), + TEMP_PCT(58, 70), + TEMP_PCT(53, 60), + TEMP_PCT(48, 50), + TEMP_PCT(43, 40), + TEMP_PCT(38, 30),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 15-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, @@ -239,7 +305,7 @@ .granularity = 200,}" register "controls.power_limits.pl2" = "{ .min_power = 25000, - .max_power = 64000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" @@ -370,6 +436,7 @@ device i2c 4a on end end end # I2C #3, Realtek RTD2142. + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -396,8 +463,11 @@ register "device_index" = "0" device pci 00.0 on end end + register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC - device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) + register "PcieRpSlotImplemented[10]" = "1" + end device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/47556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5 Gerrit-Change-Number: 47556 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/poppy/v/atlas: Reset bluetooth during boot
by Furquan Shaikh (Code Review) 18 Nov '20

18 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46620 ) Change subject: mb/google/poppy/v/atlas: Reset bluetooth during boot ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46620/4/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46620/4/src/mainboard/google/poppy… PS4, Line 198: DEEP What is the default state of GPP_E2? And is there an internal or external pull down on this line? If yes, then there is no additional work required to meet the timing. Configuring as DEEP ensures that the pad gets reset on any kind of reset (except S3/S4/S5). With default internal or external pull, BT_DISABLE_L will be pulled down and since this configuration happens in ramstage, it is guaranteed that you meet the 170ms+ of reset assertion. -- To view, visit https://review.coreboot.org/c/coreboot/+/46620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c489963f7a353e8fc5f55b6cba7aaee0b347a37 Gerrit-Change-Number: 46620 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Nov 2020 18:27:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update HPD1/2 GPIO as per latest schematics
by Subrata Banik (Code Review) 18 Nov '20

18 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47683 ) Change subject: mb/intel/adlrvp: Update HPD1/2 GPIO as per latest schematics ...................................................................... mb/intel/adlrvp: Update HPD1/2 GPIO as per latest schematics HPD_1: A19 -> E14 HPD_2: A20 -> A18 Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47683/1 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 039a437..a44d4ac 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -277,9 +277,9 @@ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), - /* HPD_1 (A19) and HPD_2 (A20) pins */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* HPD_1 (E14) and HPD_2 (A18) pins */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* IMGCLKOUT */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/47683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047 Gerrit-Change-Number: 47683 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in em100[master]: README: Move usage to the bottom
by Stefan Reinauer (Code Review) 18 Nov '20

18 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47648 ) Change subject: README: Move usage to the bottom ...................................................................... README: Move usage to the bottom Right now the usage string is separated from the explanation of options by a list of features. Clean up to make README more coherent. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I6f7c4d57fbecdac18e95fc9dc08ed8d857e4bf34 --- M README 1 file changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/48/47648/1 diff --git a/README b/README index a76d34e..3509d58 100644 --- a/README +++ b/README @@ -10,9 +10,6 @@ providing a much faster development cycle than is possible by reprogramming the SPI flash each time. -Example: - ./em100 --stop --set M25P80 -d file.bin --start -t -O 0xfff00000 - Major features provided by the tool include: - Set the chip being emulated (the tool supports about 600) @@ -22,7 +19,10 @@ - Output a trace of SPI commands issued by the SoC - Reading / writing em100 firmware (dangerous as it can brick your em100) -For help, use the -h option: +[1] https://www.dediprog.com/product/EM100Pro-G2 + +Example: + ./em100 --stop --set M25P80 -d file.bin -v --start -t -O 0xfff00000 Usage: -c|--set CHIP: select chip emulation @@ -36,20 +36,17 @@ -t|--trace: trace mode -O|--offset HEX_VAL: address offset for trace mode -T|--terminal: terminal mode - -F|--firmware-update FILE: update EM100pro firmware (dangerous) + -F|--firmware-update FILE|auto: update EM100pro firmware (dangerous) -f|--firmware-dump FILE: export raw EM100pro firmware to file -g|--firmware-write FILE: export EM100pro firmware to DPFW file -S|--set-serialno NUM: set serial number to NUM -V|--set-voltage [1.8|3.3] switch FPGA voltage -p|--holdpin [LOW|FLOAT|INPUT]: set the hold pin state -x|--device BUS:DEV use EM100pro on USB bus/device - -x|--device DPxxxxxx use EM100pro with serial no DPxxxxxx + -x|--device EMxxxxxx use EM100pro with serial no EMxxxxxx -l|--list-devices list all connected EM100pro devices -U|--update-files update device (chip) and firmware database -C|--compatible enable compatibility mode (patch image for EM100Pro) -D|--debug: print debug information. -h|--help: this help text - -[1] https://www.dediprog.com/product/EM100Pro-G2 - -- To view, visit https://review.coreboot.org/c/em100/+/47648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I6f7c4d57fbecdac18e95fc9dc08ed8d857e4bf34 Gerrit-Change-Number: 47648 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ids: add model number to AMD GBE controller
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47678 ) Change subject: include/device/pci_ids: add model number to AMD GBE controller ...................................................................... include/device/pci_ids: add model number to AMD GBE controller Change-Id: I4499c383e63cd12a0fc11efd94ef396d9ad23789 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47678/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d1a4744..c8d0c9a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -475,7 +475,7 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD 0x7906 #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E -#define PCI_DEVICE_ID_AMD_FAM17H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 #define PCI_DEVICE_ID_ATI_FAM17H_GPU 0x15D8 #define PCI_DEVICE_ID_ATI_FAM17H_HDA0 0x15DE -- To view, visit https://review.coreboot.org/c/coreboot/+/47678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4499c383e63cd12a0fc11efd94ef396d9ad23789 Gerrit-Change-Number: 47678 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ids: add model number to PCIe port and bus devices
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47677 ) Change subject: include/device/pci_ids: add model number to PCIe port and bus devices ...................................................................... include/device/pci_ids: add model number to PCIe port and bus devices Different models within family 17h have different PCI IDs for their PCIe GPP port and internal bus devices. Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h M src/soc/amd/picasso/pcie_gpp.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47677/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7dacb65..d1a4744 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -453,9 +453,9 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB -#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 96d33f2..3c3021e 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -48,8 +48,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA, - PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB, 0 }; @@ -72,5 +72,5 @@ static const struct pci_driver external_pcie_gpp_driver __pci_driver = { .ops = &external_pcie_gpp_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP, + .device = PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030 Gerrit-Change-Number: 47677 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ids: add model number to data fabric devices
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47676 ) Change subject: include/device/pci_ids: add model number to data fabric devices ...................................................................... include/device/pci_ids: add model number to data fabric devices Different models within family 17h have different PCI IDs for their data fabric PCI devices. Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h M src/soc/amd/picasso/data_fabric.c 2 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47676/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cb2d2dd..7dacb65 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -461,13 +461,13 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 -#define PCI_DEVICE_ID_AMD_FAM17H_DF0 0x15E8 -#define PCI_DEVICE_ID_AMD_FAM17H_DF1 0x15E9 -#define PCI_DEVICE_ID_AMD_FAM17H_DF2 0x15EA -#define PCI_DEVICE_ID_AMD_FAM17H_DF3 0x15EB -#define PCI_DEVICE_ID_AMD_FAM17H_DF4 0x15EC -#define PCI_DEVICE_ID_AMD_FAM17H_DF5 0x15ED -#define PCI_DEVICE_ID_AMD_FAM17H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3 0x15EB +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index ac4e23d..79fdba1 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -123,19 +123,19 @@ static const char *data_fabric_acpi_name(const struct device *dev) { switch (dev->device) { - case PCI_DEVICE_ID_AMD_FAM17H_DF0: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0: return "DFD0"; - case PCI_DEVICE_ID_AMD_FAM17H_DF1: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1: return "DFD1"; - case PCI_DEVICE_ID_AMD_FAM17H_DF2: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2: return "DFD2"; - case PCI_DEVICE_ID_AMD_FAM17H_DF3: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3: return "DFD3"; - case PCI_DEVICE_ID_AMD_FAM17H_DF4: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4: return "DFD4"; - case PCI_DEVICE_ID_AMD_FAM17H_DF5: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5: return "DFD5"; - case PCI_DEVICE_ID_AMD_FAM17H_DF6: + case PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6: return "DFD6"; default: printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); @@ -152,13 +152,13 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_DF0, - PCI_DEVICE_ID_AMD_FAM17H_DF1, - PCI_DEVICE_ID_AMD_FAM17H_DF2, - PCI_DEVICE_ID_AMD_FAM17H_DF3, - PCI_DEVICE_ID_AMD_FAM17H_DF4, - PCI_DEVICE_ID_AMD_FAM17H_DF5, - PCI_DEVICE_ID_AMD_FAM17H_DF6, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20 Gerrit-Change-Number: 47676 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/pci_ids: deduplicate AMD family 17h northbridge ID
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47675 ) Change subject: include/device/pci_ids: deduplicate AMD family 17h northbridge ID ...................................................................... include/device/pci_ids: deduplicate AMD family 17h northbridge ID The code uses PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB instead; Change-Id: Ia88550d377643741f78ff068e57d6a2d783306f3 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47675/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8531d04..cb2d2dd 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -453,7 +453,6 @@ #define PCI_DEVICE_ID_AMD_CZ_USB3_0 0x7914 #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B -#define PCI_DEVICE_ID_AMD_FAM17H_GNB 0x15D0 #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC -- To view, visit https://review.coreboot.org/c/coreboot/+/47675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88550d377643741f78ff068e57d6a2d783306f3 Gerrit-Change-Number: 47675 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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