coreboot-gerrit November 2020

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Change in coreboot[master]: include/device/pci_ids: use the right device ID for AMD Picasso GPU
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47674 ) Change subject: include/device/pci_ids: use the right device ID for AMD Picasso GPU ...................................................................... include/device/pci_ids: use the right device ID for AMD Picasso GPU The code that uses the GPU device ID uses the correct ATI vendor ID, but the description wrongly used AMD as vendor. In the AMD APUs the GPU PCI device and the corresponding audio controller use the ATI PCI vendor ID while all other PCI devices in the SoC use the AMD PCI vendor ID. Also move the two entries in a separate section right below the one they were in. Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/graphics/graphics.c 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47674/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 675acc4..8531d04 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -455,10 +455,8 @@ #define PCI_DEVICE_ID_AMD_FAM17H_GNB 0x15D0 #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP 0x15D3 -#define PCI_DEVICE_ID_AMD_FAM17H_GPU 0x15D8 #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA 0x15DB #define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB 0x15DC -#define PCI_DEVICE_ID_AMD_FAM17H_HDA0 0x15DE #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 @@ -480,6 +478,9 @@ #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E #define PCI_DEVICE_ID_AMD_FAM17H_GBE 0x1458 +#define PCI_DEVICE_ID_ATI_FAM17H_GPU 0x15D8 +#define PCI_DEVICE_ID_ATI_FAM17H_HDA0 0x15DE + #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 #define PCI_DEVICE_ID_VLSI_82C593 0x0006 diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index 24cabfe..d9cdd1a 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -128,7 +128,7 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_GPU, + PCI_DEVICE_ID_ATI_FAM17H_GPU, 0, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b5bd4638f5b07c487f223321872563b36337e9 Gerrit-Change-Number: 47674 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WA] Boldar : Use GPIO H10/H11 for UART 0
by Aamir Bohra (Code Review) 18 Nov '20

18 Nov '20

Aamir Bohra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47601 ) Change subject: [WA] Boldar : Use GPIO H10/H11 for UART 0 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/47601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd063a0120a3c80f76e0eb918b3468a980119de3 Gerrit-Change-Number: 47601 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Sowmya V <v.sowmya(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-CC: Curtis Chen <curtis.chen(a)intel.corp-partner.google.com> Gerrit-CC: Cyan Yang <cyan.yang(a)intel.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbol
by Felix Held (Code Review) 18 Nov '20

18 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47672 ) Change subject: soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbol ...................................................................... soc/amd/common: remove SOC_AMD_COMMON_BLOCK Kconfig symbol SOC_AMD_COMMON needs to be selected to be able to select SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig files from the sub-folders simplifies this a bit. Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/Kconfig M src/soc/amd/common/Makefile.inc D src/soc/amd/common/block/Kconfig M src/soc/amd/common/block/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/cimx/sb800/Kconfig M src/southbridge/amd/pi/hudson/Kconfig 9 files changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47672/1 diff --git a/src/soc/amd/common/Kconfig b/src/soc/amd/common/Kconfig index debedac..a0836a3 100644 --- a/src/soc/amd/common/Kconfig +++ b/src/soc/amd/common/Kconfig @@ -1,7 +1,7 @@ config SOC_AMD_COMMON bool help - common code for AMD SOCs + common code blocks for AMD SOCs if SOC_AMD_COMMON @@ -9,6 +9,6 @@ bool default n -source "src/soc/amd/common/block/Kconfig" +source "src/soc/amd/common/block/*/Kconfig" endif # SOC_AMD_COMMON diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index 2a5b42a..c0757c5 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -1,5 +1 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON),y) - -subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block - -endif +subdirs-$(CONFIG_SOC_AMD_COMMON) += block diff --git a/src/soc/amd/common/block/Kconfig b/src/soc/amd/common/block/Kconfig deleted file mode 100644 index 86150ed..0000000 --- a/src/soc/amd/common/block/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -config SOC_AMD_COMMON_BLOCK - bool - help - SoC driver for AMD common IP code - -if SOC_AMD_COMMON_BLOCK - -comment "AMD SoC Common IP Code" -source "src/soc/amd/common/block/*/Kconfig" - -endif diff --git a/src/soc/amd/common/block/Makefile.inc b/src/soc/amd/common/block/Makefile.inc index 33c8822..ad75b92 100644 --- a/src/soc/amd/common/block/Makefile.inc +++ b/src/soc/amd/common/block/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK),y) +ifeq ($(CONFIG_SOC_AMD_COMMON),y) subdirs-y += ./* diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9ebc651..4d7d2a6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,7 +29,6 @@ select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0e32005..86df361 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -23,7 +23,6 @@ select TSC_SYNC_LFENCE select SOC_AMD_PI select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e61bc85..b755fe1 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -15,7 +15,6 @@ select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO config EHCI_BAR diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 8379d23..96737cf 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -9,7 +9,6 @@ select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO if SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index cfe85a1..6a1a9c8 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -18,7 +18,6 @@ select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK select SOC_AMD_COMMON_BLOCK_ACPIMMIO config EHCI_BAR -- To view, visit https://review.coreboot.org/c/coreboot/+/47672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6 Gerrit-Change-Number: 47672 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Create galtic variant
by Paul Fagerburg (Code Review) 18 Nov '20

18 Nov '20

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47361 ) Change subject: mb/google/dedede: Create galtic variant ...................................................................... Patch Set 2: -Code-Review Removing code review vote until we get issues sorted out -- To view, visit https://review.coreboot.org/c/coreboot/+/47361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ae40b2ddc92411c980e1fc08da3023c4e9435b6 Gerrit-Change-Number: 47361 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 18 Nov 2020 15:26:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/rx6110sa: Add basic ACPI support
by Werner Zeh (Code Review) 18 Nov '20

18 Nov '20

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47235 ) Change subject: drivers/i2c/rx6110sa: Add basic ACPI support ...................................................................... drivers/i2c/rx6110sa: Add basic ACPI support This patch adds basic ACPI support for the RTC so that the OS is able to use this RTC via the ACPI interface. Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/chip.h M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/rx6110sa/rx6110sa.h 3 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47235/1 diff --git a/src/drivers/i2c/rx6110sa/chip.h b/src/drivers/i2c/rx6110sa/chip.h index 46ef7f1..feb9133 100644 --- a/src/drivers/i2c/rx6110sa/chip.h +++ b/src/drivers/i2c/rx6110sa/chip.h @@ -3,6 +3,7 @@ #include "rx6110sa.h" struct drivers_i2c_rx6110sa_config { + unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz)*/ /* The day (of the week) is indicated by 7 bits, bit 0 to bit 6. */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ @@ -23,4 +24,9 @@ unsigned char bks_on; unsigned char bks_off; unsigned char iocut_en; /* Disable backup of I/O circuit. */ + + const char *hid; /* ACPI _HID (required) */ + const char *desc; /* ACPI device description */ + const char *name; /* ACPI device name (optional) */ + }; diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index ca39bdb..e758728 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> #include <device/i2c_bus.h> #include <device/device.h> #include <version.h> @@ -163,11 +165,67 @@ rx6110sa_write(dev, CTRL_REG, reg); } +#if CONFIG(HAVE_ACPI_TABLES) +static void rx6110sa_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_rx6110sa_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + if (!dev->enabled || !scope) + return; + + if (!config->hid) { + printk(BIOS_ERR, "ERROR: HID for %s required\n", dev_path(dev)); + return; + } + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->hid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + dev->chip_ops->name, dev_path(dev)); +} + +/* Use name specified in config or take a fixed name. */ +static const char *rx6110sa_acpi_name(const struct device *dev) +{ + struct drivers_i2c_rx6110sa_config *config = dev->chip_info; + + if (config->name && strlen(config->name) == RX6110SA_ACPI_NAME_LEN) + return config->name; + else + return RX6110SA_ACPI_NAME; +} +#endif + static struct device_operations rx6110sa_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = rx6110sa_init, - .final = rx6110sa_final + .final = rx6110sa_final, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = rx6110sa_acpi_name, + .acpi_fill_ssdt = rx6110sa_fill_ssdt, +#endif }; static void rx6110sa_enable(struct device *dev) diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index 187bad4..91685e9 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -7,6 +7,9 @@ #define RX6110SA_SLAVE_ADR 0x32 #define RX6110SA_I2C_CONTROLLER 0 +#define RX6110SA_ACPI_NAME "ERX6" +#define RX6110SA_ACPI_NAME_LEN 4 + /* Register layout */ #define SECOND_REG 0x10 #define MINUTE_REG 0x11 -- To view, visit https://review.coreboot.org/c/coreboot/+/47235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b319e3088e6511592075b055f8fa3e2aedaa209 Gerrit-Change-Number: 47235 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI S3: Minor cleanup
by Kyösti Mälkki (Code Review) 18 Nov '20

18 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42613 ) Change subject: ACPI S3: Minor cleanup ...................................................................... ACPI S3: Minor cleanup Drop extra function in the middle and adjust the post_code() to happen wright before jump to wakeup vector. Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_s3.c 1 file changed, 8 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42613/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index fef04ac..814719a 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -56,18 +56,6 @@ extern unsigned char __wakeup; extern unsigned int __wakeup_size; -static void acpi_jump_to_wakeup(void *vector) -{ - /* Copy wakeup trampoline in place. */ - memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); - - set_boot_successful(); - - timestamp_add_now(TS_ACPI_WAKE_JUMP); - - acpi_do_wakeup((uintptr_t)vector); -} - void __weak mainboard_suspend_resume(void) { } @@ -88,8 +76,15 @@ /* Call mainboard resume handler first, if defined. */ mainboard_suspend_resume(); + /* Copy wakeup trampoline in place. */ + memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); + + set_boot_successful(); + + timestamp_add_now(TS_ACPI_WAKE_JUMP); + post_code(POST_OS_RESUME); - acpi_jump_to_wakeup(wake_vec); + acpi_do_wakeup((uintptr_t)wake_vec); die("Failed the jump to wakeup vector\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I951c3292f5dbf52a58471da9de94b0c4f4ca7c20 Gerrit-Change-Number: 42613 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/smsc/sio1036: Support 16-bit IO port addressing
by Nikolai Vyssotski (Code Review) 18 Nov '20

18 Nov '20

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47647 ) Change subject: superio/smsc/sio1036: Support 16-bit IO port addressing ...................................................................... superio/smsc/sio1036: Support 16-bit IO port addressing SMSC/Microchip 1036 can be strapped to 4E/4D and 164E/164D so make source code support 16 bits addressing. Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/superio/smsc/sio1036/sio1036_early_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47647/1 diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index a65f672..c4a580a 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -10,13 +10,13 @@ static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0xaa, port); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbe6f5b6dbd74299b34b0717e618dc736e7ad6f Gerrit-Change-Number: 47647 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: arch/x86/spinlock: Drop linker section in inline assembly
by Patrick Rudolph (Code Review) 18 Nov '20

18 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46839 ) Change subject: arch/x86/spinlock: Drop linker section in inline assembly ...................................................................... arch/x86/spinlock: Drop linker section in inline assembly The linker section isn't required or specified in the linker script. This confuses GCC and prevents garbage collecting functions using spinlocks, which might cause linker errors. Tested by compiling the C SIPI vector with spinlocks. Change-Id: Ia4f5a8f4aec0e05bc35359b334845c177867d4a4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/smp/spinlock.h 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46839/1 diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 799ac2c..37e3eaf 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -35,13 +35,11 @@ "\n1:\t" \ "lock ; decb %0\n\t" \ "js 2f\n" \ - ".section .text.lock,\"ax\"\n" \ "2:\t" \ "cmpb $0,%0\n\t" \ "rep;nop\n\t" \ "jle 2b\n\t" \ - "jmp 1b\n" \ - ".previous" + "jmp 1b\n" /* * This works. Despite all the confusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/46839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4f5a8f4aec0e05bc35359b334845c177867d4a4 Gerrit-Change-Number: 46839 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 18 Nov '20

18 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 54: (1 comment) https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39133/48//COMMIT_MSG@34 PS48, Line 34: without video > Using non-zero PrimaryDisplay on FSP-M might serve as a work-around for this problem I tested this with PrimaryDisplay set to 2. -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 54 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Nov 2020 09:30:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Caveh Jalali (Code Review) 18 Nov '20

18 Nov '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... Patch Set 9: (6 comments) https://review.coreboot.org/c/coreboot/+/47501/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47501/7//COMMIT_MSG@7 PS7, Line 7: Config for passive USB-C DB on C1 > Plesae make it a statement by adding a verb (in imperative mood): […] Done https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/Kconfig: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 153: VARIANT_HAS_PASSIVE_USB_DB > I don't think this is necessary. […] Done https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… PS2, Line 131: x04; /* port2 retimer disable */ > these are in the EDS, but not available in published header files. […] Done https://review.coreboot.org/c/coreboot/+/47501/7/src/mainboard/google/volte… File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/47501/7/src/mainboard/google/volte… PS7, Line 129: #if CONFIG(VARIANT_HAS_PASSIVE_USB_DB) : /* Set up port C1 for USB3 passive DB */ : if (fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { : /* : * TGL UP3/UP4 Processor EDS vol. 2a rev. 1.2 : * section 3.6.10 : * set IOM_TYPEC_SW_CONFIGURATION_4.PORT2_HSL_ORIENTATION_OVRRD_EN : */ : cfg->TcssAuxOri |= IOM_TCSS_PORT_CTRL(1, : IOM_TCSS_ORI_NORMAL, IOM_TCSS_MUX_INTERNAL); : cfg->IomTypeCPortPadCfg[2] = GPIO_ID_TCP1_AUXP_DC; : cfg->IomTypeCPortPadCfg[3] = GPIO_ID_TCP1_AUXN_DC; : } : #endif /* VARIANT_HAS_PASSIVE_USB_DB */ > suggestion: […] Done https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/47501/3/src/mainboard/google/volte… PS3, Line 34: #define TGL_GPIO_ID_GPP_E22 0x090E0016 : #define TGL_GPIO_ID_GPP_E23 0x090E0017 : > that's a question for brandon.breitenstein(a)intel.com. […] Done https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h: https://review.coreboot.org/c/coreboot/+/47501/2/src/mainboard/google/volte… PS2, Line 34: 0x090E0016 > i couldn't find any published macros to compose this value. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 9 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Nov 2020 07:08:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit November 2020