coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common/acpi: move S0ix UUID to the condition
by Nico Huber (Code Review) 19 Nov '20

19 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: move S0ix UUID to the condition ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG@10 PS1, Line 10: PEPD > How about you rename this first to give the commit message some meaning? Sorry, that was a stale draft. Might have made sense, though, idk. -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Nov 2020 23:31:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: drop the southridge scope around PEPD
by Nico Huber (Code Review) 19 Nov '20

19 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47246 ) Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD ...................................................................... soc/intel/common/acpi: drop the southridge scope around PEPD PEPD will get included directly in the southbridge. Thus, drop the scope around it. Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47246 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 74 insertions(+), 77 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 6159685..19ec558 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -14,90 +14,87 @@ External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -Scope(\_SB) +Device(LPID) { - Device(LPID) + Name(_ADR, 0x00000000) + Name(_CID, EISAID("PNP0D80")) + Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) + Method(_DSM, 4) { - Name(_ADR, 0x00000000) - Name(_CID, EISAID("PNP0D80")) - Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) - Method(_DSM, 4) - { - If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) + If(Arg0 == ^UUID) { + /* + * Enum functions + */ + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(1) - } - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(1) - } - - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ - If (CondRefOf (\_SB.PCI0.EGPM)) - { - \_SB.PCI0.EGPM () - } + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) } + /* - * Function 6 - Low Power S0 Exit Notification + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(0) - } - - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (\_SB.PCI0.RGPM)) - { - \_SB.PCI0.RGPM () - } + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () } } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } - Return(Buffer(One) {0x00}) - } // Method(_DSM) - } // Device (LPID) -} // End Scope(\_SB) + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } + } + } + + Return(Buffer(One) {0x00}) + } // Method(_DSM) +} // Device (LPID) -- To view, visit https://review.coreboot.org/c/coreboot/+/47246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Gerrit-Change-Number: 47246 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/sandybridge: Correct some whitespace issues
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47570 ) Change subject: nb/intel/sandybridge: Correct some whitespace issues ...................................................................... nb/intel/sandybridge: Correct some whitespace issues Add a missing tab and remove spurious spaces in the IOSAV structs. Change-Id: If588d3f01c8744fd0c83576a56cfdda2fb43a3bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/47570/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index f9f1f7d..697167a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -660,7 +660,7 @@ /* DRAM command MRS */ [2] = { .sp_cmd_ctrl = { - .command = IOSAV_MRS, + .command = IOSAV_MRS, }, .subseq_ctrl = { .cmd_executions = 1, @@ -831,7 +831,7 @@ /* DRAM command NOP (without ODT nor chip selects) */ [0] = { .sp_cmd_ctrl = { - .command = IOSAV_NOP & ~(0xff << 8), + .command = IOSAV_NOP & ~(0xff << 8), }, .subseq_ctrl = { .cmd_executions = 1, @@ -865,8 +865,8 @@ .rank = 0, }, .addr_update = { - .inc_rank = 1, - .addr_wrap = 20, + .inc_rank = 1, + .addr_wrap = 20, }, }, }; @@ -1506,7 +1506,7 @@ .rank = slotrank, }, .addr_update = { - .addr_wrap = 18, + .addr_wrap = 18, }, }, }; @@ -2294,7 +2294,7 @@ } FOR_ALL_POPULATED_CHANNELS - program_timings(ctrl, channel); + program_timings(ctrl, channel); reprogram_320c(ctrl); return 0; @@ -2893,7 +2893,7 @@ .rank = slotrank, }, .addr_update = { - .addr_wrap = 18, + .addr_wrap = 18, }, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If588d3f01c8744fd0c83576a56cfdda2fb43a3bd Gerrit-Change-Number: 47570 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clean up `dram_mr2` function
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47569 ) Change subject: nb/intel/sandybridge: Clean up `dram_mr2` function ...................................................................... nb/intel/sandybridge: Clean up `dram_mr2` function Constify variables, and also remove pointless and-masks on mr2reg. Change-Id: I3829012ff7d41f4308ee84d6fbf3b1f2803431af Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47569/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d166292..0f1b2d8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -767,22 +767,19 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) { - u16 pasr, cwl, mr2reg; - odtmap odt; + const u16 pasr = 0; + const u16 cwl = ctrl->CWL - 5; + const odtmap odt = get_ODT(ctrl, channel); + int srt = 0; - - pasr = 0; - cwl = ctrl->CWL - 5; - odt = get_ODT(ctrl, channel); - if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; - mr2reg = 0; - mr2reg = (mr2reg & ~0x07) | pasr; - mr2reg = (mr2reg & ~0x38) | (cwl << 3); - mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); - mr2reg = (mr2reg & ~0x80) | (srt << 7); + u16 mr2reg = 0; + mr2reg |= pasr; + mr2reg |= cwl << 3; + mr2reg |= ctrl->auto_self_refresh << 6; + mr2reg |= srt << 7; mr2reg |= (odt.rttwr / 60) << 9; write_mrreg(ctrl, channel, rank, 2, mr2reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/47569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3829012ff7d41f4308ee84d6fbf3b1f2803431af Gerrit-Change-Number: 47569 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47568 ) Change subject: nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM ...................................................................... nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAM Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz. Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47568/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 095d853..d166292 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -769,13 +769,14 @@ { u16 pasr, cwl, mr2reg; odtmap odt; - int srt; + int srt = 0; pasr = 0; cwl = ctrl->CWL - 5; odt = get_ODT(ctrl, channel); - srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) + srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; mr2reg = 0; mr2reg = (mr2reg & ~0x07) | pasr; -- To view, visit https://review.coreboot.org/c/coreboot/+/47568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Gerrit-Change-Number: 47568 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Drop unused `rank` parameter
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47518 ) Change subject: nb/intel/sandybridge: Drop unused `rank` parameter ...................................................................... nb/intel/sandybridge: Drop unused `rank` parameter Change-Id: I5476bbe1a99d087bc026dc5646c8440c50dd151e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/47518/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 45f7a99..4bdb82d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -716,7 +716,7 @@ write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); } -static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) +static odtmap get_ODT(ramctr_timing *ctrl, int channel) { /* Get ODT based on rankmap */ int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); @@ -748,7 +748,7 @@ odtmap odt; u32 mr1reg; - odt = get_ODT(ctrl, rank, channel); + odt = get_ODT(ctrl, channel); mr1reg = 2; mr1reg |= encode_odt(odt.rttnom); @@ -773,7 +773,7 @@ pasr = 0; cwl = ctrl->CWL - 5; - odt = get_ODT(ctrl, rank, channel); + odt = get_ODT(ctrl, channel); srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; -- To view, visit https://review.coreboot.org/c/coreboot/+/47518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5476bbe1a99d087bc026dc5646c8440c50dd151e Gerrit-Change-Number: 47518 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Relocate `get_ODT` function
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47517 ) Change subject: nb/intel/sandybridge: Relocate `get_ODT` function ...................................................................... nb/intel/sandybridge: Relocate `get_ODT` function Change-Id: I21d3e04de45f58cef0603b6b75119cae4b1a7aae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47517/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 127b493..45f7a99 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -607,18 +607,6 @@ } } -static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) -{ - /* Get ODT based on rankmap */ - int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); - - if (dimms_per_ch == 1) { - return (const odtmap){60, 60}; - } else { - return (const odtmap){120, 30}; - } -} - static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) { wait_for_iosav(channel); @@ -728,6 +716,18 @@ write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); } +static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) +{ + /* Get ODT based on rankmap */ + int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); + + if (dimms_per_ch == 1) { + return (const odtmap){60, 60}; + } else { + return (const odtmap){120, 30}; + } +} + static u32 encode_odt(u32 odt) { switch (odt) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21d3e04de45f58cef0603b6b75119cae4b1a7aae Gerrit-Change-Number: 47517 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clean up MR0 composition
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47516 ) Change subject: nb/intel/sandybridge: Clean up MR0 composition ...................................................................... nb/intel/sandybridge: Clean up MR0 composition There's no need to use and-masks here. Change-Id: If06352daf53ce278dfc64102e023e4f1ea78385c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47516/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3d82a00..127b493 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -700,9 +700,6 @@ static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; - /* DLL Reset - self clearing - set after CLK frequency has been changed */ - mr0reg = 1 << 8; - /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { mch_cas = (u16) ((ctrl->CAS - 4) << 1); @@ -714,12 +711,15 @@ /* Convert tWR to MCH register friendly */ mch_wr = mch_wr_t[ctrl->tWR - 5]; - mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); - mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); - mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); + /* DLL Reset - self clearing - set after CLK frequency has been changed */ + mr0reg = 1 << 8; + + mr0reg |= (mch_cas & 0x1) << 2; + mr0reg |= (mch_cas & 0xe) << 3; + mr0reg |= mch_wr << 9; /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); + mr0reg |= !is_mobile << 12; return mr0reg; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If06352daf53ce278dfc64102e023e4f1ea78385c Gerrit-Change-Number: 47516 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI: Define acpi_get_preferred_pm_profile()
by Kyösti Mälkki (Code Review) 19 Nov '20

19 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42140 ) Change subject: ACPI: Define acpi_get_preferred_pm_profile() ...................................................................... ACPI: Define acpi_get_preferred_pm_profile() Change-Id: I2e7f22ccccc6c0df8e7e9f354c50893a53a41714 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/arch/x86/Makefile.inc A src/arch/x86/acpi_pm.c M src/include/acpi/acpi.h 4 files changed, 27 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42140/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 8bf4b49..24c6911 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1245,14 +1245,7 @@ fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) - fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) - fadt->preferred_pm_profile = PM_TABLET; - else - fadt->preferred_pm_profile = PM_DESKTOP; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); acpi_fill_fadt(fadt); diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0dd8d2b..d290c26 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -227,6 +227,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) +ramstage-y += acpi_pm.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += c_start.S diff --git a/src/arch/x86/acpi_pm.c b/src/arch/x86/acpi_pm.c new file mode 100644 index 0000000..edc6706 --- /dev/null +++ b/src/arch/x86/acpi_pm.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <smbios.h> + +uint8_t acpi_get_preferred_pm_profile(void) +{ + int enclosure = smbios_mainboard_enclosure_type(); + + switch (enclosure) { + case SMBIOS_ENCLOSURE_LAPTOP: + case SMBIOS_ENCLOSURE_CONVERTIBLE: + return PM_MOBILE; + case SMBIOS_ENCLOSURE_DETACHABLE: + case SMBIOS_ENCLOSURE_TABLET: + return PM_TABLET; + case SMBIOS_ENCLOSURE_DESKTOP: + return PM_DESKTOP; + case SMBIOS_ENCLOSURE_UNKNOWN: + default: + return PM_UNSPECIFIED; + } +} diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e6c18c2..b3f70d6 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1013,6 +1013,8 @@ } #endif +uint8_t acpi_get_preferred_pm_profile(void); + /* Returns ACPI_Sx values. */ int acpi_get_sleep_type(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7f22ccccc6c0df8e7e9f354c50893a53a41714 Gerrit-Change-Number: 42140 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: APCI S3: Split arch-agnostic parts
by Kyösti Mälkki (Code Review) 19 Nov '20

19 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42614 ) Change subject: APCI S3: Split arch-agnostic parts ...................................................................... APCI S3: Split arch-agnostic parts Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Makefile.inc A src/acpi/acpi_pm.c M src/arch/x86/Makefile.inc M src/arch/x86/acpi_s3.c 4 files changed, 48 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42614/1 diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 7e37e1a..108f427 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dsm.c ramstage-y += acpigen_ps2_keybd.c @@ -12,6 +13,8 @@ ramstage-y += sata.c ramstage-y += soundwire.c +postcar-y += acpi_pm.c + ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c endif diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c new file mode 100644 index 0000000..b88b761 --- /dev/null +++ b/src/acpi/acpi_pm.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <romstage_handoff.h> + +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1; + +static void acpi_handoff_wakeup(void) +{ + if (acpi_slp_type < 0) { + if (romstage_handoff_is_resume()) { + printk(BIOS_DEBUG, "S3 Resume\n"); + acpi_slp_type = ACPI_S3; + } else { + printk(BIOS_DEBUG, "Normal boot\n"); + acpi_slp_type = ACPI_S0; + } + } +} + +int acpi_is_wakeup(void) +{ + acpi_handoff_wakeup(); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); +} + +int acpi_is_wakeup_s3(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S3); +} + +int acpi_is_wakeup_s4(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S4); +} + +void __weak mainboard_suspend_resume(void) +{ +} diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6297384..6773b270 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -157,7 +157,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-y += boot.c romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C @@ -198,7 +197,6 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ -postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += post.c postcar-y += gdt_init.S @@ -235,7 +233,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +ramstage-y += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += post.c diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 814719a..8017dff 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -9,45 +9,6 @@ #include <cpu/x86/smm.h> #include <fallback.h> #include <timestamp.h> -#include <romstage_handoff.h> - -#if ENV_RAMSTAGE || ENV_POSTCAR - -/* This is filled with acpi_is_wakeup() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_is_wakeup(void) -{ - acpi_handoff_wakeup(); - /* Both resume from S2 and resume from S3 restart at CPU reset */ - return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); -} - -int acpi_is_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - -int acpi_is_wakeup_s4(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S4); -} -#endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 @@ -56,10 +17,6 @@ extern unsigned char __wakeup; extern unsigned int __wakeup_size; -void __weak mainboard_suspend_resume(void) -{ -} - void __noreturn acpi_resume(void *wake_vec) { if (CONFIG(HAVE_SMI_HANDLER)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Gerrit-Change-Number: 42614 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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