coreboot-gerrit November 2020

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 19 Nov '20

19 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 57: (1 comment) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/ramstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 41: LPSS_S0ixEnable > Is this meant to be enabled? Yes, enabled. I'm not sure about this, but judging by the documentation, it is set to enable on all Kontron boards with Atom processor -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 57 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Nov 2020 22:57:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: rename PEPD/LPI macros for clarification
by Nico Huber (Code Review) 19 Nov '20

19 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47247 ) Change subject: soc/intel/common/acpi: rename PEPD/LPI macros for clarification ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6 Gerrit-Change-Number: 47247 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Nov 2020 22:57:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Nico Huber (Code Review) 19 Nov '20

19 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Nov 2020 22:55:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Rewrite magic numbers
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47511 ) Change subject: nb/intel/sandybridge: Rewrite magic numbers ...................................................................... nb/intel/sandybridge: Rewrite magic numbers Use bitwise negations for AND-masks and shifts for bitfields. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Id265728c362a5035ac57f84766e883608f29c398 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 34 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47511/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ec5d59a..5d4a767 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -27,9 +27,9 @@ static void toggle_io_reset(void) { u32 r32 = MCHBAR32(MC_INIT_STATE_G); - MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); udelay(1); - MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; + MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); udelay(1); } @@ -130,11 +130,11 @@ stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -208,7 +208,7 @@ printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + MCHBAR32_OR(TC_RFP_ch(channel), 0xff); /* Self-refresh timing parameters */ reg = 0; @@ -561,19 +561,19 @@ MCHBAR32(MC_INIT_STATE_G) = reg; /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); /* XXX Wait 20ns */ udelay(1); @@ -688,7 +688,7 @@ const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; /* DLL Reset - self clearing - set after CLK frequency has been changed */ - mr0reg = 0x100; + mr0reg = 1 << 8; /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { @@ -854,10 +854,10 @@ } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); wait_for_iosav(channel); @@ -946,7 +946,7 @@ MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); - reg_io_latency &= 0xffff0000; + reg_io_latency &= ~0xffff; reg_roundtrip_latency = 0; @@ -1660,7 +1660,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { /* enable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7); wait_for_iosav(channel); @@ -1712,7 +1712,8 @@ wait_for_iosav(channel); /* disable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, + make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); } static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) @@ -1930,15 +1931,15 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -1948,7 +1949,7 @@ Only NOP is allowed in this mode */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 0x1080); + make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); MCHBAR32(GDCRTRAININGMOD) = 0x108052; @@ -1971,10 +1972,10 @@ wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); @@ -2118,11 +2119,11 @@ iosav_run_once(channel); wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); @@ -2888,7 +2889,7 @@ {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; + MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; @@ -2910,7 +2911,7 @@ FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); } udelay(1); @@ -2940,7 +2941,7 @@ dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | + MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; } } @@ -2949,8 +2950,8 @@ { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; + MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); } } @@ -2974,7 +2975,7 @@ MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3015,8 +3016,8 @@ FOR_ALL_CHANNELS MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); - MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); + MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel */ @@ -3042,7 +3043,7 @@ /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } @@ -3073,11 +3074,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); } printram("CPE\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id265728c362a5035ac57f84766e883608f29c398 Gerrit-Change-Number: 47511 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Remove now-unnecessary sequence macros
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47504 ) Change subject: nb/intel/sandybridge: Remove now-unnecessary sequence macros ...................................................................... nb/intel/sandybridge: Remove now-unnecessary sequence macros Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I7980daf316cfd524d24df2c10e43b9b15e4e30bf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_iosav.c 1 file changed, 596 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47504/1 diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 4e37444..11b2acb 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -51,52 +51,639 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) { - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(slotrank, gap, post, wrap); + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ZQCS, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = gap, + .post_ssq_wait = post, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = wrap, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) { - const struct iosav_ssq sequence[] = PREA_SEQUENCE(post, wrap); + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = post, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = wrap, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) { - const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(tMOD, loops, gap, loops2, post2); + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. In this mode only RD and RDA + * are allowed, and all reads return a predefined pattern. + */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }, + /* DRAM command RD */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops, + .cmd_delay_gap = gap, + .post_ssq_wait = 4, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops2, + .cmd_delay_gap = 4, + .post_ssq_wait = post2, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 3, + .rank = slotrank, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) { - const struct iosav_ssq sequence[] = - MISC_WRITE_SEQUENCE(gap0, loops0, gap1, loops2, wrap2); + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops0, + .cmd_delay_gap = gap0, + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = loops0 == 1 ? 0 : 1, + .addr_wrap = loops0 == 1 ? 0 : 18, + }, + }, + /* DRAM command NOP */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = gap1, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }, + /* DRAM command WR */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = loops2, + .cmd_delay_gap = 4, + .post_ssq_wait = 4, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = wrap2, + }, + }, + /* DRAM command NOP */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 31, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_command_training_sequence( ramctr_timing *ctrl, int channel, int slotrank, unsigned int address) { - const struct iosav_ssq sequence[] = COMMAND_TRAINING_SEQUENCE(address); + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = address, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + .lfsr_upd = 3, + .lfsr_xors = 2, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = 15, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank) { - const struct iosav_ssq sequence[] = WRITE_DATA_SEQUENCE; + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 0, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 32, + .cmd_delay_gap = 20, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) { - const struct iosav_ssq sequence[] = AGGRESSIVE_WRITE_READ_SEQUENCE; + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), + .post_ssq_wait = ctrl->tRCD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 480, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 4, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank) { - const struct iosav_ssq sequence[] = MEMORY_TEST_SEQUENCE; + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 4, + .cmd_delay_gap = 8, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command WR */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_WR, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 100, + .cmd_delay_gap = 4, + .post_ssq_wait = 40, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PRE */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = 40, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7980daf316cfd524d24df2c10e43b9b15e4e30bf Gerrit-Change-Number: 47504 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/common/acpi: move S0ix UUID to the condition
by Nico Huber (Code Review) 19 Nov '20

19 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: move S0ix UUID to the condition ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG@10 PS1, Line 10: PEPD How about you rename this first to give the commit message some meaning? -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 19 Nov 2020 22:53:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/intel/sandybridge: Create sequence helpers
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47503 ) Change subject: nb/intel/sandybridge: Create sequence helpers ...................................................................... nb/intel/sandybridge: Create sequence helpers Create some functions to program commonly-used sequences. Change-Id: I1b6474ab208fe5fc2bd7f1b68eff20541fdfce9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 92 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47503/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index dc7f32b..ec5d59a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -530,8 +530,7 @@ /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(slotrank, 3, 8, 0); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_zqcs_sequence(channel, slotrank, 3, 8, 0); /* * Execute command queue - why is bit 22 set here?! @@ -867,8 +866,7 @@ /* Drain */ wait_for_iosav(channel); - const struct iosav_ssq zqcs_sequence[] = ZQCS_SEQUENCE(slotrank, 4, 101, 31); - iosav_write_sequence(channel, zqcs_sequence, ARRAY_SIZE(zqcs_sequence)); + iosav_write_zqcs_sequence(channel, slotrank, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1028,9 +1026,7 @@ { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence(channel, slotrank, ctrl->tMOD, 1, 3, 15, ctrl->CAS + 36); /* Execute command queue */ iosav_run_once(channel); @@ -1291,8 +1287,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = PREA_SEQUENCE(ctrl->tRP, 0); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0); /* Execute command queue */ iosav_run_once(channel); @@ -1388,9 +1383,8 @@ wait_for_iosav(channel); - const struct iosav_ssq wr_sequence[] = - MISC_WRITE_SEQUENCE(MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); - iosav_write_sequence(channel, wr_sequence, ARRAY_SIZE(wr_sequence)); + iosav_write_misc_write_sequence(ctrl, channel, slotrank, + MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), 4, 4, 500, 18); /* Execute command queue */ iosav_run_once(channel); @@ -1524,8 +1518,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = PREA_SEQUENCE(ctrl->tRP, 18); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18); /* Execute command queue */ iosav_run_once(channel); @@ -1634,9 +1627,8 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -1654,9 +1646,8 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -1811,8 +1802,7 @@ wait_for_iosav(channel); - const struct iosav_ssq wr_sequence[] = MISC_WRITE_SEQUENCE(3, 1, 3, 3, 31); - iosav_write_sequence(channel, wr_sequence, ARRAY_SIZE(wr_sequence)); + iosav_write_misc_write_sequence(ctrl, channel, slotrank, 3, 1, 3, 3, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1914,8 +1904,7 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(slotrank, 4, 4, 31); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -1989,8 +1978,7 @@ MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(0, 4, 101, 31); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); /* Execute command queue */ iosav_run_once(channel); @@ -2056,8 +2044,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = COMMAND_TRAINING_SEQUENCE(ctr); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); /* Program LFSR for the RD/WR subsequences */ MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; @@ -2125,8 +2112,7 @@ /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(slotrank, 4, 4, 31); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -2143,8 +2129,7 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(slotrank, 4, 4, 31); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); /* Execute command queue */ iosav_run_once(channel); @@ -2305,9 +2290,8 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 500, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2364,9 +2348,8 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2386,9 +2369,8 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = - READ_MPR_SEQUENCE(ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_read_mpr_sequence( + channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); /* Execute command queue */ iosav_run_once(channel); @@ -2488,8 +2470,7 @@ } wait_for_iosav(channel); - const struct iosav_ssq sequence[] = WRITE_DATA_SEQUENCE; - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_data_write_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); @@ -2587,8 +2568,7 @@ { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = AGGRESSIVE_WRITE_READ_SEQUENCE; - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_aggressive_write_read_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); @@ -2764,8 +2744,7 @@ } wait_for_iosav(channel); - const struct iosav_ssq sequence[] = MEMORY_TEST_SEQUENCE; - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_memory_test_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 3937f41..67ae966 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -710,11 +710,25 @@ }, \ } +typedef struct ramctr_timing_st ramctr_timing; + void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); void iosav_run_once(const int ch); void wait_for_iosav(int channel); +void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); +void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); +void iosav_write_read_mpr_sequence( + int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); +void iosav_write_command_training_sequence( + ramctr_timing *ctrl, int channel, int slotrank, unsigned int address); +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank); +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank); + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index d56ab7a..d3a748d 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -48,3 +48,55 @@ return; } } + +void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap) +{ + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(gap, post, slotrank, wrap); + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap) +{ + const struct iosav_ssq sequence[] = PREA_SEQUENCE(post, wrap); + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_read_mpr_sequence( + int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2) +{ + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(tMOD, loops, gap, loops2, post2); + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, + u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) +{ + const struct iosav_ssq sequence[] = + MISC_WRITE_SEQUENCE(gap0, loops0, gap1, loops2, wrap2); + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_command_training_sequence( + ramctr_timing *ctrl, int channel, int slotrank, unsigned int address) +{ + const struct iosav_ssq sequence[] = COMMAND_TRAINING_SEQUENCE(address); + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = WRITE_DATA_SEQUENCE; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = AGGRESSIVE_WRITE_READ_SEQUENCE; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + +void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = MEMORY_TEST_SEQUENCE; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6474ab208fe5fc2bd7f1b68eff20541fdfce9b Gerrit-Change-Number: 47503 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: nb/intel/sandybridge: Extract some IOSAV sequences into macros
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47493 ) Change subject: nb/intel/sandybridge: Extract some IOSAV sequences into macros ...................................................................... nb/intel/sandybridge: Extract some IOSAV sequences into macros This allows deduplicating them while preserving reproducibility. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Ic7d1a5732296bb678b9954f80508e9f7de7ff319 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 518 insertions(+), 1,034 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47493/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7a77434..d58eef4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -530,26 +530,7 @@ /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - const struct iosav_ssq sequence[] = { - /* DRAM command ZQCS */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(3, 8, slotrank, 0); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* @@ -1069,93 +1050,7 @@ { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. In this mode only RD and RDA - * are allowed, and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 15, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 36, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(1, 3, 15, 36); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -1760,30 +1655,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command PREA */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - }; + const struct iosav_ssq sequence[] = PREA_SEQUENCE(18); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -1893,94 +1765,7 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(3, 4, 1, 8); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -1999,94 +1784,7 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(3, 4, 1, 8); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -2432,29 +2130,7 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = { - /* DRAM command ZQCS */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }, - }; + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(4, 4, slotrank, 31); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -2529,29 +2205,7 @@ MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command ZQCS */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 101, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = 0, - }, - .addr_update = { - .addr_wrap = 31, - }, - }, - }; + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(4, 101, 0, 31); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -2618,103 +2272,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command ACT */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 8, - .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = ctr, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command WR */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - .lfsr_upd = 3, - .lfsr_xors = 2, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - .lfsr_upd = 3, - .lfsr_xors = 2, - }, - }, - /* DRAM command PRE */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 15, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - }; + const struct iosav_ssq sequence[] = COMMAND_TRAINING_SEQUENCE(ctr); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Program LFSR for the RD/WR subsequences */ @@ -2783,29 +2341,7 @@ /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = { - /* DRAM command ZQCS */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }, - }; + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(4, 4, slotrank, 31); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -2823,29 +2359,7 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - const struct iosav_ssq sequence[] = { - /* DRAM command ZQCS */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ZQCS, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 31, - }, - }, - }; + const struct iosav_ssq sequence[] = ZQCS_SEQUENCE(4, 4, slotrank, 31); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3007,94 +2521,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 500, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(500, 4, 1, 8); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3152,94 +2579,7 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(3, 4, 1, 8); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3260,94 +2600,7 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 3, - .cmd_delay_gap = 4, - .post_ssq_wait = 4, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->CAS + 8, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 3, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_MPR_SEQUENCE(3, 4, 1, 8); iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3448,97 +2701,7 @@ } wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command ACT */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = MAX(ctrl->tRRD, - (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - /* DRAM command WR */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 20, - .post_ssq_wait = ctrl->tWTR + - ctrl->CWL + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 32, - .cmd_delay_gap = 20, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command PRE */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = WRITE_DATA_SEQUENCE; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3637,96 +2800,7 @@ { wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command ACT */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), - .post_ssq_wait = ctrl->tRCD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command WR */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 480, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 480, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command PRE */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 4, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - }, - }; + const struct iosav_ssq sequence[] = READ_WRITE_SEQUENCE_ALT_2; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ @@ -3903,99 +2977,7 @@ } wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command ACT */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 4, - .cmd_delay_gap = 8, - .post_ssq_wait = 40, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command WR */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_WR, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 100, - .cmd_delay_gap = 4, - .post_ssq_wait = 40, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 100, - .cmd_delay_gap = 4, - .post_ssq_wait = 40, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command PRE */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = 40, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - }; + const struct iosav_ssq sequence[] = MEMORY_TEST_SEQUENCE; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index a8644ae..9989bc2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,508 @@ } addr_update; }; +#define ZQCS_SEQUENCE(gap, post, slotrank, wrap) \ + { \ + /* DRAM command ZQCS */ \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_ZQCS, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = gap, \ + .post_ssq_wait = post, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .addr_wrap = wrap, \ + }, \ + }, \ + } + +#define PREA_SEQUENCE(wrap) \ + { \ + /* DRAM command PREA */ \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_PRE, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 3, \ + .post_ssq_wait = ctrl->tRP, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 1024, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .addr_wrap = wrap, \ + }, \ + }, \ + } + +#define READ_MPR_SEQUENCE(loops, gap, loops2, post) \ + { \ + /* \ + * DRAM command MRS \ + * \ + * Write MR3 MPR enable. In this mode only RD and RDA \ + * are allowed, and all reads return a predefined pattern. \ + */ \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_MRS, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 3, \ + .post_ssq_wait = ctrl->tMOD, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 4, \ + .rowbits = 6, \ + .bank = 3, \ + .rank = slotrank, \ + }, \ + }, \ + /* DRAM command RD */ \ + [1] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = loops, \ + .cmd_delay_gap = gap, \ + .post_ssq_wait = 4, \ + .data_direction = SSQ_RD, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + }, \ + /* DRAM command RD */ \ + [2] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = loops2, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = ctrl->CAS + post, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + }, \ + /* \ + * DRAM command MRS \ + * \ + * Write MR3 MPR disable. \ + */ \ + [3] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_MRS, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 3, \ + .post_ssq_wait = ctrl->tMOD, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 3, \ + .rank = slotrank, \ + }, \ + }, \ + } + +#define COMMAND_TRAINING_SEQUENCE(ctr) \ + { \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_ACT, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 8, \ + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), \ + .post_ssq_wait = ctrl->tRCD, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = ctr, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_bank = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [1] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_WR, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 32, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, \ + .data_direction = SSQ_WR, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + .lfsr_upd = 3, \ + .lfsr_xors = 2, \ + }, \ + }, \ + [2] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 32, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = MAX(ctrl->tRTP, 8), \ + .data_direction = SSQ_RD, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + .lfsr_upd = 3, \ + .lfsr_xors = 2, \ + }, \ + }, \ + [3] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_PRE, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = 15, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 1024, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .addr_wrap = 18, \ + }, \ + }, \ + } + +#define WRITE_DATA_SEQUENCE \ + { \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_ACT, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 4, \ + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), \ + .post_ssq_wait = ctrl->tRCD, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_bank = 0, \ + .addr_wrap = 18, \ + }, \ + }, \ + [1] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_WR, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 32, \ + .cmd_delay_gap = 20, \ + .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, \ + .data_direction = SSQ_WR, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [2] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 32, \ + .cmd_delay_gap = 20, \ + .post_ssq_wait = MAX(ctrl->tRTP, 8), \ + .data_direction = SSQ_RD, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [3] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_PRE, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 3, \ + .post_ssq_wait = ctrl->tRP, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 1024, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + }, \ + } + +#define READ_WRITE_SEQUENCE_ALT_2 \ + { \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_ACT, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 4, \ + .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), \ + .post_ssq_wait = ctrl->tRCD, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_bank = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [1] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_WR, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 480, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, \ + .data_direction = SSQ_WR, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [2] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 480, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = MAX(ctrl->tRTP, 8), \ + .data_direction = SSQ_RD, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [3] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_PRE, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = ctrl->tRP, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 1024, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + }, \ + } + +#define MEMORY_TEST_SEQUENCE \ + { \ + [0] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_ACT, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 4, \ + .cmd_delay_gap = 8, \ + .post_ssq_wait = 40, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_bank = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [1] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_WR, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 100, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = 40, \ + .data_direction = SSQ_WR, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [2] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_RD, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 100, \ + .cmd_delay_gap = 4, \ + .post_ssq_wait = 40, \ + .data_direction = SSQ_RD, \ + }, \ + .sp_cmd_addr = { \ + .address = 0, \ + .rowbits = 0, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .inc_addr_8 = 1, \ + .addr_wrap = 18, \ + }, \ + }, \ + [3] = { \ + .sp_cmd_ctrl = { \ + .command = IOSAV_PRE, \ + .ranksel_ap = 1, \ + }, \ + .subseq_ctrl = { \ + .cmd_executions = 1, \ + .cmd_delay_gap = 3, \ + .post_ssq_wait = 40, \ + .data_direction = SSQ_NA, \ + }, \ + .sp_cmd_addr = { \ + .address = 1024, \ + .rowbits = 6, \ + .bank = 0, \ + .rank = slotrank, \ + }, \ + .addr_update = { \ + .addr_wrap = 18, \ + }, \ + }, \ + } + void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); void iosav_run_once(const int ch); -- To view, visit https://review.coreboot.org/c/coreboot/+/47493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7d1a5732296bb678b9954f80508e9f7de7ff319 Gerrit-Change-Number: 47493 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: nb/intel/sandybridge: Use arrays to program IOSAV
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47492 ) Change subject: nb/intel/sandybridge: Use arrays to program IOSAV ...................................................................... nb/intel/sandybridge: Use arrays to program IOSAV Instead of programming subsequences one-by-one, we might as well take the whole sequence as an array and program all subsequences in one go. Since the number of subsequences is now known in advance, handling of global state can be simplified, which allows reusing the last sequence. Change-Id: Ica1b2b20e04ae368f10aa236ca24d12f69464430 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 382 insertions(+), 569 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47492/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 578b784..7a77434 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -530,9 +530,9 @@ /* Choose a populated rank */ slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -548,9 +548,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* * Execute command queue - why is bit 22 set here?! @@ -638,9 +638,9 @@ val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); } - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command MRS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, }, @@ -656,13 +656,9 @@ .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command MRS */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -679,13 +675,9 @@ .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command MRS */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command MRS */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, }, @@ -701,9 +693,9 @@ .bank = reg, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -828,9 +820,9 @@ } } - /* DRAM command NOP (without ODT nor chip selects) */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq zqcl_sequence[] = { + /* DRAM command NOP (without ODT nor chip selects) */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_NOP & ~(0xff << 8), }, @@ -846,13 +838,9 @@ .bank = 0, .rank = 0, }, - }; - iosav_write_ssq(BROADCAST_CH, &ssq); - } - - /* DRAM command ZQCL */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ZQCL */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, .ranksel_ap = 1, @@ -873,9 +861,9 @@ .inc_rank = 1, .addr_wrap = 20, }, - }; - iosav_write_ssq(BROADCAST_CH, &ssq); - } + }, + }; + iosav_write_sequence(BROADCAST_CH, zqcl_sequence, ARRAY_SIZE(zqcl_sequence)); /* Execute command queue on all channels. Do it four times. */ iosav_run_queue(BROADCAST_CH, 4, 0); @@ -898,9 +886,9 @@ /* Drain */ wait_for_iosav(channel); - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq zqcs_sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -919,9 +907,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, zqcs_sequence, ARRAY_SIZE(zqcs_sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1081,14 +1069,14 @@ { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. In this mode only RD and RDA + * are allowed, and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -1105,13 +1093,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -1128,13 +1112,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -1151,17 +1131,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -1178,9 +1154,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1441,9 +1417,9 @@ wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1460,9 +1436,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1558,9 +1534,9 @@ wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq wr_sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -1581,13 +1557,9 @@ .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -1607,13 +1579,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -1634,13 +1602,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -1660,18 +1624,18 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, wr_sequence, ARRAY_SIZE(wr_sequence)); /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq rd_sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1691,13 +1655,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ACT */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -1718,13 +1678,9 @@ .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -1745,13 +1701,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PREA */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1771,9 +1723,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1808,9 +1760,9 @@ wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -1830,9 +1782,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -1941,15 +1893,15 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -1966,13 +1918,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -1989,13 +1937,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -2012,17 +1956,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -2039,9 +1979,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2059,15 +1999,15 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -2084,13 +2024,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -2107,13 +2043,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -2130,17 +2062,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -2157,9 +2085,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2175,9 +2103,10 @@ write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); wait_for_iosav(channel); - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + + const struct iosav_ssq sequence[] = { + /* DRAM command NOP */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -2194,13 +2123,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_NOP_ALT, .ranksel_ap = 1, @@ -2217,9 +2142,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2317,9 +2242,9 @@ wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq wr_sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -2336,13 +2261,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -2362,13 +2283,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -2389,13 +2306,9 @@ .inc_addr_8 = 1, .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command NOP */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command NOP */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -2415,18 +2328,18 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, wr_sequence, ARRAY_SIZE(wr_sequence)); /* Execute command queue */ iosav_run_once(channel); wait_for_iosav(channel); - /* DRAM command PREA */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq rd_sequence[] = { + /* DRAM command PREA */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -2446,13 +2359,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command ACT */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -2469,13 +2378,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 3, @@ -2494,9 +2399,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2527,9 +2432,9 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -2548,9 +2453,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2624,9 +2529,9 @@ MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -2645,9 +2550,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2712,9 +2617,10 @@ MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -2735,13 +2641,9 @@ .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -2764,15 +2666,9 @@ .lfsr_upd = 3, .lfsr_xors = 2, }, - }; - iosav_write_ssq(channel, &ssq); - } - /* FIXME: Hardcoded subsequence index */ - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -2795,16 +2691,9 @@ .lfsr_upd = 3, .lfsr_xors = 2, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* FIXME: Hardcoded subsequence index */ - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PRE */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -2824,9 +2713,13 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + + /* Program LFSR for the RD/WR subsequences */ + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; + MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; /* Execute command queue */ iosav_run_once(channel); @@ -2890,9 +2783,9 @@ /* Choose an existing rank */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -2911,9 +2804,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -2930,9 +2823,9 @@ /* choose an existing rank. */ slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* DRAM command ZQCS */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ZQCS */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ZQCS, }, @@ -2951,9 +2844,9 @@ .addr_update = { .addr_wrap = 31, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -3114,15 +3007,15 @@ wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3139,13 +3032,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3162,13 +3051,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3185,17 +3070,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3212,9 +3093,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -3271,15 +3152,15 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3296,13 +3177,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3319,13 +3196,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3342,17 +3215,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3369,9 +3238,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -3391,15 +3260,15 @@ FOR_ALL_POPULATED_RANKS { wait_for_iosav(channel); - /* - * DRAM command MRS - * - * Write MR3 MPR enable. - * In this mode only RD and RDA are allowed, - * and all reads return a predefined pattern. - */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* + * DRAM command MRS + * + * Write MR3 MPR enable. + * In this mode only RD and RDA are allowed, + * and all reads return a predefined pattern. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3416,13 +3285,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3439,13 +3304,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3462,17 +3323,13 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command MRS - * - * Write MR3 MPR disable. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command MRS + * + * Write MR3 MPR disable. + */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_MRS, .ranksel_ap = 1, @@ -3489,9 +3346,9 @@ .bank = 3, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -3591,9 +3448,9 @@ } wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -3614,13 +3471,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -3642,13 +3495,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3669,13 +3518,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PRE */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -3692,9 +3537,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -3792,9 +3637,9 @@ { wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -3815,13 +3660,9 @@ .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -3842,13 +3683,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -3869,13 +3706,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PRE */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -3892,9 +3725,9 @@ .bank = 0, .rank = slotrank, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -4070,9 +3903,9 @@ } wait_for_iosav(channel); - /* DRAM command ACT */ - { - const struct iosav_ssq ssq = { + const struct iosav_ssq sequence[] = { + /* DRAM command ACT */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -4093,13 +3926,9 @@ .inc_bank = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command WR */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command WR */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -4120,13 +3949,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command RD */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command RD */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, .ranksel_ap = 1, @@ -4147,13 +3972,9 @@ .inc_addr_8 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* DRAM command PRE */ - { - const struct iosav_ssq ssq = { + }, + /* DRAM command PRE */ + [3] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -4173,9 +3994,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_once(channel); @@ -4216,13 +4037,13 @@ for (bank = 0; bank < 8; bank++) { for (row = 0; row < rowsize; row += 16) { - /* - * DRAM command ACT - * Opens the row for writing. - */ - { - u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); - const struct iosav_ssq ssq = { + u8 gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD); + const struct iosav_ssq sequence[] = { + /* + * DRAM command ACT + * Opens the row for writing. + */ + [0] = { .sp_cmd_ctrl = { .command = IOSAV_ACT, .ranksel_ap = 1, @@ -4243,17 +4064,13 @@ .inc_addr_1 = 1, .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command WR - * Writes (128 + 1) * 8 (burst length) * 8 (bus width) - * bytes. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command WR + * Writes (128 + 1) * 8 (burst length) * 8 (bus width) + * bytes. + */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_WR, .ranksel_ap = 1, @@ -4275,16 +4092,12 @@ .inc_addr_8 = 1, .addr_wrap = 9, }, - }; - iosav_write_ssq(channel, &ssq); - } - - /* - * DRAM command PRE - * Closes the row. - */ - { - const struct iosav_ssq ssq = { + }, + /* + * DRAM command PRE + * Closes the row. + */ + [2] = { .sp_cmd_ctrl = { .command = IOSAV_PRE, .ranksel_ap = 1, @@ -4304,9 +4117,9 @@ .addr_update = { .addr_wrap = 18, }, - }; - iosav_write_ssq(channel, &ssq); - } + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); /* Execute command queue */ iosav_run_queue(channel, 16, 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 73c28bc..a8644ae 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,7 +98,7 @@ } addr_update; }; -void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq); +void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); void iosav_run_once(const int ch); void wait_for_iosav(int channel); diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 9ab415a..9437ace 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -15,21 +15,21 @@ /* Number of programmed IOSAV subsequences. */ static unsigned int ssq_count = 0; -void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) +void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length) { - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; + for (unsigned int i = 0; i < length; i++) { + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = seq[i].sp_cmd_ctrl.raw; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = seq[i].subseq_ctrl.raw; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = seq[i].sp_cmd_addr.raw; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = seq[i].addr_update.raw; + } - ssq_count++; + ssq_count = length; } void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) { MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); - - ssq_count = 0; } void iosav_run_once(const int ch) -- To view, visit https://review.coreboot.org/c/coreboot/+/47492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica1b2b20e04ae368f10aa236ca24d12f69464430 Gerrit-Change-Number: 47492 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: nb/intel/sandybridge: Move IOSAV functions to separate file
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47491 ) Change subject: nb/intel/sandybridge: Move IOSAV functions to separate file ...................................................................... nb/intel/sandybridge: Move IOSAV functions to separate file Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h A src/northbridge/intel/sandybridge/raminit_iosav.c 4 files changed, 52 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47491/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a5b2e5e..6380681 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c +romstage-y += raminit_iosav.c romstage-y += raminit_native.c romstage-y += raminit_tables.c romstage-y += ../../../device/dram/ddr3.c diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 8a4b25b..578b784 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,31 +18,6 @@ /* FIXME: no support for 3-channel chipsets */ -/* Number of programmed IOSAV subsequences. */ -static unsigned int ssq_count = 0; - -static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) -{ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; - - ssq_count++; -} - -static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) -{ - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); - - ssq_count = 0; -} - -static void iosav_run_once(const int ch) -{ - iosav_run_queue(ch, 1, 0); -} - static void sfence(void) { asm volatile ("sfence"); @@ -543,14 +518,6 @@ } } -static void wait_for_iosav(int channel) -{ - while (1) { - if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) - return; - } -} - static void write_reset(ramctr_timing *ctrl) { int channel, slotrank; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index a6f4e0b..73c28bc 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,11 @@ } addr_update; }; +void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq); +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); +void iosav_run_once(const int ch); +void wait_for_iosav(int channel); + /* FIXME: Vendor BIOS uses 64 but our algorithms are less performant and even 1 seems to be enough in practice. */ #define NUM_PATTERNS 4 diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c new file mode 100644 index 0000000..9ab415a --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <types.h> + +#include "raminit_native.h" +#include "raminit_common.h" +#include "raminit_tables.h" +#include "sandybridge.h" + +/* FIXME: no support for 3-channel chipsets */ + +/* Number of programmed IOSAV subsequences. */ +static unsigned int ssq_count = 0; + +void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) +{ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; + + ssq_count++; +} + +void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) +{ + MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); + + ssq_count = 0; +} + +void iosav_run_once(const int ch) +{ + iosav_run_queue(ch, 1, 0); +} + +void wait_for_iosav(int channel) +{ + while (1) { + if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) + return; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab Gerrit-Change-Number: 47491 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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