coreboot-gerrit November 2020

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Change in em100[master]: Handle errors of libusb_bulk_transfer()
by Stefan Reinauer (Code Review) 19 Nov '20

19 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47731 ) Change subject: Handle errors of libusb_bulk_transfer() ...................................................................... Handle errors of libusb_bulk_transfer() Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Iad1308e3bc2656506b0f485aecff8328034dc319 --- M usb.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/31/47731/1 diff --git a/usb.c b/usb.c index c7d52d8..4fd3df5 100644 --- a/usb.c +++ b/usb.c @@ -20,16 +20,20 @@ { int actual; int length = 16; /* haven't seen any other length yet */ - libusb_bulk_transfer(dev, 1 | LIBUSB_ENDPOINT_OUT, + int ret = libusb_bulk_transfer(dev, 1 | LIBUSB_ENDPOINT_OUT, data, length, &actual, BULK_SEND_TIMEOUT); + if (LIBUSB_SUCCESS != ret) + printf("ERROR: USB: %s: %s\n", __func__, libusb_strerror(ret)); return (actual == length); } int get_response(libusb_device_handle *dev, void *data, int length) { int actual; - libusb_bulk_transfer(dev, 2 | LIBUSB_ENDPOINT_IN, + int ret = libusb_bulk_transfer(dev, 2 | LIBUSB_ENDPOINT_IN, data, length, &actual, BULK_SEND_TIMEOUT); + if (LIBUSB_SUCCESS != ret) + printf("ERROR: USB: %s: %s\n", __func__, libusb_strerror(ret)); return actual; } -- To view, visit https://review.coreboot.org/c/em100/+/47731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Iad1308e3bc2656506b0f485aecff8328034dc319 Gerrit-Change-Number: 47731 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Make em100 a (struct em100 *)
by Stefan Reinauer (Code Review) 19 Nov '20

19 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47730 ) Change subject: Make em100 a (struct em100 *) ...................................................................... Make em100 a (struct em100 *) Make em100 a pointer to struct em100 in main, to make the code more consistent with all other functions. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I51ccfd3047140e40814de4df2adb8446e6408f20 --- M em100.c 1 file changed, 49 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/30/47730/1 diff --git a/em100.c b/em100.c index e0b145a..09cc490 100644 --- a/em100.c +++ b/em100.c @@ -30,6 +30,7 @@ int debug = 0; static volatile int do_exit_flag = 0; +static struct em100 em100_state; static void exit_handler(int sig __unused) { @@ -841,6 +842,7 @@ unsigned int spi_start_address = 0; const char *voltage = NULL; struct sigaction signal_action; + struct em100 *em100 = &em100_state; while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", longopts, &idx)) != -1) { @@ -928,8 +930,7 @@ } } - struct em100 em100; - if (!em100_attach(&em100, bus, device, serial_number)) { + if (!em100_attach(em100, bus, device, serial_number)) { return 1; } @@ -950,8 +951,8 @@ sigemptyset(&signal_action.sa_mask); sigaction(SIGINT, &signal_action, NULL); - if (em100.hwversion == HWVERSION_EM100PRO || em100.hwversion == HWVERSION_EM100PRO_EARLY) { - printf("MCU version: %d.%02d\n", em100.mcu >> 8, em100.mcu & 0xff); + if (em100->hwversion == HWVERSION_EM100PRO || em100->hwversion == HWVERSION_EM100PRO_EARLY) { + printf("MCU version: %d.%02d\n", em100->mcu >> 8, em100->mcu & 0xff); /* While the Dediprog software for Windows will refuse to work * with 1.8V chips on older FPGA versions, it does not * specifically output a voltage when reporting the FPGA @@ -959,43 +960,43 @@ * known to behave the old way, 0.75 is behaving the new * way. */ - if (em100.fpga > 0x0033) /* 0.51 */ + if (em100->fpga > 0x0033) /* 0.51 */ printf("FPGA version: %d.%02d (%s)\n", - em100.fpga >> 8 & 0x7f, em100.fpga & 0xff, - em100.fpga & 0x8000 ? "1.8V" : "3.3V"); + em100->fpga >> 8 & 0x7f, em100->fpga & 0xff, + em100->fpga & 0x8000 ? "1.8V" : "3.3V"); else - printf("FPGA version: %d.%02d\n", em100.fpga >> 8, - em100.fpga & 0xff); + printf("FPGA version: %d.%02d\n", em100->fpga >> 8, + em100->fpga & 0xff); } else {/* EM100Pro-G2 */ - printf("MCU version: %d.%d\n", em100.mcu >> 8, em100.mcu & 0xff); + printf("MCU version: %d.%d\n", em100->mcu >> 8, em100->mcu & 0xff); printf("FPGA version: %d.%03d\n", - em100.fpga >> 8 & 0x7f, em100.fpga & 0xff); + em100->fpga >> 8 & 0x7f, em100->fpga & 0xff); } - printf("Hardware version: %u\n", em100.hwversion); + printf("Hardware version: %u\n", em100->hwversion); - if (em100.serialno != 0xffffffff) + if (em100->serialno != 0xffffffff) printf("Serial number: %s%06d\n", - em100.hwversion == HWVERSION_EM100PRO_EARLY ? "DP" : "EM", em100.serialno); + em100->hwversion == HWVERSION_EM100PRO_EARLY ? "DP" : "EM", em100->serialno); else printf("Serial number: N.A.\n"); printf("SPI flash database: %s\n", database_version); - get_current_state(&em100); - get_current_pin_state(&em100); + get_current_state(em100); + get_current_pin_state(em100); printf("\n"); if (debug) { - em100_debug(&em100); + em100_debug(em100); } if (firmware_in) { - firmware_update(&em100, firmware_in, verify); - return em100_detach(&em100); + firmware_update(em100, firmware_in, verify); + return em100_detach(em100); } if (firmware_out) { - firmware_dump(&em100, firmware_out, firmware_is_dpfw); - return em100_detach(&em100); + firmware_dump(em100, firmware_out, firmware_is_dpfw); + return em100_detach(em100); } if (serialno) { @@ -1013,17 +1014,17 @@ printf("Error: Can't parse serial number '%s'\n", serialno); else - set_serialno(&em100, serial_number); + set_serialno(em100, serial_number); - return em100_detach(&em100); + return em100_detach(em100); } if (do_stop) { - set_state(&em100, 0); + set_state(em100, 0); } if (desiredchip) { - if (!set_chip_type(&em100, chip)) { + if (!set_chip_type(em100, chip)) { printf("Failed configuring chip type.\n"); return 0; } @@ -1033,25 +1034,25 @@ * unless specified by the user on the command line. */ if (!address_mode && chip->size > (16 * 1024 * 1024)) { - set_address_mode(&em100, 4); + set_address_mode(em100, 4); } } if (address_mode) { - if (set_address_mode(&em100, address_mode) < 0) { + if (set_address_mode(em100, address_mode) < 0) { return 1; } } if (voltage) { - if (!set_fpga_voltage_from_str(&em100, voltage)) { + if (!set_fpga_voltage_from_str(em100, voltage)) { printf("Failed configuring FPGA voltage.\n"); return 1; } } if (holdpin) { - if (!set_hold_pin_state_from_str(&em100, holdpin)) { + if (!set_hold_pin_state_from_str(em100, holdpin)) { printf("Failed configuring hold pin state.\n"); return 0; } @@ -1064,7 +1065,7 @@ /* Read configured SPI emulation from EM100 */ chipdesc emulated_chip; - if (!get_chip_type(&em100, &emulated_chip)) { + if (!get_chip_type(em100, &emulated_chip)) { printf("Configured to emulate %dkB chip\n", emulated_chip.size / 1024); maxlen = emulated_chip.size; } @@ -1084,7 +1085,7 @@ return 1; } - read_sdram(&em100, data, 0x00000000, maxlen); + read_sdram(em100, data, 0x00000000, maxlen); int length = fwrite(data, maxlen, 1, fdata); fclose(fdata); @@ -1141,7 +1142,7 @@ } if (compatibility) - autocorrect_image(&em100, data, length); + autocorrect_image(em100, data, length); if (spi_start_address) { readback = malloc(maxlen); @@ -1150,16 +1151,16 @@ free(data); return 1; } - done = read_sdram(&em100, readback, 0, maxlen); + done = read_sdram(em100, readback, 0, maxlen); if (done) { memcpy((unsigned char*)readback + spi_start_address, data, length); - write_sdram(&em100, (unsigned char*)readback, 0x00000000, maxlen); + write_sdram(em100, (unsigned char*)readback, 0x00000000, maxlen); } else { printf("Error: sdram readback failed\n"); } free(readback); } else { - write_sdram(&em100, (unsigned char*)data, 0x00000000, length); + write_sdram(em100, (unsigned char*)data, 0x00000000, length); } if (verify) { @@ -1169,14 +1170,14 @@ free(data); return 1; } - done = read_sdram(&em100, readback, spi_start_address, length); + done = read_sdram(em100, readback, spi_start_address, length); if (done && (memcmp(data, readback, length) == 0)) printf("Verify: PASS\n"); else { printf("Verify: FAIL\n"); free(readback); free(data); - em100_detach(&em100); + em100_detach(em100); return 1; } free(readback); @@ -1186,27 +1187,27 @@ } if (do_start) { - set_state(&em100, 1); + set_state(em100, 1); } if (trace || terminal) { - if ((holdpin == NULL) && (!set_hold_pin_state(&em100, 3))) { + if ((holdpin == NULL) && (!set_hold_pin_state(em100, 3))) { printf("Error: Failed to set EM100 to input\n"); return 1; } if (!do_start && !do_stop) - set_state(&em100, 1); + set_state(em100, 1); printf ("Starting "); if (trace) { - reset_spi_trace(&em100); + reset_spi_trace(em100); printf("trace%s", terminal ? " & " : ""); } if (terminal) { - init_spi_terminal(&em100); + init_spi_terminal(em100); printf("terminal"); } @@ -1214,22 +1215,22 @@ while (!do_exit_flag) { if (trace) - read_spi_trace(&em100, terminal, + read_spi_trace(em100, terminal, address_offset); else - read_spi_terminal(&em100, 0); + read_spi_terminal(em100, 0); } if (!do_start && !do_stop) - set_state(&em100, 0); + set_state(em100, 0); if (trace) - reset_spi_trace(&em100); + reset_spi_trace(em100); - if ((holdpin == NULL) && (!set_hold_pin_state(&em100, 2))) { + if ((holdpin == NULL) && (!set_hold_pin_state(em100, 2))) { printf("Error: Failed to set EM100 to float\n"); return 1; } } - return em100_detach(&em100); + return em100_detach(em100); } -- To view, visit https://review.coreboot.org/c/em100/+/47730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I51ccfd3047140e40814de4df2adb8446e6408f20 Gerrit-Change-Number: 47730 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Make do_exit_flag static
by Stefan Reinauer (Code Review) 19 Nov '20

19 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47729 ) Change subject: Make do_exit_flag static ...................................................................... Make do_exit_flag static It does not be globally visible Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I81d06f8803cd9c5ca6877a1e3d19287a681f5612 --- M em100.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/29/47729/1 diff --git a/em100.c b/em100.c index 580290a..e0b145a 100644 --- a/em100.c +++ b/em100.c @@ -29,7 +29,7 @@ char *database_version; int debug = 0; -volatile int do_exit_flag = 0; +static volatile int do_exit_flag = 0; static void exit_handler(int sig __unused) { -- To view, visit https://review.coreboot.org/c/em100/+/47729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I81d06f8803cd9c5ca6877a1e3d19287a681f5612 Gerrit-Change-Number: 47729 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in em100[master]: Update VERSION file last
by Stefan Reinauer (Code Review) 19 Nov '20

19 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47728 ) Change subject: Update VERSION file last ...................................................................... Update VERSION file last This way, if the update goes wrong, another invocation of em100 -U will fix the situation. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I947b6d287cb3fc7fd15dd3001656a8883a7e9d2d --- M curl.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/28/47728/1 diff --git a/curl.c b/curl.c index e6ee8bb..5fad845 100644 --- a/curl.c +++ b/curl.c @@ -183,9 +183,9 @@ printf("Downloading latest version: %s\n", new_version); else printf("Update available: %s (installed: %s)\n", new_version, old_version); - download(version_name, version_id); download(configs_name, configs_id); download(firmware_name, firmware_id); + download(version_name, version_id); return 0; } -- To view, visit https://review.coreboot.org/c/em100/+/47728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I947b6d287cb3fc7fd15dd3001656a8883a7e9d2d Gerrit-Change-Number: 47728 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/terrador: Correct enable_gpio to GPP_F16
by David Wu (Code Review) 19 Nov '20

19 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47742 ) Change subject: mb/google/volteer/var/terrador: Correct enable_gpio to GPP_F16 ...................................................................... mb/google/volteer/var/terrador: Correct enable_gpio to GPP_F16 The GPP_F16 is for enable_gpio after check the schematic. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821 --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47742/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index c3b5df7..caedfda 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -120,9 +120,8 @@ register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/47742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821 Gerrit-Change-Number: 47742 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Update release notes for Denverton NS deprecation
by Michael Niewöhner (Code Review) 19 Nov '20

19 Nov '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47539 ) Change subject: Documentation: Update release notes for Denverton NS deprecation ...................................................................... Abandoned see CB:47753 -- To view, visit https://review.coreboot.org/c/coreboot/+/47539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a6df3f3e640d1316e9cc2dbe244ea63c3a24dfa Gerrit-Change-Number: 47539 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: Дмитрий Понаморев <dponamorev(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/dedede: Enable microcode update
by Sugnan Prabhu S (Code Review) 19 Nov '20

19 Nov '20

Hello build bot (Jenkins), Krishna P Bhat D, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47162 to look at the new patch set (#5). Change subject: mb/google/dedede: Enable microcode update ...................................................................... mb/google/dedede: Enable microcode update Adds flashmap descriptor with RW_UCODE_STAGED to enable microcode update with the top swap. Change-Id: I956bc82bdb68049058335ff86c22742a235256c2 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/mainboard/google/dedede/Kconfig A src/mainboard/google/dedede/chromeos-ucode.fmd 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47162/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I956bc82bdb68049058335ff86c22742a235256c2 Gerrit-Change-Number: 47162 Gerrit-PatchSet: 5 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02
by Ronak Kanabar (Code Review) 19 Nov '20

19 Nov '20

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47500 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02 The headers added are generated as per FSP v2385_02. Previous FSP version was 2376. Changes Include: - add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h TEST=Build and boot JSLRVP Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h 1 file changed, 55 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47500/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h index fc167c5..55f8418 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h @@ -308,9 +308,26 @@ **/ UINT8 VtdDisable; -/** Offset 0x00E1 - Reserved +/** Offset 0x00E1 - Vtd Programming for Igd + 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar + programming disabled) + $EN_DIS **/ - UINT8 Reserved3[3]; + UINT8 VtdIgdEnable; + +/** Offset 0x00E2 - Vtd Programming for Ipu + 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIpuEnable; + +/** Offset 0x00E3 - Vtd Programming for Iop + 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar + programming disabled) + $EN_DIS +**/ + UINT8 VtdIopEnable; /** Offset 0x00E4 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. @@ -406,7 +423,7 @@ /** Offset 0x00F5 - Reserved **/ - UINT8 Reserved4[3]; + UINT8 Reserved3[3]; /** Offset 0x00F8 - MMA Test Content Pointer Pointer to MMA Test Content in Memory @@ -614,7 +631,7 @@ /** Offset 0x012B - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved4; /** Offset 0x012C - HECI1 BAR address BAR address of HECI1 @@ -671,7 +688,7 @@ /** Offset 0x0141 - Reserved **/ - UINT8 Reserved6[3]; + UINT8 Reserved5[3]; /** Offset 0x0144 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 @@ -694,7 +711,7 @@ /** Offset 0x014E - Reserved **/ - UINT8 Reserved7[24]; + UINT8 Reserved6[24]; /** Offset 0x0166 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): @@ -772,7 +789,7 @@ /** Offset 0x017C - Reserved **/ - UINT8 Reserved8[10]; + UINT8 Reserved7[10]; /** Offset 0x0186 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support @@ -782,7 +799,7 @@ /** Offset 0x0187 - Reserved **/ - UINT8 Reserved9; + UINT8 Reserved8; /** Offset 0x0188 - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI @@ -792,7 +809,7 @@ /** Offset 0x0189 - Reserved **/ - UINT8 Reserved10[2]; + UINT8 Reserved9[2]; /** Offset 0x018B - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable @@ -832,7 +849,7 @@ /** Offset 0x0191 - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved10; /** Offset 0x0192 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable @@ -872,7 +889,7 @@ /** Offset 0x0198 - Reserved **/ - UINT8 Reserved12[130]; + UINT8 Reserved11[130]; /** Offset 0x021A - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 @@ -1045,7 +1062,7 @@ /** Offset 0x024D - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved12; /** Offset 0x024E - core voltage override The core voltage override which is applied to the entire range of cpu core frequencies. @@ -1113,7 +1130,7 @@ /** Offset 0x025F - Reserved **/ - UINT8 Reserved14[9]; + UINT8 Reserved13[9]; /** Offset 0x0268 - CPU Run Control Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: @@ -1146,7 +1163,7 @@ /** Offset 0x026D - Reserved **/ - UINT8 Reserved15[3]; + UINT8 Reserved14[3]; /** Offset 0x0270 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1210,7 +1227,7 @@ /** Offset 0x02A9 - Reserved **/ - UINT8 Reserved16[6]; + UINT8 Reserved15[6]; /** Offset 0x02AF - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1392,7 +1409,7 @@ /** Offset 0x0492 - Reserved **/ - UINT8 Reserved17[2]; + UINT8 Reserved16[2]; /** Offset 0x0494 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1418,7 +1435,7 @@ /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved18[5]; + UINT8 Reserved17[5]; /** Offset 0x04BC - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1447,7 +1464,7 @@ /** Offset 0x04C3 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved18; /** Offset 0x04C4 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1475,7 +1492,7 @@ /** Offset 0x04CB - Reserved **/ - UINT8 Reserved20[5]; + UINT8 Reserved19[5]; /** Offset 0x04D0 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -1686,7 +1703,7 @@ /** Offset 0x04F3 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved20; /** Offset 0x04F4 - Margin Limit L2 % of L1 check for margin limit check @@ -1920,7 +1937,7 @@ /** Offset 0x051B - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; /** Offset 0x051C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -1943,7 +1960,7 @@ /** Offset 0x051F - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved22; /** Offset 0x0520 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -1953,7 +1970,7 @@ /** Offset 0x0522 - Reserved **/ - UINT8 Reserved24[2]; + UINT8 Reserved23[2]; /** Offset 0x0524 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) @@ -1980,7 +1997,7 @@ /** Offset 0x052B - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved24; /** Offset 0x052C - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on @@ -2371,7 +2388,7 @@ /** Offset 0x0576 - Reserved **/ - UINT8 Reserved26; + UINT8 Reserved25; /** Offset 0x0577 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, @@ -2438,7 +2455,7 @@ /** Offset 0x0581 - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved26; /** Offset 0x0582 - Post Code Output Port This option configures Post Code Output Port @@ -2458,7 +2475,7 @@ /** Offset 0x0586 - Reserved **/ - UINT8 Reserved28[18]; + UINT8 Reserved27[18]; /** Offset 0x0598 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it @@ -2485,7 +2502,7 @@ /** Offset 0x059D - Reserved **/ - UINT8 Reserved29[2]; + UINT8 Reserved28[2]; /** Offset 0x059F - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -2498,7 +2515,7 @@ /** Offset 0x05A0 - Reserved **/ - UINT8 Reserved30[18]; + UINT8 Reserved29[18]; /** Offset 0x05B2 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2515,7 +2532,7 @@ /** Offset 0x05B4 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x05B5 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -2526,7 +2543,7 @@ /** Offset 0x05B6 - Reserved **/ - UINT8 Reserved32[100]; + UINT8 Reserved31[100]; /** Offset 0x061A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2549,7 +2566,7 @@ /** Offset 0x061F - Reserved **/ - UINT8 Reserved33[11]; + UINT8 Reserved32[11]; /** Offset 0x062A - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2591,7 +2608,7 @@ /** Offset 0x0630 - Reserved **/ - UINT8 Reserved34[3]; + UINT8 Reserved33[3]; /** Offset 0x0633 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -2600,7 +2617,7 @@ /** Offset 0x0635 - Reserved **/ - UINT8 Reserved35[19]; + UINT8 Reserved34[19]; /** Offset 0x0648 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. @@ -2610,7 +2627,7 @@ /** Offset 0x0649 - Reserved **/ - UINT8 Reserved36[11]; + UINT8 Reserved35[11]; /** Offset 0x0654 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 @@ -2692,7 +2709,7 @@ /** Offset 0x0669 - Reserved **/ - UINT8 Reserved37[19]; + UINT8 Reserved36[19]; /** Offset 0x067C - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -2708,7 +2725,7 @@ /** Offset 0x067E - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved37; /** Offset 0x067F - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings @@ -2718,7 +2735,7 @@ /** Offset 0x0680 - Reserved **/ - UINT8 Reserved39[16]; + UINT8 Reserved38[16]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/47500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb Gerrit-Change-Number: 47500 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Angel Pons (Code Review) 19 Nov '20

19 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 56: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/romstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 13: DualRankSupportEnable > This is needed if the memory exceeds 16GB per channel. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 56 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Nov 2020 17:50:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 19 Nov '20

19 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 56: (5 comments) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/romstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 10: Profile > Is there an enum for this? Outside the scope of this patch This will be done in the next patches https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 13: DualRankSupportEnable > Why disable support for dual rank? This is needed if the memory exceeds 16GB per channel. In the case of mal10, the memory capacity is limited to 8GB. https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 19: RmtCheckRun > Why skip margin check? Enable TEST=successful boot https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 25: MrcFastBoot > Why no fast boot? Enable TEST=successful boot https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/variants/mal10/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 96: 1 > Problems with HS400? Only on our RTOS, there are no problems with Ubuntu. Let's set this to HS400 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 56 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 19 Nov 2020 17:25:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2020