coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common: Use per-soc definition for BAR sizes
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47378 ) Change subject: soc/intel/common: Use per-soc definition for BAR sizes ...................................................................... soc/intel/common: Use per-soc definition for BAR sizes The various platform BARs are not always the same size across different SOCs, so use the defined size rather than a hardcoded value. This results in the following change on TGL which increased the MCHBAR size to 128K: -system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved +system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved And fixes the following error output from the kernel: resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff], which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff] Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47378/1 diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index bac0590..b4b7465 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -253,17 +253,17 @@ /* MCH BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.48h */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + Memory32Fixed (ReadWrite, 0, MCH_BASE_SIZE, MCHB) /* DMI BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.68h */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB) /* EP BAR _BAS will be updated in _CRS below according to * B0:D0:F0:Reg.40h */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB) /* PCI Express BAR _BAS and _LEN will be updated in * _CRS below according to B0:D0:F0:Reg.60h -- To view, visit https://review.coreboot.org/c/coreboot/+/47378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64 Gerrit-Change-Number: 47378 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cse: Clear post code before reset
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47257 ) Change subject: soc/intel/common/block/cse: Clear post code before reset ...................................................................... soc/intel/common/block/cse: Clear post code before reset To avoid "unknown post code 0x55" entries in the event log on cold boot clear the post code before doing the CSE initiated reset. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47257/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ef6db3d..d10492b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -555,6 +555,9 @@ { uint32_t csr; + /* Clear post code to prevent eventlog entry from unknown code. */ + post_code(0); + /* Send reset request */ csr = read_host_csr(); csr |= (CSR_RESET | CSR_IG); -- To view, visit https://review.coreboot.org/c/coreboot/+/47257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186 Gerrit-Change-Number: 47257 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47198 ) Change subject: mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default ...................................................................... mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default Set the default state of the TCSS PCIe RP0 to hidden so that coreboot does not allocate resources to this hotplug root port. The default behavior on the reference design is that there is only one USB4 port attached to port C1 while port C0 is only a USB3 port. Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and C1 ports, so these boards change the default to 'on' so that coreboot does allocate resources for the hotplug port. BUG=b:159143739 BRANCH=volteer TEST=build volteer and voxel and check the resulting static.c to ensure the device is hidden or not. Also boot with the two different configurations and ensure resources are assigned or not. Finally check that S0ix still functions with the C0 port set to 'hidden' after authorizing a PCIe tunnel on port C1. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47198/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 6a8553c..f443421 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -414,7 +414,10 @@ device generic 0 on end end end # DPTF 0x9A03 - device ref tbt_pcie_rp0 on + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index e0dac7a..7fd1c86 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -188,6 +188,11 @@ device generic 0 on end end end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 7c95c50..064f3f3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -202,6 +202,11 @@ device generic 0 on end end end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. -- To view, visit https://review.coreboot.org/c/coreboot/+/47198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d Gerrit-Change-Number: 47198 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sconfig: Apply 'hidden' state from override tree
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47197 ) Change subject: sconfig: Apply 'hidden' state from override tree ...................................................................... sconfig: Apply 'hidden' state from override tree In order to allow override trees to hide/unhide a device copy the hidden state to the base device. This allows a sequence of states like: chipset.cb: mark device 'off' by default devicetree.cb: mark device 'hidden' (to skip resource allocation) overridetree.cb: mark device 'on' for device present on a variant BUG=b:159143739 BRANCH=volteer TEST=build volteer variants with TCSS RP0 either hidden or on and check the resulting static.c to see if the hidden bit is set appropriately. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Iebe5f6d2fd93fbcc4329875565c2ebf4823da59b --- M util/sconfig/main.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47197/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index a7b2ce6..13befa3 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1559,6 +1559,12 @@ base_dev->enabled = override_dev->enabled; /* + * Copy the hidden state of override device to base device. This allows + * override tree to hide or unhide a particular device. + */ + base_dev->hidden = override_dev->hidden; + + /* * Copy subsystem vendor and device ids from override device to base * device only if the ids are non-zero in override device. Else, honor * the values in base device. -- To view, visit https://review.coreboot.org/c/coreboot/+/47197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe5f6d2fd93fbcc4329875565c2ebf4823da59b Gerrit-Change-Number: 47197 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47255 ) Change subject: mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device ...................................................................... mb/google/volteer: Set up SATAXPCIE1 IOSSTATE based on detected device There is an issue with the storage device being mis-detected on exit from S0ix which is causing the root device to disappear if the power is actually turned off via RTD3. To work around this read the RX state of the pin and apply the IOSSTATE setting to drive a 0 or 1 back to the internal controller. This will ensure the device is detected the same on resume as on initial boot. BUG=b:171993054 TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2 slot and ensure this pin is configured appropriately. Additionally test with PCIe RTD3 enabled to ensure suspend/resume works reliably. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47255/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index acba972..ea4374d 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -7,6 +7,8 @@ #include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> #include <fw_config.h> +#include <gpio.h> +#include <intelblocks/gpio.h> #include <security/tpm/tss.h> #include <soc/gpio.h> #include <soc/pci_devs.h> @@ -126,6 +128,25 @@ override_pads = variant_override_gpio_table(&override_num); gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); + + /* + * Check SATAXPCIE1 (GPP_A12) RX status to determine if SSD is NVMe or SATA and set + * the IOSSTATE RX field to drive 0 or 1 back to the internal controller to ensure + * the attached device is not mis-detected on resume from S0ix. + */ + if (gpio_get(GPP_A12)) { + const struct pad_config gpio_pedet_nvme[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx1), + }; + gpio_configure_pads(gpio_pedet_nvme, ARRAY_SIZE(gpio_pedet_nvme)); + printk(BIOS_INFO, "SATAXPCIE1 indicates PCIe NVMe is present\n"); + } else { + const struct pad_config gpio_pedet_sata[] = { + PAD_CFG_NF_IOSSTATE(GPP_A12, NONE, DEEP, NF1, HIZCRx0), + }; + gpio_configure_pads(gpio_pedet_sata, ARRAY_SIZE(gpio_pedet_sata)); + printk(BIOS_INFO, "SATAXPCIE1 indicates SATA SSD is present\n"); + } } void mainboard_silicon_init_params(FSP_S_CONFIG *params) -- To view, visit https://review.coreboot.org/c/coreboot/+/47255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78 Gerrit-Change-Number: 47255 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47254 ) Change subject: soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration ...................................................................... soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. BUG=b:171993054 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3 --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/47254/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 8bd2e5a..1dee304 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -47,6 +47,7 @@ select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT + select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3 Gerrit-Change-Number: 47254 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Expose UPD to disable Precision Time Management
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46856 ) Change subject: soc/intel/tigerlake: Expose UPD to disable Precision Time Management ...................................................................... soc/intel/tigerlake: Expose UPD to disable Precision Time Management Expose a config option that allows disabling the FSP UPD which controls Precision Time Management for a particular PCIe root port. Since this is enabled by default the option is inverted to allow disabling for a particular port while not affecting others. BUG=b:160996445 TEST=boot on volteer with PTM disabled for the NVMe root port Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46856/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f..fcd6b0c 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -242,6 +242,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */ + uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 887241b..1520cfe 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -186,6 +186,7 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = !config->PciePtmDisable[i]; } /* Enable ClkReqDetect for enabled port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Gerrit-Change-Number: 46856 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable RTD3 for SD card
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47377 ) Change subject: mb/google/volteer: Enable RTD3 for SD card ...................................................................... mb/google/volteer: Enable RTD3 for SD card Enable the PCIe RTD3 driver for the PCIe attached SD card interface and provide the enable/reset GPIOs. These GPIOs are common across all variants so this is implemented in the baseboard devicetree with an fw_config probe if the device is present. The RTS5261 device does not have an enable GPIO so it is disabled in a workaround in mainboard.c, along with marking the SD-Express device as external. BUG=b:162289926, b:162289982 TEST=Tested on Delbin platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable. enabling this for the regular Genesys Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 3 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47377/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 0538e74..13e356a 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -66,6 +66,10 @@ PAD_NC(GPP_R7, NONE), }; +static const struct pad_config sd_gl9755s_pads[] = { + PAD_CFG_GPO(GPP_D16, 1, DEEP), +}; + static void fw_config_handle(void *unused) { if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { @@ -93,5 +97,9 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) { + printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n"); + gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 0850e74..b18ef3d 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -16,6 +16,7 @@ #include <vb2_api.h> #include "drivers/intel/pmc_mux/conn/chip.h" +#include "soc/intel/common/block/pcie/rtd3/chip.h" extern struct chip_operations drivers_intel_pmc_mux_conn_ops; @@ -138,6 +139,14 @@ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); } +extern struct chip_operations soc_intel_common_block_pcie_rtd3_ops; + +static bool is_rtd3(struct device *dev) +{ + return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == 0 && + dev->chip_ops == &soc_intel_common_block_pcie_rtd3_ops; +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { bool has_usb4; @@ -150,6 +159,25 @@ memset(params->ITbtPcieRootPortEn, 0, ARRAY_SIZE(params->ITbtPcieRootPortEn) * sizeof(*params->ITbtPcieRootPortEn)); + + /* Configure SD-Express device with differences from devicetree. */ + if (fw_config_probe(FW_CONFIG(DB_SD, SD_RTS5261))) { + const struct device *rp8 = pcidev_path_on_root(PCH_DEVFN_PCIE8); + const struct device *rtd3; + struct soc_intel_common_block_pcie_rtd3_config *config; + + if (rp8 && rp8->link_list->children) { + rtd3 = dev_find_matching_device_on_bus(rp8->link_list, is_rtd3); + if (rtd3) { + printk(BIOS_INFO, "Configure SD-Express as External Port\n"); + config = rtd3->chip_info; + config->is_external = 1; + + /* Disable enable GPIO, pin is used for card present. */ + config->enable_gpio.pin_count = 0; + } + } + } } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 20a3843..d923843 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -444,7 +444,17 @@ device ref sata on end device ref pcie_rp1 on end device ref pcie_rp7 on end - device ref pcie_rp8 on end + device ref pcie_rp8 on + probe DB_SD SD_GL9755S + probe DB_SD SD_RTS5261 + chip soc/intel/common/block/pcie/rtd3 + # Enable GPIO is disabled in mainboard.c for RTS5261 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end device ref pcie_rp9 on end device ref pcie_rp11 on end device ref uart0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/47377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26 Gerrit-Change-Number: 47377 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants: Enable RTD3 for the NVMe device
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46262 ) Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ...................................................................... mb/google/volteer/variants: Enable RTD3 for the NVMe device Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/1 diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3..bebf38f 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 21b1f07..ef52517 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -59,6 +59,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..7f806ea 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -126,6 +126,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 8ce6875..7528a4f 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -182,6 +182,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. -- To view, visit https://review.coreboot.org/c/coreboot/+/46262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Gerrit-Change-Number: 46262 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46261 ) Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox ...................................................................... soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox This SOC overrides the common PMC device and instantiates the PMC device in the SSDT. It needs to call the common PMC function to provide the IPC mailbox method. The common PCIe RTD3 driver can also be enabled which will allow mainboards to enable Runtime D3 power control for PCIe devices. BUG=b:160996445 TEST=boot on volteer with this driver enabled for the NVMe device in the devicetree and disassemble the SSDT to ensure that the RTD3 code is present. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/pmc.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 4df2e85..0be2225 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06..a7705de 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -119,6 +119,9 @@ acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); acpigen_write_resourcetemplate_footer(); + /* Define IPC Write Method */ + pmc_acpi_fill_ssdt_ipc_write_method(); + acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc Gerrit-Change-Number: 46261 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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