coreboot-gerrit November 2020

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Change in coreboot[master]: configs: Add a sample config for scaleway tagada
by Julien Viard de Galbert (Code Review) 20 Nov '20

20 Nov '20

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47341 ) Change subject: configs: Add a sample config for scaleway tagada ...................................................................... configs: Add a sample config for scaleway tagada Signed-off-by: Julien Viard de Galbert <julien(a)vdg.name> Change-Id: I39fd9aabe7285d39e1883622ee9d6a60c6651b6e --- A configs/config.scaleway_tagada 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47341/1 diff --git a/configs/config.scaleway_tagada b/configs/config.scaleway_tagada new file mode 100644 index 0000000..1ec73c4 --- /dev/null +++ b/configs/config.scaleway_tagada @@ -0,0 +1,14 @@ +CONFIG_VENDOR_SCALEWAY=y +CONFIG_CBFS_SIZE=0x400000 +CONFIG_CONSOLE_POST=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_IQAT_ENABLE is not set +CONFIG_ENABLE_HSUART=y +CONFIG_USE_DENVERTON_NS_FSP_CAR=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd" +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_BOOT_STATE=y -- To view, visit https://review.coreboot.org/c/coreboot/+/47341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fd9aabe7285d39e1883622ee9d6a60c6651b6e Gerrit-Change-Number: 47341 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46555 ) Change subject: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback ...................................................................... soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 11fe44b..c017d79 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,7 +14,9 @@ #include <soc/ramstage.h> #include <soc/pm.h> #include <soc/soc_util.h> +#include <soc/pci_devs.h> #include <stdlib.h> +#include <security/intel/txt/txt_platform.h> /* C620 IOAPIC has 120 redirection entries */ #define C620_IOAPIC_REDIR_ENTRIES 120 @@ -558,6 +560,38 @@ DEV_FUNC_EXIT(dev); } +union dpr_register txt_get_chipset_dpr(void) +{ + struct iiostack_resource info; + union dpr_register dpr; + const pci_devfn_t VTD = PCI_DEVFN(VTD_DEV, VTD_FUNC); + const struct device *dev = pcidev_path_on_root(VTD); + + if (dev == NULL) + die("Unable to find VTD PCI DEV"); + + dpr.raw = pci_read_config32(dev, VTD_LTDPR); + + get_iiostack_info(&info); + for (int s = 1; s < info.no_of_stacks; s++) { + uint8_t bus = info.res[s].BusBase; + dev = pcidev_path_on_bus(bus, VTD); + + if (dev == NULL) + die("Unable to find VTD PCI DEV"); + + union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (memcmp(&dpr, &test_dpr, sizeof(dpr))) { + printk(BIOS_ERR, "LTDPR not the same on all IIO's"); + /* TODO: Have the caller check this */ + dpr.raw = 0; + return dpr; + } + } + + return dpr; +} + struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 965bb66..4d04105 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -70,6 +70,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_LTDPR 0x290 /* CPU Devices */ #define CBDMA_DEV_NUM 0x04 -- To view, visit https://review.coreboot.org/c/coreboot/+/46555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Gerrit-Change-Number: 46555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/25436 ) Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/scaleway/tagada/gpio_defs.h M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/scaleway/tagada/hsio.h 3 files changed, 89 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h new file mode 100644 index 0000000..b89ad5a --- /dev/null +++ b/src/mainboard/scaleway/tagada/gpio_defs.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_GPIO_DEFS_H +#define _MAINBOARD_GPIO_DEFS_H + +#include <soc/gpio_defs.h> + +// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED +#define GPIO_GPIO_0 0 +#define R_PAD_CFG_DW0_GPIO_0 0x4d8 +#define PID_GPIO_0 PID_NorthCommunity + +// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn +#define GPIO_GPIO_4 4 +#define R_PAD_CFG_DW0_GPIO_4 0x568 +#define PID_GPIO_4 PID_SouthCommunity + +// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn +#define GPIO_GPIO_5 5 +#define R_PAD_CFG_DW0_GPIO_5 0x570 +#define PID_GPIO_5 PID_SouthCommunity + + +// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select +#define GPIO_GPIO_8 8 +#define R_PAD_CFG_DW0_GPIO_8 0x5c8 +#define PID_GPIO_8 PID_SouthCommunity + +// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose +#define GPIO_GPIO_9 9 +#define R_PAD_CFG_DW0_GPIO_9 0x5d0 +#define PID_GPIO_9 PID_SouthCommunity + +#endif /* _MAINBOARD_GPIO_DEFS_H */ diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c index fd6afa8..7859923 100644 --- a/src/mainboard/scaleway/tagada/hsio.c +++ b/src/mainboard/scaleway/tagada/hsio.c @@ -1,12 +1,62 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/mmio.h> +#include <console/console.h> #include <hsio.h> +#include <gpio_defs.h> #include <soc/fiamux.h> +#ifdef __RAMSTAGE__ +static void update_hsio_info_for_m2_slots(size_t num_of_entry, BL_HSIO_INFORMATION *config) +{ + uint32_t reg32; + bool m2a_pcie, m2b_pcie; + uint8_t entry; + + /* Detects modules type */ + // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4, R_PAD_CFG_DW0_GPIO_4)); + m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; + // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe + reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5, R_PAD_CFG_DW0_GPIO_5)); + m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE) ? 1 : 0; + + printk(BIOS_DEBUG, + "GPIO values from M2 slots A:%d B:%d " + "(0=SATA, 1=PCIe or not populated)\n", + m2a_pcie, m2b_pcie); + + // HSIO default config is for PCIe, only update for SATA + // (also secondary PCIe lines are already set depending on SKU) + for (entry = 0; entry < num_of_entry; entry++) { + BL_ME_FIA_MUX_CONFIG *mux_config = &(config[entry].FiaConfig.MuxConfiguration); + BL_ME_FIA_SATA_CONFIG *sata_config = + &(config[entry].FiaConfig.SataLaneConfiguration); + if (!m2a_pcie) { + // change Lane 14 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + if (!m2b_pcie) { + // change Lane 12 config + mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel = + BL_ME_FIA_MUX_LANE_SATA; + sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel = + BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED; + } + } +} +#endif + size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { - size_t num; - num = ARRAY_SIZE(tagada_hsio_config); - (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; - return num; + size_t num; + num = ARRAY_SIZE(tagada_hsio_config); +#ifdef __RAMSTAGE__ + update_hsio_info_for_m2_slots(num, tagada_hsio_config); +#endif + (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config; + return num; } diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h index 4e3a2c1..8a25a04 100644 --- a/src/mainboard/scaleway/tagada/hsio.h +++ b/src/mainboard/scaleway/tagada/hsio.h @@ -6,7 +6,7 @@ #include <fsp/util.h> #ifndef __ACPI__ -const BL_HSIO_INFORMATION tagada_hsio_config[] = { +DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = { /* * Supported Lanes: * 20 -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25436 ) Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 21 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Nov 2020 00:43:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Initialize thermal configuration
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/25439 ) Change subject: soc/intel/denverton_ns: Initialize thermal configuration ...................................................................... soc/intel/denverton_ns: Initialize thermal configuration Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25439 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h 2 files changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 1fd233a..1dc0830 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -53,6 +53,21 @@ write_cr4(read_cr4() | CR4_MCE); } +static void configure_thermal_core(void) +{ + msr_t msr; + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= THERMAL_MONITOR_ENABLE_BIT; /* TM1/TM2/EMTTM enable */ + wrmsr(IA32_MISC_ENABLE, msr); +} + static void denverton_core_init(struct device *cpu) { msr_t msr; @@ -62,6 +77,9 @@ /* Clear out pending MCEs */ dnv_configure_mca(); + /* Configure Thermal Sensors */ + configure_thermal_core(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 1f64235..89caf44 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -22,6 +22,8 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) +/* IA32_MISC_ENABLE 0x1a0 */ +#define THERMAL_MONITOR_ENABLE_BIT (1 << 3) #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad -- To view, visit https://review.coreboot.org/c/coreboot/+/25439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b924154256f8f82ded3d0fa155b3e836d9375 Gerrit-Change-Number: 25439 Gerrit-PatchSet: 22 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/denverton_ns: Enable MC Exception
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/25434 ) Change subject: soc/intel/denverton_ns: Enable MC Exception ...................................................................... soc/intel/denverton_ns: Enable MC Exception Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25434 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/cpu.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 7cee5be..1fd233a 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/cr.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -44,6 +45,12 @@ of these banks are core vs package scope. For now every CPU clears every bank. */ mca_configure(); + + /* TODO install a fallback MC handler for each core in case OS does + not provide one. Is it really needed? */ + + /* Enable the machine check exception */ + write_cr4(read_cr4() | CR4_MCE); } static void denverton_core_init(struct device *cpu) -- To view, visit https://review.coreboot.org/c/coreboot/+/25434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9773c61d06bb6c68612e498a35b5ad22cd5a8a6e Gerrit-Change-Number: 25434 Gerrit-PatchSet: 20 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <d.guckian20(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: merged

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Change in coreboot[master]: src/soc/intel/denverton_ns: Update to several improvement in coreboot...
by Julien Viard de Galbert (Code Review) 20 Nov '20

20 Nov '20

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47340 ) Change subject: src/soc/intel/denverton_ns: Update to several improvement in coreboot since 4.9 ...................................................................... src/soc/intel/denverton_ns: Update to several improvement in coreboot since 4.9 Signed-off-by: Julien Viard de Galbert <julien(a)vdg.name> Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea --- M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/Makefile.inc 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47340/1 diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 89bbbb0..888713a 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -7,6 +7,10 @@ if SOC_INTEL_DENVERTON_NS +config CPU_INTEL_NUM_FIT_ENTRIES + int + default 1 + config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 @@ -21,6 +25,7 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP select PCR_COMMON_IOSF_1_0 + select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU @@ -153,10 +158,14 @@ hex default 0x8000 -config DENVERTON_NS_CAR_NEM_ENHANCED +choice + prompt "Cache-as-ram implementation" + default USE_DENVERTON_NS_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" - depends on !FSP_CAR - default y select SOC_INTEL_COMMON_BLOCK_CAR select USE_CAR_NEM_ENHANCED_V1 help @@ -167,4 +176,12 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. +config USE_DENVERTON_NS_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + endif ## SOC_INTEL_DENVERTON_NS diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 105f866..c854037 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_SOC_INTEL_DENVERTON_NS),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01 + subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic -- To view, visit https://review.coreboot.org/c/coreboot/+/47340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc5ce91118c6052af23642fb3461f574cd888dea Gerrit-Change-Number: 47340 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 20 Nov '20

20 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 58: (1 comment) https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/ramstage.c: https://review.coreboot.org/c/coreboot/+/39133/48/src/mainboard/kontron/mal… PS48, Line 41: LPSS_S0ixEnable > Yes, enabled. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 58 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 00:40:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Remove unnecessary per-rank loops
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47609 ) Change subject: nb/intel/sandybridge: Remove unnecessary per-rank loops ...................................................................... nb/intel/sandybridge: Remove unnecessary per-rank loops The IOSAV_By_BW_MASK_ch registers are not per-rank. To preserve original behavior, use a for-populated-channels loop instead of for-all-channels. Tested on Asus P8H61-M PRO, still boots. Change-Id: I6db35c41cd05420ceaeda93255f5ed73598a5bdd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47609/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 77c0173..d8ad342 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1418,7 +1418,7 @@ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -2063,7 +2063,7 @@ precharge(ctrl); printram("CPF\n"); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } @@ -2086,7 +2086,7 @@ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -2505,7 +2505,7 @@ program_timings(ctrl, channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -2641,7 +2641,7 @@ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } return 0; @@ -3150,7 +3150,7 @@ void restore_timings(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, lane; FOR_ALL_POPULATED_CHANNELS { const union tc_rap_reg tc_rap = { @@ -3171,7 +3171,7 @@ wait_for_iosav(channel); } - FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { + FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6db35c41cd05420ceaeda93255f5ed73598a5bdd Gerrit-Change-Number: 47609 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Rename `discover_edges` functions
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47610 ) Change subject: nb/intel/sandybridge: Rename `discover_edges` functions ...................................................................... nb/intel/sandybridge: Rename `discover_edges` functions These are simply read MPR training, using the MPR pattern mode in MR3. Change-Id: Icdc60572e0ee0b59dcb5dee1e1aceccfda79f029 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47610/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 86e3e61..0837f3a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2343,7 +2343,7 @@ return 0; } -static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int dqs_pi; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; @@ -2447,7 +2447,7 @@ } } -int discover_edges(ramctr_timing *ctrl) +int read_mpr_training(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2476,7 +2476,7 @@ printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_real(ctrl, channel, slotrank, + err = find_read_mpr_margin(ctrl, channel, slotrank, falling_edges[channel][slotrank]); if (err) return err; @@ -2486,7 +2486,7 @@ printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_real(ctrl, channel, slotrank, + err = find_read_mpr_margin(ctrl, channel, slotrank, rising_edges[channel][slotrank]); if (err) return err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 5227536..e3be5c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -403,7 +403,7 @@ int receive_enable_calibration(ramctr_timing *ctrl); int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); -int discover_edges(ramctr_timing *ctrl); +int read_mpr_training(ramctr_timing *ctrl); int discover_edges_write(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 20009cb..e0b5a3d 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -690,7 +690,7 @@ printram("CP5a\n"); - err = discover_edges(ctrl); + err = read_mpr_training(ctrl); if (err) return err; -- To view, visit https://review.coreboot.org/c/coreboot/+/47610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdc60572e0ee0b59dcb5dee1e1aceccfda79f029 Gerrit-Change-Number: 47610 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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