coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/apollolake: use P2SB function to generate DMAR IOAPIC
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47535 ) Change subject: soc/intel/apollolake: use P2SB function to generate DMAR IOAPIC ...................................................................... soc/intel/apollolake: use P2SB function to generate DMAR IOAPIC Change-Id: If088d5bf701310e54b14965145229627f3a50417 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/acpi.c 1 file changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47535/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 8609c7c..d0e7a73 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -185,22 +185,14 @@ /* DEFVTBAR has to be set and enabled. */ if (defvtbar && defvten) { tmp = current; - /* - * P2SB may already be hidden. There's no clear rule, when. - * It is needed to get bus, device and function for IOAPIC and - * HPET device which is stored in P2SB device. So unhide it to - * get the info and hide it again when done. - */ - p2sb_unhide(); - struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); - uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); + union p2sb_bdf ibdf = p2sb_get_ioapic_bdf(); union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); p2sb_hide(); current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); + 2, ibdf.bus, ibdf.dev, ibdf.fn); current += acpi_create_dmar_ds_msi_hpet(current, 0, hbdf.bus, hbdf.dev, hbdf.fn); acpi_dmar_drhd_fixup(tmp, current); -- To view, visit https://review.coreboot.org/c/coreboot/+/47535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If088d5bf701310e54b14965145229627f3a50417 Gerrit-Change-Number: 47535 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add ioapic BDF functions
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47534 ) Change subject: soc/intel/common/block/p2sb: Add ioapic BDF functions ...................................................................... soc/intel/common/block/p2sb: Add ioapic BDF functions This allows to get/set the IOAPIC bus device function. Change-Id: Ib5bb409efbcbc5729cf0e996655c7ac3f6a78223 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/p2sb.c 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47534/1 diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 7cf0c48..33102db 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -40,6 +40,9 @@ union p2sb_bdf p2sb_get_hpet_bdf(void); void p2sb_set_hpet_bdf(union p2sb_bdf bdf); +union p2sb_bdf p2sb_get_ioapic_bdf(void); +void p2sb_set_ioapic_bdf(union p2sb_bdf bdf); + /* SOC overrides */ /* diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 93f711f..716b4ee 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -72,6 +72,22 @@ pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw); } +union p2sb_bdf p2sb_get_ioapic_bdf(void) +{ + union p2sb_bdf bdf; + bool p2sb_state = p2sb_is_hiden(); + p2sb_unhide(); + bdf.raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF); + if (p2sb_state) + p2sb_hide(); + return bdf; +} + +void p2sb_set_ioapic_bdf(union p2sb_bdf bdf) +{ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, bdf.raw); +} + static void p2sb_set_hide_bit(int hide) { const uint16_t reg = PCH_P2SB_E0 + 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/47534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5bb409efbcbc5729cf0e996655c7ac3f6a78223 Gerrit-Change-Number: 47534 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47533 ) Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR ...................................................................... soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR This makes coreboot more robust as it does not need to rely on syncing values set by FSP and coreboot. Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/nb_acpi.c 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47533/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3d3e803..5c7a667 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -49,6 +49,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_P2SB select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 4a44980..f4d9da3 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -12,6 +12,7 @@ #include <soc/pci_devs.h> #include <soc/soc_util.h> #include <soc/util.h> +#include <intelblocks/p2sb.h> #include "chip.h" @@ -267,11 +268,12 @@ //BIT 15 if (num_hpets && (num_hpets != 0x1f) && (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf(); printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); - current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, - HPET_DEV_NUM, HPET0_FUNC_NUM); + 0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn); + current += acpi_create_dmar_ds_msi_hpet(current, 0, hpet_bdf.bus, + hpet_bdf.dev, hpet_bdf.fn); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776 Gerrit-Change-Number: 47533 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: use P2SB function to generate DMAR HPET
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47532 ) Change subject: soc/intel/apollolake: use P2SB function to generate DMAR HPET ...................................................................... soc/intel/apollolake: use P2SB function to generate DMAR HPET Change-Id: I68f63c79d04cb2cddb92c9f6385459723f8858bd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47532/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ee1a543..8609c7c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -194,7 +194,7 @@ p2sb_unhide(); struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); - uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); + union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); p2sb_hide(); current += acpi_create_dmar_drhd(current, @@ -202,7 +202,7 @@ current += acpi_create_dmar_ds_ioapic(current, 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); current += acpi_create_dmar_ds_msi_hpet(current, - 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + 0, hbdf.bus, hbdf.dev, hbdf.fn); acpi_dmar_drhd_fixup(tmp, current); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f63c79d04cb2cddb92c9f6385459723f8858bd Gerrit-Change-Number: 47532 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add hpet BDF functions
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47531 ) Change subject: soc/intel/common/block/p2sb: Add hpet BDF functions ...................................................................... soc/intel/common/block/p2sb: Add hpet BDF functions This allows to get/set the HPET bus device function. Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/p2sb.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47531/1 diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 71f9c62..7cf0c48 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -29,6 +29,18 @@ void p2sb_enable_bar(void); void p2sb_configure_hpet(void); +union p2sb_bdf { + uint16_t raw; + struct { + uint16_t fn : 3; + uint16_t dev : 5; + uint16_t bus : 8; + }; +}; + +union p2sb_bdf p2sb_get_hpet_bdf(void); +void p2sb_set_hpet_bdf(union p2sb_bdf bdf); + /* SOC overrides */ /* * Each SoC should implement EP Mask register to disable SB access diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index b5f9a07..93f711f 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -56,6 +56,22 @@ pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); } +union p2sb_bdf p2sb_get_hpet_bdf(void) +{ + union p2sb_bdf bdf; + bool p2sb_state = p2sb_is_hiden(); + p2sb_unhide(); + bdf.raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF); + if (p2sb_state) + p2sb_hide(); + return bdf; +} + +void p2sb_set_hpet_bdf(union p2sb_bdf bdf) +{ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw); +} + static void p2sb_set_hide_bit(int hide) { const uint16_t reg = PCH_P2SB_E0 + 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/47531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e Gerrit-Change-Number: 47531 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/p2sb: Add helper function to determine p2sb state
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47530 ) Change subject: soc/intel/common/p2sb: Add helper function to determine p2sb state ...................................................................... soc/intel/common/p2sb: Add helper function to determine p2sb state Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/p2sb/p2sb.c 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47530/1 diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index d97cd8d..b5f9a07 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -15,6 +15,20 @@ #define HIDE_BIT (1 << 0) +static bool p2sb_is_hiden(void) +{ + bool valid_vid = pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) == + PCI_VENDOR_ID_INTEL; + bool read_ones = pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) == 0xffff; + + if (read_ones) + return true; + if (valid_vid) + return false; + printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n"); + return true; +} + void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ @@ -59,8 +73,7 @@ { p2sb_set_hide_bit(0); - if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != - PCI_VENDOR_ID_INTEL) + if (p2sb_is_hiden()) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to unhide PCH_DEV_P2SB device !\n"); } @@ -69,8 +82,7 @@ { p2sb_set_hide_bit(1); - if (pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID) != - 0xFFFF) + if (!p2sb_is_hiden()) die_with_post_code(POST_HW_INIT_FAILURE, "Unable to hide PCH_DEV_P2SB device !\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d6f9c18160806e289e98c2fa5d290c61434112f Gerrit-Change-Number: 47530 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack
by Frans Hendriks (Code Review) 20 Nov '20

20 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47737 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack ...................................................................... drivers/intel/fsp1_1/cache_as_ram.S: Use _car_stack area for stack Top of Temp RAM is used as bootloader stack, which is the _car_region_end area. This area is not equal to CAR stack area as defined in car.ld file. Use _ecar_stack (end of CAR stack) as starting stack location. Tested VBOOT, Vendorboot security and no security on Facebook FBG1701. Change-Id: I16b077f60560de334361b1f0d3758ab1a5cbe895 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47737/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..3be9eb9 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -133,7 +133,7 @@ jne halt2 /* Setup bootloader stack */ - movl %edx, %esp + movl $_ecar_stack, %esp /* * ebp: FSP_INFO_HEADER address -- To view, visit https://review.coreboot.org/c/coreboot/+/47737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16b077f60560de334361b1f0d3758ab1a5cbe895 Gerrit-Change-Number: 47737 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 58: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 58 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 08:43:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8192: memlayout: Add DRAM DMA region
by Yidi Lin (Code Review) 20 Nov '20

20 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47293 ) Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ...................................................................... mediatek/mt8192: memlayout: Add DRAM DMA region SPM DMA hardware requires a non-cacheable buffer to load SPM firmware. TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/include/soc/symbols.h M src/soc/mediatek/mt8192/mmu_operations.c 4 files changed, 26 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47293/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index ca66095..f348a20 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 891b782..a1c1be6 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -37,8 +42,9 @@ SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 512K) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 512K) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/include/soc/symbols.h b/src/soc/mediatek/mt8192/include/soc/symbols.h new file mode 100644 index 0000000..a7feee7 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620e..e3bc622 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h> DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e803da23126419a96ffc0337d35edd0e181871 Gerrit-Change-Number: 47293 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Enable MT8192 auxadc driver
by JG Poxu (Code Review) 20 Nov '20

20 Nov '20

Hello Po Xu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47695 to review the following change. Change subject: soc/mediatek: Enable MT8192 auxadc driver ...................................................................... soc/mediatek: Enable MT8192 auxadc driver Enable MT8192 auxadc driver [Description] Reference datasheet: RH-A-2020-0070, v1.0 Signed-off-by: Po Xu <jg_poxu(a)mediatek.com> Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/auxadc.h A src/soc/mediatek/mt8192/include/soc/efuse.h 4 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47695/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 3237d40..07a13af 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) +bootblock-y += ../common/auxadc.c bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -13,12 +14,14 @@ bootblock-y += mt6315.c bootblock-y += mt6359p.c +verstage-y += ../common/auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c +romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c @@ -31,6 +34,7 @@ romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c romstage-y += mt6359p.c +ramstage-y += ../common/auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e9cb788..9760c88 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -26,6 +26,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, @@ -37,6 +38,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h new file mode 100644 index 0000000..3289a22 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include <soc/auxadc_common.h> +#include <soc/infracfg.h> +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +static struct mt8192_infracfg_regs *const mtk_infracfg = mt8192_infracfg; + +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h new file mode 100644 index 0000000..f0f3405 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c965fc3571637d882eb297e405a5d9e6f77dd3 Gerrit-Change-Number: 47695 Gerrit-PatchSet: 1 Gerrit-Owner: JG Poxu <jg_poxu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Po Xu <jg_poxu(a)mediatek.com> Gerrit-MessageType: newchange

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