coreboot-gerrit November 2020

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Change in coreboot[master]: vc/intel/fsp2/denverton: Remove unused files
by Felix Singer (Code Review) 20 Nov '20

20 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47754 ) Change subject: vc/intel/fsp2/denverton: Remove unused files ...................................................................... vc/intel/fsp2/denverton: Remove unused files The Denverton SoC uses the header files from the git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M MAINTAINERS D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h 5 files changed, 0 insertions(+), 1,157 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/47754/1 diff --git a/MAINTAINERS b/MAINTAINERS index 1f4df52..6a1f500 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -511,7 +511,6 @@ S: Odd Fixes F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ -F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/ INTEL FSP 1.1 M: Lee Leahy <leroy.p.leahy(a)intel.com> diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h deleted file mode 100644 index 1aa46a0..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include <FspEas.h> - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F445055564E44 /* 'DNVUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F445055564E44 /* 'DNVUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F445055564E44 /* 'DNVUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h deleted file mode 100644 index 3aa74a0f..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h +++ /dev/null @@ -1,710 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - -#define MAX_CH 2 /* Maximum Number of Memory Channels */ -#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */ -#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */ - -/* - * Memory Down structures. - */ -typedef enum { - STATE_MEMORY_SLOT = 0, /* No memory down and a physical memory slot. */ - STATE_MEMORY_DOWN = 1, /* Memory down and not a physical memory slot. */ -} MemorySlotState; - -typedef struct { - MemorySlotState SlotState[MAX_CH][MAX_DIMM]; /* Memory Down state of - each DIMM in each - Channel */ - UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */ - UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Pointer to SPD Data for each - DIMM in each Channel */ -} MEMORY_DOWN_CONFIG; - -/* -* SMBIOS Memory Info structures. -*/ -typedef struct { - UINT8 DimmId; - UINT32 SizeInMb; - UINT16 MfgId; - UINT8 - ModulePartNum[20]; /* Module part number for DDR3 is 18 bytes - however for DRR4 20 bytes as per JEDEC Spec, - so reserving 20 bytes */ -} DIMM_INFO; - -typedef struct { - UINT8 ChannelId; - UINT8 DimmCount; - DIMM_INFO DimmInfo[MAX_DIMM]; -} CHANNEL_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; - UINT16 MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - UINT8 ChannelCount; - CHANNEL_INFO ChannelInfo[MAX_CH]; -} FSP_SMBIOS_MEMORY_INFO; - -/* -* GBE PCD supported states. -*/ -typedef enum { - BL_GBE0_GBE1_DISABLED, - BL_GBE0_GBE1_ENABLED, - BL_GBE1_DISABLED, -} BL_GBE_PCD_STATE; - -/* -* FIA MUX configuration structures. -*/ - -#define BL_ME_FIA_MUX_LANE_NUM_MAX 20 -#define BL_ME_FIA_MUX_LANE_NUM_MIN 1 -#define BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH 2 -#define BL_ME_FIA_MUX_LANE_MUX_SEL_MASK 0x3 -#define BL_ME_FIA_MUX_LANE_XHCI_ONLY 0xFF00000000 - -typedef enum { - BL_FIA_LANE00 = 0, - BL_FIA_LANE01, - BL_FIA_LANE02, - BL_FIA_LANE03, - BL_FIA_LANE04, - BL_FIA_LANE05, - BL_FIA_LANE06, - BL_FIA_LANE07, - BL_FIA_LANE08, - BL_FIA_LANE09, - BL_FIA_LANE10, - BL_FIA_LANE11, - BL_FIA_LANE12, - BL_FIA_LANE13, - BL_FIA_LANE14, - BL_FIA_LANE15, - BL_FIA_LANE16, - BL_FIA_LANE17, - BL_FIA_LANE18, - BL_FIA_LANE19, -} BL_ME_FIA_MUX_LANE_ORDER; - -#define BL_ME_FIA_MUX_LANE_SATA0_BEGING BL_FIA_LANE04 -#define BL_ME_FIA_MUX_LANE_SATA1_BEGING BL_FIA_LANE12 - -#define BL_FIA_LANE_CONFIG(Config, Lane) \ - ((UINT64)((UINT64)(Config) \ - << ((UINT64)(Lane) * (BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH)))) - -typedef union _BL_ME_FIA_MUX_CONFIG { - UINT64 MeFiaMuxLaneConfig; - struct { - UINT64 Lane00MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane01MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane02MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane03MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE - UINT64 Lane04MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane05MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane06MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane07MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane08MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane09MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane10MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane11MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane12MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane13MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane14MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane15MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or - // SATA - UINT64 Lane16MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane17MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane18MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Lane19MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or - // SATA - UINT64 Reserved : 24; - } BL_MeFiaMuxLaneMuxSel; -} BL_ME_FIA_MUX_CONFIG; - -typedef enum { - BL_ME_FIA_MUX_LANE_DISCONNECTED, - BL_ME_FIA_MUX_LANE_PCIE, - BL_ME_FIA_MUX_LANE_SATA, - BL_ME_FIA_MUX_LANE_XHCI, -} BL_ME_FIA_MUX_LANE_CONFIG; - -#define BL_ME_FIA_SATA_LANE_SEL_WIDTH 2 -#define BL_ME_FIA_SATA_LANE_XHCI_ONLY 0x55000000 - -typedef enum { - BL_FIA_SATA_LANE04 = 0, - BL_FIA_SATA_LANE05, - BL_FIA_SATA_LANE06, - BL_FIA_SATA_LANE07, - BL_FIA_SATA_LANE08, - BL_FIA_SATA_LANE09, - BL_FIA_SATA_LANE10, - BL_FIA_SATA_LANE11, - BL_FIA_SATA_LANE12, - BL_FIA_SATA_LANE13, - BL_FIA_SATA_LANE14, - BL_FIA_SATA_LANE15, - BL_FIA_SATA_LANE16, - BL_FIA_SATA_LANE17, - BL_FIA_SATA_LANE18, - BL_FIA_SATA_LANE19 -} BL_ME_FIA_SATA_LANE_ORDER; - -#define BL_FIA_SATA_LANE_CONFIG(Config, Lane) \ - ((UINT32)((UINT32)(Config) \ - << ((UINT32)(Lane) * (BL_ME_FIA_SATA_LANE_SEL_WIDTH)))) - -typedef union _BL_ME_FIA_SATA_CONFIG { - UINT64 MeFiaSataLaneConfig; - struct { - UINT64 Lane04SataSel : 2; - UINT64 Lane05SataSel : 2; - UINT64 Lane06SataSel : 2; - UINT64 Lane07SataSel : 2; - UINT64 Lane08SataSel : 2; - UINT64 Lane09SataSel : 2; - UINT64 Lane10SataSel : 2; - UINT64 Lane11SataSel : 2; - UINT64 Lane12SataSel : 2; - UINT64 Lane13SataSel : 2; - UINT64 Lane14SataSel : 2; - UINT64 Lane15SataSel : 2; - UINT64 Lane16SataSel : 2; - UINT64 Lane17SataSel : 2; - UINT64 Lane18SataSel : 2; - UINT64 Lane19SataSel : 2; - UINT64 Reserved : 32; - } BL_MeFiaSataLaneSataSel; -} BL_ME_FIA_SATA_CONFIG; - -typedef enum { - BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED = 0, - BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED = 1, - BL_ME_FIA_SATA_CONTROLLER_LANE_SS_AND_GPIO_ASSIGNED = 3 -} BL_ME_FIA_SATA_LANE_CONFIG; - -#define BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH 4 -#define BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH 8 -#define BL_ME_FIA_PCIE_ROOT_CONFIG_XHCI_ONLY 0x0 - -typedef enum { - BL_FIA_PCIE_ROOT_PORT_0 = 0, - BL_FIA_PCIE_ROOT_PORT_1, - BL_FIA_PCIE_ROOT_PORT_2, - BL_FIA_PCIE_ROOT_PORT_3, - BL_FIA_PCIE_ROOT_PORT_4, - BL_FIA_PCIE_ROOT_PORT_5, - BL_FIA_PCIE_ROOT_PORT_6, - BL_FIA_PCIE_ROOT_PORT_7 -} BL_ME_FIA_PCIE_ROOT_PORT_ORDER; - -#define BL_FIA_PCIE_ROOT_PORT_CONFIG(Type, Config, PcieRootPort) \ - (((Type) == BL_ME_FIA_PCIE_ROOT_PORT_STATE) \ - ? ((UINT64)((UINT64)(Config) << (UINT64)(PcieRootPort))) \ - : ((UINT64)( \ - (UINT64)(Config) << (UINT64)( \ - ((UINT64)(PcieRootPort) * \ - (BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH)) + \ - BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH)))) - -typedef union _BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG { - UINT64 MeFiaPcieRootPortsConfig; - struct { - UINT64 PcieRp0En : 1; - UINT64 PcieRp1En : 1; - UINT64 PcieRp2En : 1; - UINT64 PcieRp3En : 1; - UINT64 PcieRp4En : 1; - UINT64 PcieRp5En : 1; - UINT64 PcieRp6En : 1; - UINT64 PcieRp7En : 1; - UINT64 PcieRp0LinkWidth : 4; - UINT64 PcieRp1LinkWidth : 4; - UINT64 PcieRp2LinkWidth : 4; - UINT64 PcieRp3LinkWidth : 4; - UINT64 PcieRp4LinkWidth : 4; - UINT64 PcieRp5LinkWidth : 4; - UINT64 PcieRp6LinkWidth : 4; - UINT64 PcieRp7LinkWidth : 4; - UINT64 Reserved : 24; - } BL_MeFiaPcieRpConfig; -} BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_STATE, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH -} BL_ME_FIA_PCIE_ROOT_PORT_CONFIG_TYPE; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_DISABLED, - BL_ME_FIA_PCIE_ROOT_PORT_ENABLED -} BL_ME_FIA_PCIE_ROOT_PORT_STATE_CONFIG; - -typedef enum { - BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL = 0, - BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1 = 0xF -} BL_ME_FIA_PCIE_ROOT_PORT_LINK_CONFIG; - -typedef struct _BL_ME_FIA_CONFIG { - BL_ME_FIA_MUX_CONFIG MuxConfiguration; - BL_ME_FIA_SATA_CONFIG SataLaneConfiguration; - BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG PcieRootPortsConfiguration; -} BL_ME_FIA_CONFIG; - -/* - * The FIA_MUX_CONFIG block describes the expected configuration of - * FIA MUX configuration. - */ -typedef struct { - UINT32 SkuNumLanesAllowed; // Platform view of Num Lanes allowed - BL_ME_FIA_CONFIG FiaMuxConfig; // Current Platform FIA MUX Configuration - BL_ME_FIA_CONFIG FiaMuxConfigRequest; // FIA MUX Configuration Requested -} BL_FIA_MUX_CONFIG; - -/* - * The FIA_MUX_CONFIG_STATUS describes the status of configuring - * FIA MUX configuration. -*/ -typedef struct { - UINT64 FiaMuxConfigGetStatus; // Status returned from FiaMuxConfigGet, - // if not EFI_SUCCESS, then error occurred - // and user can decide on next steps - UINT64 FiaMuxConfigSetStatus; // Status returned from FiaMuxConfigSet, - // if not EFI_SUCCESS, then error occurred - // and user can decide on next steps - BOOLEAN FiaMuxConfigSetRequired; // Boolean: true - a FiaMuxConfigSet - // was required, false otherwise -} BL_FIA_MUX_CONFIG_STATUS; - -/* -* FIA MUX Config HOB structure -*/ -typedef struct { - BL_FIA_MUX_CONFIG FiaMuxConfig; - BL_FIA_MUX_CONFIG_STATUS FiaMuxConfigStatus; -} BL_FIA_MUX_CONFIG_HOB; - -/* PCIe port bifurcation codes - matches setup option values */ -#define PCIE_BIF_CTRL_x2x2x2x2 0 -#define PCIE_BIF_CTRL_x2x2x4 1 -#define PCIE_BIF_CTRL_x4x2x2 2 -#define PCIE_BIF_CTRL_x4x4 3 -#define PCIE_BIF_CTRL_x8 4 - -#define BL_MAX_PCIE_CTRL 2 - -/* - * HSIO INFORMATION structure - */ -typedef enum { - BL_SKU_HSIO_06 = 6, - BL_SKU_HSIO_08 = 8, - BL_SKU_HSIO_10 = 10, - BL_SKU_HSIO_12 = 12, - BL_SKU_HSIO_20 = 20, -} BL_SKU_HSIO_LANE_NUMBER; - -typedef struct { - UINT16 NumLanesSupported; - UINT8 PcieBifCtr[BL_MAX_PCIE_CTRL]; - BL_ME_FIA_CONFIG FiaConfig; -} BL_HSIO_INFORMATION; - -/* - * eMMC DLL structure for EMMC DLL registers settings - */ -typedef struct { - UINT32 TxCmdCntl; - UINT32 TxDataCntl1; - UINT32 TxDataCntl2; - UINT32 RxCmdDataCntl1; - UINT32 RxStrobeCntl; - UINT32 RxCmdDataCntl2; - UINT32 MasterSwCntl; -} BL_EMMC_DLL_CONFIG; - -typedef struct { - UINT16 Signature; - BL_EMMC_DLL_CONFIG eMMCDLLConfig; -} BL_EMMC_INFORMATION; - -typedef enum { - BL_FAST_BOOT_CHECKER_NORMAL = 0, - BL_FAST_BOOT_CHECKER_WARNING, - BL_FAST_BOOT_CHECKER_CRITICAL -} BL_FAST_BOOT_CHECKER; - -#define BL_MAX_SCRUB_SEGMENTS 5 - -typedef struct { - UINT16 Start; // Determines the low range for a memory segment (in MB) - UINT16 End; // Determines the high range for a memory segment (in MB) -} BL_SCRUB_SEGMENT; - -typedef struct { - UINT8 NumberOfSegments; - UINT8 Reserved; - BL_SCRUB_SEGMENT ScrubSegment[BL_MAX_SCRUB_SEGMENTS]; -} BL_MEMORY_SCRUB_SEGMENTS; - -/** Fsp M Configuration -**/ -typedef struct { - - /** Offset 0x0040 - Tseg Size - Size of SMRAM memory reserved. - 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB - **/ - UINT8 PcdSmmTsegSize; - - /** Offset 0x0041 - FSP Debug Print Level - Select the FSP debug message print level. - 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG - **/ - UINT8 PcdFspDebugPrintErrorLevel; - - /** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_0_0; - - /** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_0_1; - - /** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_1_0; - - /** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address - SPD SMBus Address of each DIMM slot. - **/ - UINT8 PcdSpdSmbusAddress_1_1; - - /** Offset 0x0046 - Enable Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS - **/ - UINT8 PcdMrcRmtSupport; - - /** Offset 0x0047 - RMT CPGC exp_loop_cnt - Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1). - 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, - 13:13, 14:14, 15:15 - **/ - UINT8 PcdMrcRmtCpgcExpLoopCntValue; - - /** Offset 0x0048 - RMT CPGC num_bursts - Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1). - 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, - 13:13, 14:14, 15:15 - **/ - UINT8 PcdMrcRmtCpgcNumBursts; - - /** Offset 0x0049 - Preserve Memory Across Reset - Enable/disable memory preservation across reset. - $EN_DIS - **/ - UINT8 PcdMemoryPreservation; - - /** Offset 0x004A - Fast Boot - Enable/disable Fast Boot function. Once enabled, all following boots - will use the - presaved MRC data to improve the boot performance. - $EN_DIS - **/ - UINT8 PcdFastBoot; - - /** Offset 0x004B - ECC Support - Enable/disable ECC Support. - $EN_DIS - **/ - UINT8 PcdEccSupport; - - /** Offset 0x004C - HSUART Device - Select the PCI High Speed UART Device for Serial Port. - 0:HSUART0, 1:HSUART1, 2:HSUART2 - **/ - UINT8 PcdHsuartDevice; - - /** Offset 0x004D - Memory Down - Enable/disable Memory Down function. - $EN_DIS - **/ - UINT8 PcdMemoryDown; - - /** Offset 0x004E - **/ - UINT32 PcdMemoryDownConfigPtr; - - /** Offset 0x0052 - SATA Controller 0 - Enable/disable SATA Controller 0. - $EN_DIS - **/ - UINT8 PcdEnableSATA0; - - /** Offset 0x0053 - SATA Controller 1 - Enable/disable SATA Controller 1. - $EN_DIS - **/ - UINT8 PcdEnableSATA1; - - /** Offset 0x0054 - Intel Quick Assist Technology - Enable/disable Intel Quick Assist Technology. - $EN_DIS - **/ - UINT8 PcdEnableIQAT; - - /** Offset 0x0055 - SPD Write Disable - Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = - [FORCE_DISABLE]) - 0:Force Enable, 1:Force Disable - **/ - UINT8 PcdSmbusSpdWriteDisable; - - /** Offset 0x0056 - ME_SHUTDOWN Message - Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP - Integration Guide - for details. - $EN_DIS - **/ - UINT8 PcdEnableMeShutdown; - - /** Offset 0x0057 - XHCI Controller - Enable / Disable XHCI controller - $EN_DIS - **/ - UINT8 PcdEnableXhci; - - /** Offset 0x0058 - Memory Frequency - Set DDR Memory Frequency, refer to FSP Integration Guide for details. - 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400 - **/ - UINT8 PcdDdrFreq; - - /** Offset 0x0059 - MMIO Size - Set memory mapped IO space size - 0:2048M, 1:1024M, 2:3072M - **/ - UINT8 PcdMmioSize; - - /** Offset 0x005A - ME HECI Communication - Enable/Disable ME HECI communication - $EN_DIS - **/ - UINT8 PcdMeHeciCommunication; - - /** Offset 0x005B - HSIO Lanes Number - HSIO lanes number of SKU - 6:6, 8:8, 10:10, 12:12, 20:20 - **/ - UINT8 PcdHsioLanesNumber; - - /** Offset 0x005C - **/ - UINT32 PcdFiaMuxConfigPtr; - - /** Offset 0x0060 - Customer Revision - The Customer can set this revision string for their own purpose. - **/ - UINT8 PcdCustomerRevision[32]; - - /** Offset 0x0080 - 32-Bit bus mode - Enable/Disable 32-Bit bus memory mode. - $EN_DIS - **/ - UINT8 PcdHalfWidthEnable; - - /** Offset 0x0081 - TCL Performance - Enable/Disable Tcl timing for performance. - $EN_DIS - **/ - UINT8 PcdTclIdle; - - /** Offset 0x0082 - Interleave Mode - Select Interleave Mode - 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2 - **/ - UINT8 PcdInterleaveMode; - - /** Offset 0x0083 - Memory Thermal Throttling - Enable/disable Memory Thermal Throttling management mode - $EN_DIS - **/ - UINT8 PcdMemoryThermalThrottling; - - /** Offset 0x0084 - Memory Test - Enable / Disable Memory Test, refer to FSP Integration Guide for - details. - $EN_DIS - **/ - UINT8 PcdSkipMemoryTest; - - /** Offset 0x0085 - **/ - BL_MEMORY_SCRUB_SEGMENTS *PcdScrubSegmentPtr; - - /** Offset 0x0089 - USB2 Port 1 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port1Pin; - - /** Offset 0x008A - USB2 Port 2 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port2Pin; - - /** Offset 0x008B - USB2 Port 3 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port3Pin; - - /** Offset 0x008C - USB2 Port 4 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb2Port4Pin; - - /** Offset 0x008D - USB3 Port 1 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port1Pin; - - /** Offset 0x008E - USB3 Port 2 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port2Pin; - - /** Offset 0x008F - USB3 Port 3 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port3Pin; - - /** Offset 0x0090 - USB3 Port 4 OC Pin - Map selected OC pin to the port - 0:OC Pin 0, 8:No pin mapped - **/ - UINT8 PcdUsb3Port4Pin; - - /** Offset 0x0091 - IOxAPIC 0-199 - Enable/disable IOxAPIC 24-119 entries - $EN_DIS - **/ - UINT8 PcdIOxAPIC0_199; - - /** Offset 0x0092 - DMAP_X16 - Enable/Disable DMAP_X16 dynamic MRC field indicating memory device - width is x16 or not - $EN_DIS - **/ - UINT8 PcdDmapX16; - - /** Offset 0x0093 - **/ - UINT8 UnusedUpdSpace0[333]; - - /** Offset 0x01E0 - **/ - UINT8 ReservedMemoryInitUpd[16]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSPM_ARCH_UPD FspmArchUpd; - - /** Offset 0x0040 - **/ - FSP_M_CONFIG FspmConfig; - - /** Offset 0x01F0 - **/ - UINT8 UnusedUpdSpace1[14]; - - /** Offset 0x01FE - **/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h deleted file mode 100644 index f76f1a5..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h +++ /dev/null @@ -1,289 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - -/** Fsp S Configuration -**/ -typedef struct { - - /** Offset 0x0020 - PCIe Controller 0 Bifurcation - Configure PCI Express controller 0 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 - **/ - UINT8 PcdBifurcationPcie0; - - /** Offset 0x0021 - PCIe Controller 1 Bifurcation - Configure PCI Express controller 1 bifurcation. - 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 - **/ - UINT8 PcdBifurcationPcie1; - - /** Offset 0x0022 - Active Core Count - Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) - 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, - 12:12, 13:13, - 14:14, 15:15 - **/ - UINT8 PcdActiveCoreCount; - - /** Offset 0x0023 - **/ - UINT32 PcdCpuMicrocodePatchBase; - - /** Offset 0x0027 - **/ - UINT32 PcdCpuMicrocodePatchSize; - - /** Offset 0x002B - PCIe Controller 0 - Enable / Disable PCI Express controller 0 - $EN_DIS - **/ - UINT8 PcdEnablePcie0; - - /** Offset 0x002C - PCIe Controller 1 - Enable / Disable PCI Express controller 1 - $EN_DIS - **/ - UINT8 PcdEnablePcie1; - - /** Offset 0x002D - Embedded Multi-Media Controller (eMMC) - Enable / Disable Embedded Multi-Media controller - $EN_DIS - **/ - UINT8 PcdEnableEmmc; - - /** Offset 0x002E - LAN Controllers - Enable / Disable LAN controllers, refer to FSP Integration Guide for - details. - 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only - **/ - UINT8 PcdEnableGbE; - - /** Offset 0x002F - **/ - UINT32 PcdFiaMuxConfigRequestPtr; - - /** Offset 0x0033 - **/ - UINT8 UnusedUpdSpace0[4]; - - /** Offset 0x0037 - PCIe Root Port 0 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort0DeEmphasis; - - /** Offset 0x0038 - PCIe Root Port 1 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort1DeEmphasis; - - /** Offset 0x0039 - PCIe Root Port 2 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort2DeEmphasis; - - /** Offset 0x003A - PCIe Root Port 3 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort3DeEmphasis; - - /** Offset 0x003B - PCIe Root Port 4 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort4DeEmphasis; - - /** Offset 0x003C - PCIe Root Port 5 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort5DeEmphasis; - - /** Offset 0x003D - PCIe Root Port 6 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort6DeEmphasis; - - /** Offset 0x003E - PCIe Root Port 7 DeEmphasis - Desired DeEmphasis level for PCIE root port - 0:6dB, 1:3.5dB - **/ - UINT8 PcdPcieRootPort7DeEmphasis; - - /** Offset 0x003F - **/ - UINT8 UnusedUpdSpace1; - - /** Offset 0x0040 - **/ - UINT32 PcdEMMCDLLConfigPtr; - - /** Offset 0x0044 - PCIe Root Port 0 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort0LinkSpeed; - - /** Offset 0x0045 - PCIe Root Port 1 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort1LinkSpeed; - - /** Offset 0x0046 - PCIe Root Port 2 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort2LinkSpeed; - - /** Offset 0x0047 - PCIe Root Port 3 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort3LinkSpeed; - - /** Offset 0x0048 - PCIe Root Port 4 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort4LinkSpeed; - - /** Offset 0x0049 - PCIe Root Port 5 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort5LinkSpeed; - - /** Offset 0x004A - PCIe Root Port 6 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort6LinkSpeed; - - /** Offset 0x004B - PCIe Root Port 7 Link Speed - Upper limit on link operational speed for PCI Express RootPort - 1:GEN1, 2:GEN2, 3:GEN3 - **/ - UINT8 PcdPcieRootPort7LinkSpeed; - - /** Offset 0x004C - PCIe Root Port 0 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort0Aspm; - - /** Offset 0x004D - PCIe Root Port 1 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort1Aspm; - - /** Offset 0x004E - PCIe Root Port 2 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort2Aspm; - - /** Offset 0x004F - PCIe Root Port 3 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort3Aspm; - - /** Offset 0x0050 - PCIe Root Port 4 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort4Aspm; - - /** Offset 0x0051 - PCIe Root Port 5 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort5Aspm; - - /** Offset 0x0052 - PCIe Root Port 6 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort6Aspm; - - /** Offset 0x0053 - PCIe Root Port 7 ASPM - Enable PCI Express Active State Power Management settings - 0:Disabled, 2:L1 - **/ - UINT8 PcdPcieRootPort7Aspm; - - /** Offset 0x0054 - **/ - UINT8 UnusedUpdSpace2[140]; - - /** Offset 0x00E0 - **/ - UINT8 ReservedSiliconInitUpd[16]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSP_S_CONFIG FspsConfig; - - /** Offset 0x00F0 - **/ - UINT8 UnusedUpdSpace3[14]; - - /** Offset 0x00FE - **/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h deleted file mode 100644 index f06f72bd..0000000 --- a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h +++ /dev/null @@ -1,109 +0,0 @@ -/** @file - -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include <FspUpd.h> - -#pragma pack(1) - -/** Fsp T Core UPD -**/ -typedef struct { - - /** Offset 0x0020 - **/ - UINT32 MicrocodeRegionBase; - - /** Offset 0x0024 - **/ - UINT32 MicrocodeRegionLength; - - /** Offset 0x0028 - **/ - UINT32 CodeRegionBase; - - /** Offset 0x002C - **/ - UINT32 CodeRegionLength; - - /** Offset 0x0030 - **/ - UINT8 Reserved1[16]; -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { - - /** Offset 0x0040 - Disable Port80 output in FSP-T - Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, - 2:Disable Port80 - Output, refer to FSP Integration Guide for details - 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output - **/ - UINT8 PcdFsptPort80RouteDisable; - - /** Offset 0x0041 - **/ - UINT8 ReservedTempRamInitUpd[31]; -} FSPT_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - - /** Offset 0x0000 - **/ - FSP_UPD_HEADER FspUpdHeader; - - /** Offset 0x0020 - **/ - FSPT_CORE_UPD FsptCoreUpd; - - /** Offset 0x0040 - **/ - FSPT_CONFIG FsptConfig; - - /** Offset 0x0060 - **/ - UINT8 UnusedUpdSpace0[30]; - - /** Offset 0x007E - **/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Gerrit-Change-Number: 47754 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 20 Nov '20

20 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#59). Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... mb/kontron: Add Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/kontron/mal10.md A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc A src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt A src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c A src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h A src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/mal10/Makefile.inc A src/mainboard/kontron/mal10/variants/mal10/board_info.txt A src/mainboard/kontron/mal10/variants/mal10/data.vbt A src/mainboard/kontron/mal10/variants/mal10/devicetree.cb A src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/variants/mal10/gpio.c A src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h 26 files changed, 961 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/59 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 59 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/volteer: Use SoC header for TCSS port control
by Kevin Chang (Code Review) 20 Nov '20

20 Nov '20

Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47654 ) Change subject: mb/google/volteer: Use SoC header for TCSS port control ...................................................................... Patch Set 5: Hi Caveh Sorry for got the wrong rebase setting. I had fixed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/47654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ded34ad2316764ce42851b3d9b631ed5a30860e Gerrit-Change-Number: 47654 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 12:03:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation/releases: Update for 4.13
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47801 ) Change subject: Documentation/releases: Update for 4.13 ...................................................................... Documentation/releases: Update for 4.13 Fill in some blanks for 4.13, mark it done, add template for 4.14. Also update the list of vboot supported boards. Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/releases/coreboot-4.13-relnotes.md A Documentation/releases/coreboot-4.14-relnotes.md M Documentation/releases/index.md M Documentation/security/vboot/list_vboot.md 4 files changed, 69 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47801/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index a366d35..d86499e 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -1,14 +1,58 @@ -Upcoming release - coreboot 4.13 +coreboot 4.13 ================================ -The 4.13 release is planned for November 2020. +coreboot 4.13 was released on November 20th, 2020. -Update this document with changes that should be in the release notes. +Since 4.12 there were 4200 new commits by over 230 developers and of +these, <<TODO>> contributed for the first time, which is quite an amazing +increase. +Thank you to all developers who again helped made coreboot better +than ever, and a big welcome to our new contributors! -* Please use Markdown. -* See the past few release notes for the general format. -* The chip and board additions and removals will be updated right - before the release, so those do not need to be added. +New mainboards +-------------- + +- Acer G43T-AM3 +- AMD Cereme +- Asus A88XM-E FM2+ +- Biostar TH61-ITX +- BostenTech GBYT4 +- Clevo L140CU/L141CU +- Dell OptiPlex 9010 +- Google Asurada +- Google Boten +- Google Burnet +- Google Cerise +- Google Dauntless +- Google Drawcia +- Google Esche +- Google Fennel +- Google Hayato +- Google Pompom +- Google Shuboz +- Google Stern +- Google Terrador +- Google Vilboz +- Google Voema +- Google Voxel +- Google Willow +- Google Woomax +- Google Zork +- HP EliteBook Folio 9480m +- Intel ADLRVP +- Kontron bSL6 +- Prodrive Hermes +- Purism Librem Mini +- Purism Librem Mini v2 +- Siemens Chili +- Supermicro X11SSH-F +- system76 lemp9 + +Removed mainboards +------------------ + +- Google DragonEgg +- Google Sushi Significant changes ------------------- @@ -132,8 +176,6 @@ allocation above the 4G boundary. The old resource allocator v3 is still retained for some AMD platforms that do not conform to the requirements of the allocator. -### Add significant changes here - Deprecations ------------ diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md new file mode 100644 index 0000000..43a8d0d --- /dev/null +++ b/Documentation/releases/coreboot-4.14-relnotes.md @@ -0,0 +1,16 @@ +Upcoming release - coreboot 4.14 +================================ + +The 4.14 release is planned for May 2021. + +Update this document with changes that should be in the release notes. + +* Please use Markdown. +* See the past few release notes for the general format. +* The chip and board additions and removals will be updated right + before the release, so those do not need to be added. + +Significant changes +------------------- + +### Add significant changes here diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md index 0575e93..081d1fc 100644 --- a/Documentation/releases/index.md +++ b/Documentation/releases/index.md @@ -13,6 +13,7 @@ * [4.10 - July 2019](coreboot-4.10-relnotes.md) * [4.11 - November 2019](coreboot-4.11-relnotes.md) * [4.12 - May 2020](coreboot-4.12-relnotes.md) +* [4.13 - November 2020](coreboot-4.13-relnotes.md) The checklist contains instructions to ensure that a release covers all important things and provides a reliable format for tarballs, branch @@ -24,4 +25,4 @@ ---------------- Please add to the release notes as changes are added: -* [4.13 - November 2020](coreboot-4.13-relnotes.md) +* [4.14 - May 2021](coreboot-4.14-relnotes.md) diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index c0ccfce..dd8bae8 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -34,7 +34,6 @@ - Daisy (Samsung Chromebook (2012)) - Deltan - Deltaur -- DragonEgg - Drallion - Eve (Google Pixelbook) - Fizz @@ -70,7 +69,6 @@ - Puff - Helios_Diskswap - Stryke -- Sushi - Guado (ASUS Chromebox CN62) - Jecht - Rikku (Acer Chromebox CXI2) -- To view, visit https://review.coreboot.org/c/coreboot/+/47801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b Gerrit-Change-Number: 47801 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/clevo/kbl-u: Add Clevo N130WU/N131WU
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/kbl-u: Add Clevo N130WU/N131WU ...................................................................... Patch Set 149: (1 comment) https://review.coreboot.org/c/coreboot/+/28640/149/Documentation/mainboard/… File Documentation/mainboard/clevo/n130wu/index.md: https://review.coreboot.org/c/coreboot/+/28640/149/Documentation/mainboard/… PS149, Line 41: ### Working : ### Not Working : ### Work in progress : ### Untested Shouldn't this not be empty? -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 149 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-Comment-Date: Fri, 20 Nov 2020 12:00:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1
by Kevin Chang (Code Review) 20 Nov '20

20 Nov '20

Kevin Chang has uploaded a new patch set (#10) to the change originally created by Caveh Jalali. ( https://review.coreboot.org/c/coreboot/+/47501 ) Change subject: mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 ...................................................................... mb/google/volteer/v/volteer2: Add config for passive USB-C DB on C1 This enables support for a passive USB-C daughterboard on volteer. This board has no retimers or redrivers which makes it functionally very similar to the USB-C port on the MLB. Since there is no external logic, all mux-ing happens in the TCSS. Also, the AUX DC biasing is controlled by SoC GPIO pins which must also be explicitly enabled. BRANCH=volteer BUG=b:163476857 TEST=verified external USB-C monitor shows up in both cable orientations Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/volteer/variants/volteer2/Makefile.inc M src/mainboard/google/volteer/variants/volteer2/gpio.c A src/mainboard/google/volteer/variants/volteer2/variant.c 7 files changed, 62 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47501/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/47501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9939450213bac4c0d661759bef2f38f3fd3af76 Gerrit-Change-Number: 47501 Gerrit-PatchSet: 10 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/clevo/kbl-u: Add Clevo N130WU/N131WU
by Michael Niewöhner (Code Review) 20 Nov '20

20 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/28640 ) Change subject: mb/clevo/kbl-u: Add Clevo N130WU/N131WU ...................................................................... mb/clevo/kbl-u: Add Clevo N130WU/N131WU Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A Documentation/mainboard/clevo/n130wu/index.md M Documentation/mainboard/index.md A src/mainboard/clevo/kbl-u/Kconfig A src/mainboard/clevo/kbl-u/Kconfig.name A src/mainboard/clevo/kbl-u/Makefile.inc A src/mainboard/clevo/kbl-u/acpi/ec.asl A src/mainboard/clevo/kbl-u/acpi/superio.asl A src/mainboard/clevo/kbl-u/board_info.txt A src/mainboard/clevo/kbl-u/bootblock.c A src/mainboard/clevo/kbl-u/dsdt.asl A src/mainboard/clevo/kbl-u/include/mainboard/gpio.h A src/mainboard/clevo/kbl-u/ramstage.c A src/mainboard/clevo/kbl-u/romstage.c A src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt A src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt A src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb A src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd A src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads A src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c A src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c A src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c 21 files changed, 1,045 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md new file mode 100644 index 0000000..3267561 --- /dev/null +++ b/Documentation/mainboard/clevo/n130wu/index.md @@ -0,0 +1,47 @@ +# Clevo N130WU + +## Hardware +### Technology +```eval_rst ++------------------+--------------------------------+ +| CPU | Intel i7-8550U | ++------------------+--------------------------------+ +| PCH | Intel Sunrise Point LP | ++------------------+--------------------------------+ +| EC / Super IO | ITE IT8587E | ++------------------+--------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------+ +``` + +### Flash chip +```eval_rst ++---------------------+-----------------+ +| Type | Value | ++=====================+=================+ +| Model | GD25Q64B | ++---------------------+-----------------+ +| Socketed flash | no | ++---------------------+-----------------+ +| Size | 8 MiB | ++---------------------+-----------------+ +| In circuit flashing | Yes | ++---------------------+-----------------+ +| Package | SOIC-8 | ++---------------------+-----------------+ +| Write protection | No | ++---------------------+-----------------+ +| Dual BIOS feature | No | ++---------------------+-----------------+ +| Internal flashing | Yes | ++---------------------+-----------------+ +``` + +## Board status +### Working +### Not Working +### Work in progress +### Untested + +## Also known as +* TUXEDO InfinityBook Pro 13 v3 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4a1f74b..d6aed22 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -26,6 +26,10 @@ - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Clevo + +- [N130WU / N131WU](clevo/n130wu/index.md) + ## Dell - [OptiPlex 9010 SFF](dell/optiplex_9010.md) diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig new file mode 100644 index 0000000..ed0600a --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_CLEVO_N130WU + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES +# select HAVE_CMOS_DEFAULT +# select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config MAINBOARD_DIR + string + default "clevo/kbl-u" + +config VARIANT_DIR + string + default "n13xwu" if BOARD_CLEVO_N130WU + +config MAINBOARD_PART_NUMBER + string + default "N130WU" if BOARD_CLEVO_N130WU + +config CBFS_SIZE + hex + default 0x600000 if BOARD_CLEVO_N130WU + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd" if VBOOT && !VBOOT_SLOTS_RW_A + # TODO +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB +# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,5917" if BOARD_CLEVO_N130WU + +config PXE_ROM_ID + string + default "10ec,8168" + +config UART_FOR_CONSOLE + int + default 2 + +config POST_DEVICE + bool + default n + +config CONSOLE_POST + bool + default y + +config LINEAR_FRAMEBUFFER_MAX_WIDTH + int + default 1920 + +config LINEAR_FRAMEBUFFER_MAX_HEIGHT + int + default 1080 + +endif diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name new file mode 100644 index 0000000..5a6f699c --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Kconfig.name @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +comment "Kaby Lake U" + +config BOARD_CLEVO_N130WU + bool "N130WU / N131WU" diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc new file mode 100644 index 0000000..b424d4d --- /dev/null +++ b/src/mainboard/clevo/kbl-u/Makefile.inc @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/clevo/kbl-u/acpi/ec.asl b/src/mainboard/clevo/kbl-u/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/ec.asl diff --git a/src/mainboard/clevo/kbl-u/acpi/superio.asl b/src/mainboard/clevo/kbl-u/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/clevo/kbl-u/board_info.txt b/src/mainboard/clevo/kbl-u/board_info.txt new file mode 100644 index 0000000..97514fc --- /dev/null +++ b/src/mainboard/clevo/kbl-u/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Clevo +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/kbl-u/bootblock.c b/src/mainboard/clevo/kbl-u/bootblock.c new file mode 100644 index 0000000..067c9ec --- /dev/null +++ b/src/mainboard/clevo/kbl-u/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_gpios(); +} diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl new file mode 100644 index 0000000..21acf37 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/dsdt.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h new file mode 100644 index 0000000..ef2a21c --- /dev/null +++ b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c new file mode 100644 index 0000000..b5d6786 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/ramstage.h> + +/* + * TODO: + * - Add kill switches for WLAN, BT, LTE, CCD + * - Add support for WoL (LAN, WLAN) + * - Make M.2 port configurable (SATA <> PCIe) + * - Make SATA DevSlp configurable + * - Make TBT port configurable (TBT <> DisplayPort) + */ + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + mainboard_configure_gpios(); +} diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c new file mode 100644 index 0000000..1399d33 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt new file mode 100644 index 0000000..30f8ce6 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt @@ -0,0 +1 @@ +Board name: N130WU / N131WU diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt new file mode 100644 index 0000000..f88aef4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt Binary files differ diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb new file mode 100644 index 0000000..55c5a69 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" # T3 + register "gpu_pp_down_delay_ms" = " 0" # T10 + register "gpu_pp_cycle_delay_ms" = "500" # T12 + register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 + register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 + + register "gpu_pch_backlight_pwm_hz" = "200" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # FSP Configuration + register "SkipExtGfxScan" = "1" + register "SaGv" = "SaGv_Enabled" + register "eist_enable" = "1" + + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + register "power_limits_config" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 30, + }" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1558 0x1313 inherit + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA thermal subsystem + device pci 05.0 off end # Imaging Unit + device pci 08.0 on end # Gaussian Mixture Model + device pci 13.0 off end # Sensor Hub + device pci 14.0 on # USB xHCI + register "SsicPortEnable" = "0" + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 14.3 off end # Camera + device pci 15.0 off end # I2C0 + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "0" + # Ports + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 19.0 on end # UART 2 + device pci 19.1 off end # I2C5 + device pci 19.2 off end # I2C4 + device pci 1c.0 on # PCI Express Port 1 + device pci 00.0 on end # x4 TBT + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on # PCI Express Port 5 + device pci 00.0 on end # x1 LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpLtrEnable[4]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 WLAN + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpLtrEnable[5]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M (J_SSD1) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpLtrEnable[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDXC + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 on # Power Management Controller + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + end + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # Trace Hub + end +end diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd new file mode 100644 index 0000000..f53cdf4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd @@ -0,0 +1,32 @@ +FLASH 8M { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x2d000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_SHARED@0x21000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x25000 0x2000 + RW_NVRAM(PRESERVE)@0x27000 0x5000 + FPF_STATUS@0x2c000 0x1000 + } + WP_RO@0x2d000 0x5d3000 { + FMAP@0x0 0x800 + RO_VPD(PRESERVE)@0x800 0x4000 + RO_SECTION@0x4800 0x5ce800 { + RO_FRID@0x0 0x40 + RO_FRID_PAD@0x40 0x7c0 + GBB@0x800 0x40000 + COREBOOT(CBFS)@0x40800 0x58e000 + } + } + } +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads new file mode 100644 index 0000000..38abb7a --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads @@ -0,0 +1,21 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c new file mode 100644 index 0000000..e7aadcc --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c @@ -0,0 +1,503 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + // RCIN# + _PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0), + + // LAD0 + _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0), + + // LAD1 + _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0), + + // LAD2 + _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0), + + // LAD3 + _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0), + + // LFRAME# + _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0), + + // SERIRQ + _PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0), + + // PIRQA# + _PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0), + + // CLKRUN# + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + + // CLKOUT_LPC0 + _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0), + + // CLKOUT_LPC1 + _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000), + + // PME# + _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), + + // BM_BUSY# + _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0), + + // SUSWARN#/SUSPWRDNACK + _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0), + + // SUS_STAT#/ESPI_RESET# + _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0), + + // SUS_ACK# + _PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0), + + // SD_1P8_SEL + _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0), + + // SD_PWR_EN# + _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0), + + // ISH_GP0 + _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0), + + // ISH_GP1 + _PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0), + + // ISH_GP2 + _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0), + + // ISH_GP3 + _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000), + + // ISH_GP4 + _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0), + + // ISH_GP5 + _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0), + + // CORE_VID0 + _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), + + // CORE_VID1 + _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), + + // VRALERT# + _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0), + + // CPU_GP2 + _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0), + + // CPU_GP3 + _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0), + + // SRCCLKREQ0# + _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0), + + // SRCCLKREQ1# + _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0), + + // SRCCLKREQ2# + _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0), + + // SRCCLKREQ3# + _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0), + + // SRCCLKREQ4# + _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0), + + // SRCCLKREQ5# + _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0), + + // EXT_PWR_GATE# + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + + // SLP_S0# + _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0), + + // PLTRST# + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + + // SPKR + _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000), + + // GSPI0_CS# + _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0), + + // GSPI0_CLK + _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0), + + // GSPI0_MISO + _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0), + + // GSPI0_MOSI + _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000), + + // GSPI1_CS# + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + + // GSPI1_CLK + _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0), + + // GSPI1_MISO + _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0), + + // GSPI1_MOSI + _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), + + // SML1ALERT#/PCHHOT# + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + + // SMBCLK + _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), + + // SMBDATA + _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), + + // SMBALERT# + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), + + // SML0CLK + _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0), + + // SML0DATA + _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0), + + // SML0ALERT# + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + + // SML1CLK +// _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), + + // SML1DATA +// _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), + + // UART0_RXD + _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0), + + // UART0_TXD + _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), + + // UART0_RTS# + _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), + + // UART0_CTS# + _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0), + + // UART1_RXD + _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), + + // UART1_TXD + _PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0), + + // UART1_RTS# + _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), + + // UART1_CTS# + _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0), + + // I2C0_SDA + _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0), + + // I2C0_SCL + _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0), + + // I2C1_SDA + _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0), + + // I2C1_SCL + _PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0), + + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), + + // UART2_RTS# + _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), + + // UART2_CTS# + _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0), + + // SPI1_CS# + _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0), + + // SPI1_CLK + _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0), + + // SPI1_MISO + _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0), + + // SPI1_MOSI + _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0), + + // FLASHTRIG + _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0), + + // ISH_I2C0_SDA + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0), + + // ISH_I2C0_SCL + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0), + + // ISH_I2C1_SDA + _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0), + + // ISH_I2C1_SCL + _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0), + + // ISH_UART0_RXD + _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0), + + // ISH_UART0_TXD + _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0), + + // ISH_UART0_RTS# + _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), + + // ISH_UART0_CTS# + _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0), + + // DMIC_CLK1 + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), + + // DMIC_DATA1 + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0), + + // DMIC_CLK0 + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), + + // DMIC_DATA0 + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0), + + // SPI1_IO2 + _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0), + + // SPI1_IO3 + _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), + + // I2S_MCLK + _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), + + // SATAXPCIE0/SATAGP0 + _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000), + + // SATAXPCIE1/SATAGP1 + _PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0), + + // SATAXPCIE2/SATAGP2 + _PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0), + + // CPU_GP0 + _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0), + + // DEVSLP0 + _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0), + + // DEVSLP1 + _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), + + // DEVSLP2 + _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0), + + // CPU_GP1 + _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0), + + // SATALED# + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + + // USB2_OC0# + _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0), + + // USB2_OC1# + _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0), + + // USB2_OC2# + _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0), + + // USB2_OC3# + _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0), + + // DDPB_HPD0 + _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), + + // DDPC_HPD1 + _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), + + // DDPD_HPD2 + _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0), + + // DDPE_HPD3 + _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0), + + // EDP_HPD + _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), + + // DDPB_CTRLCLK + _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0), + + // DDPB_CTRLDATA + _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), + + // DDPC_CTRLCLK + _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0), + + // DDPC_CTRLDATA + _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), + + // DDPD_CTRLCLK + _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0), + + // DDPD_CTRLDATA + _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), + + // BATLOW# + _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0), + + // LAN_WAKE# + _PAD_CFG_STRUCT(GPD2, 0x880502, 0x0), + + // PWRBTN# + _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), + + // SLP_S3# + _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), + + // SLP_S4# + _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), + + // SLP_A# + _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), + + // RSVD + _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), + + // SUSCLK + _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), + + // SLP_WLAN# + _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), + + // SLP_S5# + _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), + + // LANPHYPC + _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0), + + // I2S2_SCLK + _PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0), + + // I2S2_SFRM + _PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0), + + // I2S2_TXD + _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), + + // I2S2_RXD + _PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0), + + // I2C2_SDA + _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000), + + // I2C2_SCL + _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000), + + // I2C3_SDA + _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000), + + // I2C3_SCL + _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000), + + // I2C4_SDA + _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000), + + // I2C4_SCL + _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000), + + // I2C5_SDA/ISH_I2C2_SDA + _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000), + + // I2C5_SCL/ISH_I2C2_SCL + _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000), + + // EMMC_CMD + _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0), + + // EMMC_DATA0 + _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0), + + // EMMC_DATA1 + _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0), + + // EMMC_DATA2 + _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0), + + // EMMC_DATA3 + _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0), + + // EMMC_DATA4 + _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0), + + // EMMC_DATA5 + _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0), + + // EMMC_DATA6 + _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0), + + // EMMC_DATA7 + _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0), + + // EMMC_RCLK + _PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0), + + // EMMC_CLK + _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), + + // GPIO + _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0), + + // SD_CMD + _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), + + // SD_DATA0 + _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0), + + // SD_DATA1 + _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), + + // SD_DATA2 + _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), + + // SD_DATA3 + _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), + + // SD_CD# + _PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), + + // SD_CLK + _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), + + // SD_WP + _PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0) +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c new file mode 100644 index 0000000..00246a4 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + // UART2_RXD + _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0), + + // UART2_TXD + _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0) +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c new file mode 100644 index 0000000..05bb273 --- /dev/null +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC269VC */ + 0x10ec0269, + 0x15581314, + 11, + AZALIA_SUBVENDOR(0, 0x15581314), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Intel iGPU HDMI */ + 0x8086280b, + 0x80860101, + 4, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x5, 0x18560010), + AZALIA_PIN_CFG(2, 0x6, 0x18560010), + AZALIA_PIN_CFG(2, 0x7, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/28640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Gerrit-Change-Number: 28640 Gerrit-PatchSet: 150 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Shaleen jain <shaleen(a)jain.sh> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47538 ) Change subject: soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER ...................................................................... soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER The PCH IOAPIC is not PCI discoverable. Linux checks the BDF set in DMAR against the PCI class if it is a PIC, which 00:1F.0 for instance isn't. The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR 3, MINOR 7 if the BUS number is 0. Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47538/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 33e257c..22ef4ab 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -111,7 +111,7 @@ #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00 -#define PCH_IOAPIC_BUS_NUMBER 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 #define PCH_IOAPIC_DEV_NUM 0x1F #define PCH_IOAPIC_FUNC_NUM 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/47538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0 Gerrit-Change-Number: 47538 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47537 ) Change subject: soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF ...................................................................... soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes coreboot in control of these settings. Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/p2sb/Makefile.inc M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/pch.c M src/soc/intel/xeon_sp/skx/chip.c 6 files changed, 27 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47537/1 diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index a1330ab..d557e36 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index a10075a..2e50e64 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -9,7 +9,7 @@ romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c -ramstage-y += memmap.c +ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3daff13..7ca40e3 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -11,6 +11,7 @@ #include <soc/chip_common.h> #include <soc/cpu.h> #include <soc/ramstage.h> +#include <soc/pch.h> #include <soc/soc_util.h> #include <soc/util.h> @@ -72,6 +73,7 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); + override_hpet_ioapic_bdf(); pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h index 84d5e48..0be14ae 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch.h +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -9,4 +9,6 @@ void pch_disable_devfn(struct device *dev); #endif +void override_hpet_ioapic_bdf(void); + #endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5427952..8d28592 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -5,7 +5,9 @@ #include <soc/pcr_ids.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/p2sb.h> #include <soc/bootblock.h> +#include <soc/pch.h> #include <soc/pmc.h> #include <console/console.h> @@ -48,3 +50,20 @@ */ soc_config_acpibase(); } + +void override_hpet_ioapic_bdf(void) +{ + union p2sb_bdf ioapic_bdf = { + .bus = PCH_IOAPIC_BUS_NUMBER, + .dev = PCH_IOAPIC_DEV_NUM, + .fn = PCH_IOAPIC_FUNC_NUM, + }; + union p2sb_bdf hpet_bdf = { + .bus = HPET_BUS_NUM, + .dev = HPET_DEV_NUM, + .fn = HPET0_FUNC_NUM, + }; + + p2sb_set_ioapic_bdf(ioapic_bdf); + p2sb_set_hpet_bdf(hpet_bdf); +} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index a345c3e..0b57d20 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -6,6 +6,7 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/ramstage.h> +#include <soc/pch.h> #include <soc/soc_util.h> #include <soc/util.h> @@ -43,6 +44,7 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); + override_hpet_ioapic_bdf(); } static void soc_final(void *data) -- To view, visit https://review.coreboot.org/c/coreboot/+/47537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf Gerrit-Change-Number: 47537 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPIC
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47536 ) Change subject: soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPIC ...................................................................... soc/intel/xeon_sp: Use common P2SB functions to generate HPET IOAPIC Change-Id: I700df8fe5243db46fa8458757b4e5596c4b9f404 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47536/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index f4d9da3..c75a2f2 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -214,12 +214,12 @@ // Add PCH IOAPIC if (socket == 0 && stack == CSTACK) { + union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", - PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, - PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + PCH_IOAPIC_ID, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, - PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); } // Add IOAPIC entry -- To view, visit https://review.coreboot.org/c/coreboot/+/47536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700df8fe5243db46fa8458757b4e5596c4b9f404 Gerrit-Change-Number: 47536 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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