coreboot-gerrit November 2020

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Change in coreboot[master]: soc/mediatek/mt8192: Add auxadc driver
by Yidi Lin (Code Review) 20 Nov '20

20 Nov '20

Hello Po Xu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46390 to review the following change. Change subject: soc/mediatek/mt8192: Add auxadc driver ...................................................................... soc/mediatek/mt8192: Add auxadc driver Add MT8192 auxadc driver. Signed-off-by: Po Xu <jg_poxu(a)mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/auxadc.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/auxadc.h A src/soc/mediatek/mt8192/include/soc/efuse.h 5 files changed, 116 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46390/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d417ae2..9bb9cfd 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) +bootblock-y += auxadc.c bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -13,12 +14,14 @@ bootblock-y += mt6315.c bootblock-y += mt6359p.c +verstage-y += auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c +romstage-y += auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c @@ -29,6 +32,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c +ramstage-y += auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/auxadc.c b/src/soc/mediatek/mt8192/auxadc.c new file mode 100755 index 0000000..3f9238b --- /dev/null +++ b/src/soc/mediatek/mt8192/auxadc.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <assert.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/auxadc.h> +#include <soc/efuse.h> +#include <soc/infracfg.h> +#include <timer.h> + +static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; + +#define ADC_GE_A_SHIFT 10 +#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT) +#define ADC_OE_A_SHIFT 0 +#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT) +#define ADC_CALI_EN_A_SHIFT 20 +#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT) + +static int cali_oe; +static int cali_ge; +static int calibrated = 0; +static void mt_auxadc_update_cali(void) +{ + uint32_t cali_reg; + int cali_ge_a; + int cali_oe_a; + + cali_reg = read32(&mtk_efuse->adc_cali_reg); + + if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) { + cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT; + cali_ge_a = (cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT; + cali_ge = cali_ge_a - 512; + cali_oe = cali_oe_a - 512; + } +} +static uint32_t auxadc_get_rawdata(int channel) +{ + setbits32(&mt8192_infracfg->module_sw_cg_1_clr, 1 << 10); + assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); + + clrbits32(&mtk_auxadc->con1, 1 << channel); + assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); + + setbits32(&mtk_auxadc->con1, 1 << channel); + udelay(25); + assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); + + uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; + + setbits32(&mt8192_infracfg->module_sw_cg_1_set, 1 << 10); + + return value; +} + +int auxadc_get_voltage(unsigned int channel) +{ + uint32_t raw_value; + assert(channel < 16); + + if (!calibrated) { + mt_auxadc_update_cali(); + calibrated = 1; + } + + /* 1.5V in 4096 steps */ + raw_value = auxadc_get_rawdata(channel); + raw_value = raw_value - cali_oe; + return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge)); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100644 new mode 100755 index e9cb788..9760c88 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -26,6 +26,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, @@ -37,6 +38,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h new file mode 100755 index 0000000..18350d6 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +/* Return voltage in uVolt */ +int auxadc_get_voltage(unsigned int channel); +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h new file mode 100755 index 0000000..f0f3405 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Gerrit-Change-Number: 46390 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Po Xu <jg_poxu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/google/chromesos/sar: Reduce severity of debug message
by Maulik V Vaghela (Code Review) 20 Nov '20

20 Nov '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47442 ) Change subject: vendorcode/google/chromesos/sar: Reduce severity of debug message ...................................................................... vendorcode/google/chromesos/sar: Reduce severity of debug message Coreboot might not store wifi SAR values in VPD and may store it in CBFS. Logging the debug message with 'error' severity may interfere with automated test tool. Lowering severity to BIOS_DEBUG to avoid this issue BUG=b:171931401 BRANCH=None TEST=Severity of message is reduced and we don't see it as an error Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/vendorcode/google/chromeos/sar.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47442/1 diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index 2f73d39..9bca423 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -71,7 +71,7 @@ /* Try to read the SAR limit entry from VPD */ if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, buffer_size, VPD_RO_THEN_RW)) { - printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", + printk(BIOS_DEBUG, "Could not locate '%s' in VPD.\n", wifi_sar_limit_key); if (!CONFIG(WIFI_SAR_CBFS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/47442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba Gerrit-Change-Number: 47442 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Zhuohao Lee (Code Review) 20 Nov '20

20 Nov '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47736 ) Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 06:49:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Frank Chu (Code Review) 20 Nov '20

20 Nov '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47736 ) Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47736/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47736/2//COMMIT_MSG@7 PS2, Line 7: mb/google/volteer/variants/delbin: I2C5 trackpad bus freq 400 kHz > Please make it a statement by adding a verb in imperative mood. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 06:00:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz
by Frank Chu (Code Review) 20 Nov '20

20 Nov '20

Hello build bot (Jenkins), Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47736 to look at the new patch set (#3). Change subject: mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz ...................................................................... mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47736/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Gerrit-Change-Number: 47736 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/sandybridge: Program MR2 shadow register
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47567 ) Change subject: nb/intel/sandybridge: Program MR2 shadow register ...................................................................... nb/intel/sandybridge: Program MR2 shadow register This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands. Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47567/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4bdb82d..095d853 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -785,6 +785,22 @@ mr2reg |= (odt.rttwr / 60) << 9; write_mrreg(ctrl, channel, rank, 2, mr2reg); + + /* Program MR2 shadow */ + u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); + + reg32 &= 3 << 14 | 3 << 6; + + reg32 |= mr2reg & ~(3 << 6); + + if (rank & 1) { + if (srt) + reg32 |= 1 << (rank / 2 + 6); + } else { + if (ctrl->rank_mirror[channel][rank]) + reg32 |= 1 << (rank / 2 + 14); + } + MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; } static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) -- To view, visit https://review.coreboot.org/c/coreboot/+/47567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Gerrit-Change-Number: 47567 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Generate ACPI CRAT objects in cb
by Felix Held (Code Review) 20 Nov '20

20 Nov '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47727 ) Change subject: soc/amd/picasso: Generate ACPI CRAT objects in cb ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47727/3/src/include/acpi/acpi.h File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/47727/3/src/include/acpi/acpi.h@311 PS3, Line 311: struct acpi_crat_header > Maybe typedef this, like on line 303. […] not using typedefs here might not be completely consistent, but is the better option in the long run; see also https://doc.coreboot.org/coding_style.html#typedefs on that -- To view, visit https://review.coreboot.org/c/coreboot/+/47727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Gerrit-Change-Number: 47727 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 20 Nov 2020 01:17:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMem...
by Tim Chu (Code Review) 20 Nov '20

20 Nov '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47505 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob ...................................................................... vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob This field from SystemMemoryMapHob can be used to define error correction type in SMBIOS type 16. Tested=On OCP Delta Lake, the value is expected. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index dc870f1..9f37459 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -143,21 +143,23 @@ UINT8 reserved2[22]; UINT8 DdrVoltage; - UINT8 reserved3[38]; + UINT8 reserved3[33]; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 reserved4[4]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved4[2213]; + UINT8 reserved5[2213]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved5[1603]; + UINT8 reserved6[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved6[24]; + UINT8 reserved7[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved7[5]; + UINT8 reserved8[5]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/47505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf Gerrit-Change-Number: 47505 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Lock down P2SB SBI
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46499 ) Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ...................................................................... soc/intel/xeon_sp/cpx: Lock down P2SB SBI This is required for CBnT. Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46499 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/p2sb.h 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 3daff13..b7752b2 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -11,8 +11,10 @@ #include <soc/chip_common.h> #include <soc/cpu.h> #include <soc/ramstage.h> +#include <soc/p2sb.h> #include <soc/soc_util.h> #include <soc/util.h> +#include <soc/pci_devs.h> /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) @@ -63,6 +65,8 @@ static void chip_final(void *data) { + /* Lock SBI */ + pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); p2sb_hide(); set_bios_init_completion(); diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h index 336befe..3bdd453 100644 --- a/src/soc/intel/xeon_sp/include/soc/p2sb.h +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -11,3 +11,6 @@ #define HPTC_ADDR_ENABLE_BIT (1 << 7) #define PCH_P2SB_EPMASK0 0xb0 #define P2SB_SIZE (16 * MiB) + +#define P2SBC 0xe0 +#define SBILOCK (1 << 31) -- To view, visit https://review.coreboot.org/c/coreboot/+/46499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Gerrit-Change-Number: 46499 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Lock down P2SB SBI
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46499 ) Change subject: soc/intel/xeon_sp/cpx: Lock down P2SB SBI ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08 Gerrit-Change-Number: 46499 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 00:46:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020