coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: zork: Create gumboz variant
by Kevin Chiu (Code Review) 21 Nov '20

21 Nov '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47717 to review the following change. Change subject: zork: Create gumboz variant ...................................................................... zork: Create gumboz variant Create the gumboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:173536689 BRANCH=zork TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_GUMBOZ Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/Kconfig.name A src/mainboard/google/zork/variants/gumboz/Makefile.inc A src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl A src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl A src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl A src/mainboard/google/zork/variants/gumboz/include/variant/ec.h A src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h A src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h A src/mainboard/google/zork/variants/gumboz/overridetree.cb A src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc A src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt A src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt 13 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47717/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a0606cc..36824e6 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -72,6 +72,7 @@ default "woomax" if BOARD_GOOGLE_WOOMAX default "dirinboz" if BOARD_GOOGLE_DIRINBOZ default "shuboz" if BOARD_GOOGLE_SHUBOZ + default "gumboz" if BOARD_GOOGLE_GUMBOZ config MAINBOARD_PART_NUMBER string @@ -84,6 +85,7 @@ default "Woomax" if BOARD_GOOGLE_WOOMAX default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ default "Shuboz" if BOARD_GOOGLE_SHUBOZ + default "Gumboz" if BOARD_GOOGLE_GUMBOZ config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 8ed43f0..6c6657c 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -35,3 +35,7 @@ config BOARD_GOOGLE_SHUBOZ bool "-> Shuboz" select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_GUMBOZ + bool "-> Gumboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/variants/gumboz/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/Makefile.inc new file mode 100644 index 0000000..295acd2 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000..900e36f --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..a1161ed --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..7a793d8 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h new file mode 100644 index 0000000..2af6479 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb new file mode 100644 index 0000000..1cc2364 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + # I2C3 for H1 + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + end # device + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc new file mode 100644 index 0000000..3edeb96 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt new file mode 100644 index 0000000..106a705 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) -- To view, visit https://review.coreboot.org/c/coreboot/+/47717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Gerrit-Change-Number: 47717 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/zork: update DRAM table for dirinboz
by Kevin Chiu (Code Review) 21 Nov '20

21 Nov '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47700 to review the following change. Change subject: mb/google/zork: update DRAM table for dirinboz ...................................................................... mb/google/zork: update DRAM table for dirinboz Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:173480390 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc M src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47700/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc index 5e09836..6d8a906 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt index 8c8ee39..d6d5d09 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt @@ -7,3 +7,4 @@ MT40A1G16KD-062E:E 8 (1000) K4AAG165WA-BCTD 9 (1001) K4AAG165WA-BCWE 10 (1010) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt index ba70da3..5a6541f 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -15,3 +15,4 @@ MT40A1G16KD-062E:E, 8 K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 +H5ANAG6NCJR-XNC -- To view, visit https://review.coreboot.org/c/coreboot/+/47700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Gerrit-Change-Number: 47700 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: util: Add new DDR4 H5ANAG6NCJR-XNC for zork boards
by Kevin Chiu (Code Review) 21 Nov '20

21 Nov '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47698 to review the following change. Change subject: util: Add new DDR4 H5ANAG6NCJR-XNC for zork boards ...................................................................... util: Add new DDR4 H5ANAG6NCJR-XNC for zork boards Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=None TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- A src/mainboard/google/zork/spd/ddr4-spd-9.hex M src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47698/1 diff --git a/src/mainboard/google/zork/spd/ddr4-spd-9.hex b/src/mainboard/google/zork/spd/ddr4-spd-9.hex new file mode 100644 index 0000000..1ce7c21 --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 202f173..21565c6 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -13,3 +13,4 @@ H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex -- To view, visit https://review.coreboot.org/c/coreboot/+/47698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Gerrit-Change-Number: 47698 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/zork: update telemetry settings for Woomax
by Kane Chen (Code Review) 21 Nov '20

21 Nov '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47743 ) Change subject: mb/google/zork: update telemetry settings for Woomax ...................................................................... mb/google/zork: update telemetry settings for Woomax Update Woomax to improve the performance. BUG=b:168073070 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b --- M src/mainboard/google/zork/variants/woomax/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/47743/1 diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index abbdd92..5a2bc99 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -16,9 +16,9 @@ register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope_mA" = "102586" + register "telemetry_vddcr_vdd_slope_mA" = "101070" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope_mA" = "26967" + register "telemetry_vddcr_soc_slope_mA" = "24560" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/47743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b Gerrit-Change-Number: 47743 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: include/devices/pci_ids: add IDs for new AMD SoCs
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47703 ) Change subject: include/devices/pci_ids: add IDs for new AMD SoCs ...................................................................... include/devices/pci_ids: add IDs for new AMD SoCs Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/device/pci_ids.h 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47703/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5095f11..10abdf7 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -301,11 +301,13 @@ #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 @@ -454,13 +456,17 @@ #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_1 0x1633 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_2 0x1634 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA @@ -468,6 +474,22 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670 +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1617 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 @@ -476,9 +498,15 @@ #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 +#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C +#define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU 0x1638 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_HDA0 0x1637 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 -- To view, visit https://review.coreboot.org/c/coreboot/+/47703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b Gerrit-Change-Number: 47703 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10
by John Su (Code Review) 21 Nov '20

21 Nov '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47691 ) Change subject: mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10 ...................................................................... mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10 Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC) activation. BUG=b:171531244 TEST=build and verify by thermal team Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c --- M src/mainboard/google/dedede/variants/madoo/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47691/1 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 1be1012..1bf90e7 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -59,7 +59,7 @@ .tdp_pl2_override = 20, }" - register "tcc_offset" = "5" # TCC of 95C + register "tcc_offset" = "10" # TCC of 90C device domain 0 on device pci 04.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/47691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c Gerrit-Change-Number: 47691 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: nb/intel/sandybridge: Rename loop variable
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47606 ) Change subject: nb/intel/sandybridge: Rename loop variable ...................................................................... nb/intel/sandybridge: Rename loop variable What `discover_edges_real` is shmooing is the DQS PI setting. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47606/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 257eae4..e740f55 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2345,14 +2345,14 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { - int edge; + int dqs_pi; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; int lane; - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { + for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = edge; - ctrl->timings[channel][slotrank].lanes[lane].falling = edge; + ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; + ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; } program_timings(ctrl, channel); @@ -2372,7 +2372,7 @@ wait_for_iosav(channel); FOR_ALL_LANES { - stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Gerrit-Change-Number: 47606 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... Patch Set 59: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 59 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 20 Nov 2020 21:22:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Generate ACPI CRAT objects in cb
by Angel Pons (Code Review) 20 Nov '20

20 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47727 ) Change subject: soc/amd/picasso: Generate ACPI CRAT objects in cb ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47727/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47727/3//COMMIT_MSG@15 PS3, Line 15: FPS FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/47727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Gerrit-Change-Number: 47727 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 20 Nov 2020 21:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork: Remove 50ms WIFI delay
by Martin Roth (Code Review) 20 Nov '20

20 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47719 ) Change subject: mb/google/zork: Remove 50ms WIFI delay ...................................................................... mb/google/zork: Remove 50ms WIFI delay As a part of trying to get our boot time as low as possible, any delays in the code should try to be refactored out. This removes the 50ms delay in the WIFI sequence by enabling power and putting the wifi module into reset in bootblock, then bringing it out of reset in ramstage. This is significantly longer than the 50ms requirement. The reset GPIO was already being set high in ramstage, so that code didn't need to be added. BUG=b:171513520 TEST=Boot on boards with different module types, WIFI works on both. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/47719/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 14b85b0..73f6314 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -199,8 +199,8 @@ * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. * - Enable power to WiFi using EN_PWR_WIFI_L. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET_L. + * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) + * - Deassert WIFI_AUX_RESET_L in mainboard_configure_gpios */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET_L */ @@ -210,8 +210,6 @@ }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - mdelay(50); - gpio_set(GPIO_86, 1); } static void wifi_power_reset_configure_active_high_power(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 Gerrit-Change-Number: 47719 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 7

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020