coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: soc/intel/skylake: Use correct NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 21 Nov '20

21 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45010 ) Change subject: soc/intel/skylake: Use correct NHLT_PDM_DEV definition ...................................................................... Patch Set 8: *ping* -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Nov 2020 21:58:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/amdfwtool: add missing zero-initialization for local variable
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47817 ) Change subject: util/amdfwtool: add missing zero-initialization for local variable ...................................................................... util/amdfwtool: add missing zero-initialization for local variable Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/data_parse.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47817/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index c2ce32b..21e7317 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -224,7 +224,8 @@ { amd_bios_type fw_type = AMD_BIOS_INVALID; amd_bios_entry *bhd_tableptr; - uint8_t subprog, instance = 0; + uint8_t subprog = 0; + uint8_t instance = 0; (void) (cb_config); /* Remove warning and reserved for future. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Gerrit-Change-Number: 47817 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: [WIP] soc/amd: factor out vbnv_cmos_failed() into common block
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47584 ) Change subject: [WIP] soc/amd: factor out vbnv_cmos_failed() into common block ...................................................................... [WIP] soc/amd: factor out vbnv_cmos_failed() into common block still untested. Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/vbnv_cmos/Kconfig A src/soc/amd/common/block/vbnv_cmos/Makefile.inc R src/soc/amd/common/block/vbnv_cmos/vbnv_cmos.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc D src/soc/amd/stoneyridge/pmutil.c 8 files changed, 12 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/47584/1 diff --git a/src/soc/amd/common/block/vbnv_cmos/Kconfig b/src/soc/amd/common/block/vbnv_cmos/Kconfig new file mode 100644 index 0000000..9130167 --- /dev/null +++ b/src/soc/amd/common/block/vbnv_cmos/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_VBNV_CMOS + bool + default n + help + Select this option to add the AMD common VBOOT CMOS functions that + VBOOT_VBNV_CMOS needs to the build. diff --git a/src/soc/amd/common/block/vbnv_cmos/Makefile.inc b/src/soc/amd/common/block/vbnv_cmos/Makefile.inc new file mode 100644 index 0000000..79b65c9 --- /dev/null +++ b/src/soc/amd/common/block/vbnv_cmos/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_VBNV_CMOS) += vbnv_cmos.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_VBNV_CMOS) += vbnv_cmos.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_VBNV_CMOS) += vbnv_cmos.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_VBNV_CMOS) += vbnv_cmos.c diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/common/block/vbnv_cmos/vbnv_cmos.c similarity index 100% rename from src/soc/amd/picasso/pmutil.c rename to src/soc/amd/common/block/vbnv_cmos/vbnv_cmos.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 9ebc651..8fab58c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -43,6 +43,7 @@ select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_VBNV_CMOS if VBOOT_VBNV_CMOS select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ffc1463..6ec4cd1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -23,14 +23,12 @@ bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c -bootblock-y += pmutil.c bootblock-y += reset.c bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c -romstage-y += pmutil.c romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c @@ -45,7 +43,6 @@ romstage-y += mrc_cache.c verstage-y += i2c.c -verstage-y += pmutil.c verstage-y += config.c verstage-y += aoac.c verstage_x86-y += gpio.c @@ -66,7 +63,6 @@ ramstage-y += gpio.c ramstage-y += aoac.c ramstage-y += southbridge.c -ramstage-y += pmutil.c ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0e32005..baba752 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -37,6 +37,7 @@ select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS + select SOC_AMD_COMMON_BLOCK_VBNV_CMOS if VBOOT_VBNV_CMOS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index fb0a45b..311ea68 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += i2c.c bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c -bootblock-y += pmutil.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -28,7 +27,6 @@ romstage-y += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c -romstage-y += pmutil.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -40,7 +38,6 @@ verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-y += pmutil.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c @@ -61,7 +58,6 @@ ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += northbridge.c -ramstage-y += pmutil.c ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c deleted file mode 100644 index a2ad2db..0000000 --- a/src/soc/amd/stoneyridge/pmutil.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <security/vboot/vboot_common.h> -#include <security/vboot/vbnv.h> -#include <pc80/mc146818rtc.h> - -int vbnv_cmos_failed(void) -{ - /* If CMOS power has failed, the century will be set to 0xff */ - return cmos_read(RTC_CLK_ALTCENTURY) == 0xff; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/47584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Gerrit-Change-Number: 47584 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28618 ) Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... Abandoned oh, wait, i should have read what I commented some time ago. sorry for the noise -- To view, visit https://review.coreboot.org/c/coreboot/+/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has restored this change. ( https://review.coreboot.org/c/coreboot/+/28618 ) Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: restore

1 0

Change in coreboot[master]: util/inteltool: Add Sunrise Point LP
by Felix Held (Code Review) 21 Nov '20

21 Nov '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28618 ) Change subject: util/inteltool: Add Sunrise Point LP ...................................................................... Patch Set 6: abandoned? that should probably have been the submit button instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/28618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2454cc11d83a860815bfaab5197c25b29f3384df Gerrit-Change-Number: 28618 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 21 Nov 2020 19:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1473_11
by Subrata Banik (Code Review) 21 Nov '20

21 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47722 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1473_11 ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1473_11 List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 55 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/47722/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 552f50a..da746ba 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -965,7 +965,7 @@ /** Offset 0x0B88 **/ - UINT8 UnusedUpdSpace33[6]; + UINT8 UnusedUpdSpace32[6]; /** Offset 0x0B8E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index e78311c..38945d0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -650,51 +650,47 @@ /** Offset 0x0951 - Reserved **/ - UINT8 Reserved35[105]; + UINT8 Reserved35[132]; -/** Offset 0x09BA - PCH Sata Pwr Opt Enable +/** Offset 0x09D5 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x09BB - Reserved +/** Offset 0x09D6 - Reserved **/ UINT8 Reserved36[50]; -/** Offset 0x09ED - Enable SATA Port DmVal +/** Offset 0x0A08 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x09F5 - Reserved -**/ - UINT8 Reserved37; - -/** Offset 0x09F6 - Enable SATA Port DmVal +/** Offset 0x0A10 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x0A06 - Reserved +/** Offset 0x0A20 - Reserved **/ - UINT8 Reserved38[62]; + UINT8 Reserved37[62]; -/** Offset 0x0A44 - USB2 Port Over Current Pin +/** Offset 0x0A5E - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A54 - USB3 Port Over Current Pin +/** Offset 0x0A6E - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A5E - Reserved +/** Offset 0x0A78 - Reserved **/ - UINT8 Reserved39[14]; + UINT8 Reserved38[16]; -/** Offset 0x0A6C - Enable 8254 Static Clock Gating +/** Offset 0x0A88 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -702,7 +698,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A6D - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A89 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -710,22 +706,22 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A6E - Reserved +/** Offset 0x0A8A - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; -/** Offset 0x0A6F - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A70 - Reserved +/** Offset 0x0A8C - Reserved **/ - UINT8 Reserved41[89]; + UINT8 Reserved40[93]; -/** Offset 0x0AC9 - Enable PS_ON. +/** Offset 0x0AE9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -733,29 +729,29 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0ACA - Reserved +/** Offset 0x0AEA - Reserved **/ - UINT8 Reserved42[310]; + UINT8 Reserved41[318]; -/** Offset 0x0C00 - RpPtmBytes +/** Offset 0x0C28 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0C04 - Reserved +/** Offset 0x0C2C - Reserved **/ - UINT8 Reserved43[99]; + UINT8 Reserved42[95]; -/** Offset 0x0C67 - Enable/Disable IGFX PmSupport +/** Offset 0x0C8B - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C68 - Reserved +/** Offset 0x0C8C - Reserved **/ - UINT8 Reserved44; + UINT8 Reserved43; -/** Offset 0x0C69 - GT Frequency Limit +/** Offset 0x0C8D - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -769,22 +765,22 @@ **/ UINT8 GtFreqMax; -/** Offset 0x0C6A - Reserved +/** Offset 0x0C8E - Reserved **/ - UINT8 Reserved45[24]; + UINT8 Reserved44[24]; -/** Offset 0x0C82 - Enable or Disable HWP +/** Offset 0x0CA6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C83 - Reserved +/** Offset 0x0CA7 - Reserved **/ - UINT8 Reserved46[8]; + UINT8 Reserved45[8]; -/** Offset 0x0C8B - TCC Activation Offset +/** Offset 0x0CAF - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -792,63 +788,63 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0C8C - Reserved +/** Offset 0x0CB0 - Reserved **/ - UINT8 Reserved47[34]; + UINT8 Reserved46[34]; -/** Offset 0x0CAE - Enable or Disable CPU power states (C-states) +/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CAF - Reserved +/** Offset 0x0CD3 - Reserved **/ - UINT8 Reserved48[196]; + UINT8 Reserved47[196]; -/** Offset 0x0D73 - Enable LOCKDOWN SMI +/** Offset 0x0D97 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D74 - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D98 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D75 - Unlock all GPIO pads +/** Offset 0x0D99 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D76 - Reserved +/** Offset 0x0D9A - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved48[2]; -/** Offset 0x0D78 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DB0 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DD4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0DE8 - Reserved +/** Offset 0x0E0C - Reserved **/ - UINT8 Reserved50[313]; + UINT8 Reserved49[313]; -/** Offset 0x0F21 - LpmStateEnableMask +/** Offset 0x0F45 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0F22 - Reserved +/** Offset 0x0F46 - Reserved **/ - UINT8 Reserved51[702]; + UINT8 Reserved50[698]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -867,11 +863,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x11E0 +/** Offset 0x1200 **/ - UINT8 UnusedUpdSpace45[6]; + UINT8 UnusedUpdSpace46[6]; -/** Offset 0x11E6 +/** Offset 0x1206 **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/47722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Gerrit-Change-Number: 47722 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/google/asurada: Get ram id from AUX_IN3
by Yidi Lin (Code Review) 21 Nov '20

21 Nov '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46391 to review the following change. Change subject: mb/google/asurada: Get ram id from AUX_IN3 ...................................................................... mb/google/asurada: Get ram id from AUX_IN3 Mapping the voltage of AUX_IN3 to ram id. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 --- M src/mainboard/google/asurada/boardid.c 1 file changed, 55 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46391/1 diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c index 2c8efcd..6dc1f7a 100644 --- a/src/mainboard/google/asurada/boardid.c +++ b/src/mainboard/google/asurada/boardid.c @@ -1,9 +1,58 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> /* board_id is provided by ec/google/chromeec/ec_boardid.c */ +#define ADC_LEVELS 15 + +enum { + RAM_ID_CHANNEL = 3, +}; + +static const int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + /* 0 : */ 74300, + /* 1 : */ 211700, + /* 2 : */ 318800, + /* 3 : */ 428600, + /* 4 : */ 541700, + /* 5 : */ 665800, + /* 6 : */ 781400, + /* 7 : */ 900000, + /* 8 : */ 1023100, + /* 9 : */ 1137000, + /* 10 : */ 1240000, + /* 11 : */ 1342600, + /* 12 : */ 1457500, + /* 13 : */ 1575600, + /* 14 : */ 1683600, +}; + +static const int *adc_voltages[] = { + [RAM_ID_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + int value = auxadc_get_voltage(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + printk(BIOS_DEBUG, "ADC[%d]: Raw value=%d ID=%d\n", channel, value, id); + return id; +} + uint32_t sku_id(void) { return 0; @@ -11,5 +60,10 @@ uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) + cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + + return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Gerrit-Change-Number: 46391 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: mb/clevo/cml-u: Add hda_verb.c in mainboard Makefile
by Michael Niewöhner (Code Review) 21 Nov '20

21 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47820 ) Change subject: mb/clevo/cml-u: Add hda_verb.c in mainboard Makefile ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Gerrit-Change-Number: 47820 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Nov 2020 13:21:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/clevo/cml-u: Add hda_verb.c in mainboard Makefile
by Felix Singer (Code Review) 21 Nov '20

21 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47820 ) Change subject: mb/clevo/cml-u: Add hda_verb.c in mainboard Makefile ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Gerrit-Change-Number: 47820 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Nov 2020 13:02:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020