coreboot-gerrit November 2020

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Change in coreboot[master]: nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47621 ) Change subject: nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask ...................................................................... nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/47621/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index e93ce0a..886177d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1423,9 +1423,7 @@ FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } + return 0; } @@ -1978,7 +1976,7 @@ int write_training(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, slotrank; int err; FOR_ALL_POPULATED_CHANNELS @@ -1992,10 +1990,6 @@ printram("CPF\n"); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); } @@ -2015,9 +2009,6 @@ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } return 0; } @@ -2294,6 +2285,7 @@ fill_pattern0(ctrl, channel, 0, 0); FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } @@ -2357,10 +2349,6 @@ toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS { - FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - find_predefined_pattern(ctrl, channel); fill_pattern0(ctrl, channel, 0, 0xffffffff); @@ -2539,9 +2527,6 @@ FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } return 0; } @@ -3048,7 +3033,7 @@ void restore_timings(ramctr_timing *ctrl) { - int channel, lane; + int channel; FOR_ALL_POPULATED_CHANNELS { const union tc_rap_reg tc_rap = { @@ -3069,10 +3054,6 @@ wait_for_iosav(channel); } - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); -- To view, visit https://review.coreboot.org/c/coreboot/+/47621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Gerrit-Change-Number: 47621 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Drop `precharge` function
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47620 ) Change subject: nb/intel/sandybridge: Drop `precharge` function ...................................................................... nb/intel/sandybridge: Drop `precharge` function This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 2 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/47620/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 709217c..e93ce0a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1669,51 +1669,6 @@ program_wdb_pattern_length(channel, 16); } -static void precharge(ramctr_timing *ctrl) -{ - int channel, slotrank, lane; - - FOR_ALL_POPULATED_CHANNELS { - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - } -} - static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) { int timB; @@ -2029,12 +1984,12 @@ FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + printram("CPE\n"); + err = jedec_write_leveling(ctrl); if (err) return err; - printram("CPE\n"); - precharge(ctrl); printram("CPF\n"); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { -- To view, visit https://review.coreboot.org/c/coreboot/+/47620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Gerrit-Change-Number: 47620 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded value
by Felix Singer (Code Review) 22 Nov '20

22 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47839 ) Change subject: mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded value ...................................................................... mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded value Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/kontron/bsl6/dsdt.asl M src/mainboard/siemens/chili/dsdt.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47839/1 diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl index 225c8a5..3be5115 100644 --- a/src/mainboard/kontron/bsl6/dsdt.asl +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 diff --git a/src/mainboard/siemens/chili/dsdt.asl b/src/mainboard/siemens/chili/dsdt.asl index 6fd12b1..9b49942 100644 --- a/src/mainboard/siemens/chili/dsdt.asl +++ b/src/mainboard/siemens/chili/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision -- To view, visit https://review.coreboot.org/c/coreboot/+/47839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Gerrit-Change-Number: 47839 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in em100[master]: Cleanly detach em100 in case of error
by Stefan Reinauer (Code Review) 22 Nov '20

22 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47845 ) Change subject: Cleanly detach em100 in case of error ...................................................................... Cleanly detach em100 in case of error Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ibaeefaa9da257dfb3a89275146b40fd0713fa033 --- M em100.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/45/47845/1 diff --git a/em100.c b/em100.c index 1af0f03..178151a 100644 --- a/em100.c +++ b/em100.c @@ -934,8 +934,10 @@ } const chipdesc *chip = setup_chips(desiredchip); - if (desiredchip && !chip) + if (desiredchip && !chip) { + em100_detach(em100); return 1; + } /* Set up signal handler. This is used for two reasons: * 1) to create a way to cleanly exit trace mode. @@ -1026,6 +1028,7 @@ if (desiredchip) { if (!set_chip_type(em100, chip)) { printf("Failed configuring chip type.\n"); + em100_detach(em100); return 0; } printf("Chip set to %s %s.\n", chip->vendor, chip->name); @@ -1040,6 +1043,7 @@ if (address_mode) { if (set_address_mode(em100, address_mode) < 0) { + em100_detach(em100); return 1; } } @@ -1047,6 +1051,7 @@ if (voltage) { if (!set_fpga_voltage_from_str(em100, voltage)) { printf("Failed configuring FPGA voltage.\n"); + em100_detach(em100); return 1; } } @@ -1054,6 +1059,7 @@ if (holdpin) { if (!set_hold_pin_state_from_str(em100, holdpin)) { printf("Failed configuring hold pin state.\n"); + em100_detach(em100); return 0; } } @@ -1076,12 +1082,14 @@ void *data = malloc(maxlen); if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); + em100_detach(em100); return 1; } FILE *fdata = fopen(read_filename, "wb"); if (!fdata) { perror("Could not open download file"); free(data); + em100_detach(em100); return 1; } @@ -1093,6 +1101,7 @@ if (length != 1) { printf("FATAL: failed to write"); + em100_detach(em100); return 1; } } @@ -1105,12 +1114,14 @@ if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); + em100_detach(em100); return 1; } FILE *fdata = fopen(filename, "rb"); if (!fdata) { perror("Could not open upload file"); free(data); + em100_detach(em100); return 1; } @@ -1125,12 +1136,14 @@ if (length > maxlen) { printf("FATAL: length > maxlen\n"); free(data); + em100_detach(em100); return 1; } if (length == 0) { printf("FATAL: No file to upload.\n"); free(data); + em100_detach(em100); return 1; } @@ -1138,6 +1151,7 @@ { printf("FATAL: file size does not match to chip size.\n"); free(data); + em100_detach(em100); return 1; } @@ -1149,6 +1163,7 @@ if (readback == NULL) { printf("FATAL: couldn't allocate memory(size: %x)\n", maxlen); free(data); + em100_detach(em100); return 1; } done = read_sdram(em100, readback, 0, maxlen); @@ -1168,6 +1183,7 @@ if (readback == NULL) { printf("FATAL: couldn't allocate memory\n"); free(data); + em100_detach(em100); return 1; } done = read_sdram(em100, readback, spi_start_address, length); @@ -1195,6 +1211,7 @@ if ((holdpin == NULL) && (!set_hold_pin_state(em100, 3))) { printf("Error: Failed to set EM100 to input\n"); + em100_detach(em100); return 1; } @@ -1230,11 +1247,13 @@ if (!do_start && !do_stop) set_state(em100, 0); + if (trace) reset_spi_trace(em100); if ((holdpin == NULL) && (!set_hold_pin_state(em100, 2))) { printf("Error: Failed to set EM100 to float\n"); + em100_detach(em100); return 1; } } -- To view, visit https://review.coreboot.org/c/em100/+/47845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ibaeefaa9da257dfb3a89275146b40fd0713fa033 Gerrit-Change-Number: 47845 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Clarify register write
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47619 ) Change subject: nb/intel/sandybridge: Clarify register write ...................................................................... nb/intel/sandybridge: Clarify register write It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/47619/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2799103..709217c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1973,6 +1973,7 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5, -- To view, visit https://review.coreboot.org/c/coreboot/+/47619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Gerrit-Change-Number: 47619 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Encapsulate JEDEC write leveling
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47617 ) Change subject: nb/intel/sandybridge: Encapsulate JEDEC write leveling ...................................................................... nb/intel/sandybridge: Encapsulate JEDEC write leveling Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 19 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47617/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cff7e8b..2799103 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1714,7 +1714,7 @@ } } -static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) +static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) { int timB; int statistics[NUM_LANES][128]; @@ -1960,13 +1960,9 @@ * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data * lanes (DQ). */ -int write_training(ramctr_timing *ctrl) +static int jedec_write_leveling(ramctr_timing *ctrl) { - int channel, slotrank, lane; - int err; - - FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + int channel, slotrank; disable_refresh_machine(ctrl); @@ -1989,7 +1985,7 @@ /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timB(ctrl, channel, slotrank); + const int err = write_level_rank(ctrl, channel, slotrank); if (err) return err; } @@ -2021,6 +2017,21 @@ toggle_io_reset(); + return 0; +} + +int write_training(ramctr_timing *ctrl) +{ + int channel, slotrank, lane; + int err; + + FOR_ALL_POPULATED_CHANNELS + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + + err = jedec_write_leveling(ctrl); + if (err) + return err; + printram("CPE\n"); precharge(ctrl); printram("CPF\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9c6315340164029e30354723b4103d906633602 Gerrit-Change-Number: 47617 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Do not rewrite write leveling sequence
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47616 ) Change subject: nb/intel/sandybridge: Do not rewrite write leveling sequence ...................................................................... nb/intel/sandybridge: Do not rewrite write leveling sequence There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47616/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3fdbc98..cff7e8b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1714,24 +1714,6 @@ } } -static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) -{ - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; - int bank = 1; - - if (ctrl->rank_mirror[channel][slotrank]) - ddr3_mirror_mrreg(&bank, &mr1reg); - - wait_for_iosav(channel); - - iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); -} - static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) { int timB; @@ -1747,13 +1729,26 @@ }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + int bank = 1; + + if (ctrl->rank_mirror[channel][slotrank]) + ddr3_mirror_mrreg(&bank, &mr1reg); + + wait_for_iosav(channel); + + iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); + for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].timB = timB; } program_timings(ctrl, channel); - test_timB(ctrl, channel, slotrank); + /* Execute command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); FOR_ALL_LANES { statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + -- To view, visit https://review.coreboot.org/c/coreboot/+/47616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Gerrit-Change-Number: 47616 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Make helper for write leveling sequence
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47615 ) Change subject: nb/intel/sandybridge: Make helper for write leveling sequence ...................................................................... nb/intel/sandybridge: Make helper for write leveling sequence Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 90 insertions(+), 82 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/47615/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2a3fb8c..3fdbc98 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1716,9 +1716,6 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { - /* First DQS/DQS# rising edge after write leveling mode is programmed */ - const u32 tWLMRD = 40; - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; int bank = 1; @@ -1727,85 +1724,7 @@ wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command MRS: enable DQs on this slotrank */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = tWLMRD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = mr1reg, - .rowbits = 6, - .bank = bank, - .rank = slotrank, - }, - }, - /* DRAM command NOP */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CWL + ctrl->tWLO, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command NOP */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP_ALT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CAS + 38, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command MRS: disable DQs on this slotrank */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = mr1reg | 1 << 12, - .rowbits = 6, - .bank = bank, - .rank = slotrank, - }, - }, - }; - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); /* Execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index e3be5c9..8424e8f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,8 @@ void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 11b2acb..25f5ae7 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -199,6 +199,93 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) +{ + /* First DQS/DQS# rising edge after write leveling mode is programmed */ + const u32 tWLMRD = 40; + + const struct iosav_ssq sequence[] = { + /* DRAM command MRS: enable DQs on this slotrank */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tWLMRD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWLO, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP_ALT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CAS + 38, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command MRS: disable DQs on this slotrank */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg | 1 << 12, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Gerrit-Change-Number: 47615 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Run `read_mpr_training` before write training
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47611 ) Change subject: nb/intel/sandybridge: Run `read_mpr_training` before write training ...................................................................... nb/intel/sandybridge: Run `read_mpr_training` before write training Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47611/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e0b5a3d..ae9a4f4 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -684,16 +684,16 @@ if (err) return err; + err = read_mpr_training(ctrl); + if (err) + return err; + err = write_training(ctrl); if (err) return err; printram("CP5a\n"); - err = read_mpr_training(ctrl); - if (err) - return err; - printram("CP5b\n"); err = command_training(ctrl); -- To view, visit https://review.coreboot.org/c/coreboot/+/47611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Gerrit-Change-Number: 47611 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/sandybridge: Rename `read_training` function
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47576 ) Change subject: nb/intel/sandybridge: Rename `read_training` function ...................................................................... nb/intel/sandybridge: Rename `read_training` function Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47576/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index f20181e..9da5a97 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1307,7 +1307,7 @@ * Once the controller has detected this pattern a bit in the result register is set for the * current phase shift. */ -int read_training(ramctr_timing *ctrl) +int receive_enable_calibration(ramctr_timing *ctrl) { int channel, slotrank, lane; int err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index de74af5..5227536 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -400,7 +400,7 @@ void dram_zones(ramctr_timing *ctrl, int training); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); void dram_jedecreset(ramctr_timing *ctrl); -int read_training(ramctr_timing *ctrl); +int receive_enable_calibration(ramctr_timing *ctrl); int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); int discover_edges(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 53017eb..20009cb 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -680,7 +680,7 @@ /* Prepare for memory training */ prepare_training(ctrl); - err = read_training(ctrl); + err = receive_enable_calibration(ctrl); if (err) return err; -- To view, visit https://review.coreboot.org/c/coreboot/+/47576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Gerrit-Change-Number: 47576 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020