coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.c
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47755 ) Change subject: soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.c ...................................................................... soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.c pmc.c mostly contains a PCI driver, while this function just calls into SMM. Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c 4 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47755/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 329bbe9..f62ec2f 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -48,7 +48,4 @@ */ int pmc_soc_get_resources(struct pmc_resource_config *cfg); -/* API to set ACPI mode */ -void pmc_set_acpi_mode(void); - #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2acc275..ecc8166 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -232,4 +232,7 @@ /* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ void pmc_disable_acpi_timer(void); +/* API to set ACPI mode */ +void pmc_set_acpi_mode(void); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 5bfad71..d153bc7 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <device/pci_ops.h> #include <console/console.h> -#include <cpu/x86/smm.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/pmc.h> @@ -90,13 +89,6 @@ pch_pmc_add_io_resources(dev, config); } -void pmc_set_acpi_mode(void) -{ - if (!acpi_is_wakeup_s3()) { - apm_control(APM_CNT_ACPI_DISABLE); - } -} - static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index a5dff2d..02ca6de 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -4,6 +4,7 @@ #include <bootmode.h> #include <device/mmio.h> #include <cbmem.h> +#include <cpu/x86/smm.h> #include <console/console.h> #include <halt.h> #include <intelblocks/pmclib.h> @@ -709,3 +710,10 @@ setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } #endif /* PMC_LOW_POWER_MODE_PROGRAM */ + +void pmc_set_acpi_mode(void) +{ + if (!acpi_is_wakeup_s3()) { + apm_control(APM_CNT_ACPI_DISABLE); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Gerrit-Change-Number: 47755 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: MAINTAINERS: update maintainers of INTEL FSP DENVERTON-NS SOC & HARCU...
by Mariusz Szafrański (Code Review) 22 Nov '20

22 Nov '20

Mariusz Szafrański has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47753 ) Change subject: MAINTAINERS: update maintainers of INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB ...................................................................... MAINTAINERS: update maintainers of INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB Change-Id: Ifdb24f9566b53af6c23b4cd4adba0c1876e4fc9d Signed-off-by: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> --- M MAINTAINERS 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47753/1 diff --git a/MAINTAINERS b/MAINTAINERS index 1f4df52..79f771d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -506,8 +506,10 @@ F: src/include/cpu/intel/ INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB +M: Suresh Bellampalli <suresh.bellampalli(a)intel.com> M: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> -M: David Guckian <david.guckian(a)intel.com> +M: Michal Motyl <michalx.motyl(a)intel.com> +M: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> S: Odd Fixes F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ -- To view, visit https://review.coreboot.org/c/coreboot/+/47753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb24f9566b53af6c23b4cd4adba0c1876e4fc9d Gerrit-Change-Number: 47753 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-MessageType: newchange

9 12

Change in coreboot[master]: soc/intel/denverton_ns: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 22 Nov '20

22 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46240 ) Change subject: soc/intel/denverton_ns: Convert to ASL 2.0 syntax ...................................................................... soc/intel/denverton_ns: Convert to ASL 2.0 syntax Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/irqlinks.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 4 files changed, 66 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46240/1 diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index f858cdf..7ce6c7a 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -62,27 +62,27 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } diff --git a/src/soc/intel/denverton_ns/acpi/irqlinks.asl b/src/soc/intel/denverton_ns/acpi/irqlinks.asl index e62d84d..ef076bc 100644 --- a/src/soc/intel/denverton_ns/acpi/irqlinks.asl +++ b/src/soc/intel/denverton_ns/acpi/irqlinks.asl @@ -8,7 +8,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link @@ -28,10 +28,10 @@ CreateWordField(RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link @@ -87,10 +87,10 @@ CreateWordField(RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -103,14 +103,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link @@ -146,10 +146,10 @@ CreateWordField(RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -162,14 +162,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link @@ -205,10 +205,10 @@ CreateWordField(RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -221,14 +221,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link @@ -264,10 +264,10 @@ CreateWordField(RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -280,14 +280,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link @@ -323,10 +323,10 @@ CreateWordField(RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -339,14 +339,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link @@ -382,10 +382,10 @@ CreateWordField(RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -398,14 +398,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link @@ -441,10 +441,10 @@ CreateWordField(RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -457,14 +457,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index e1d1e40..40d745e 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -97,9 +97,9 @@ CreateDwordField(MCRS, ^PM01._LEN, PLEN) // MMIO Low is saved in NVS - Store (\MMOB, PMIN) - Store (\MMOL, PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \MMOB + PMAX = \MMOL + PLEN = PMAX - PMIN + 1 // Find PCI resource area in MCRS CreateQWordField(MCRS, ^PM02._MIN, P2MN) @@ -107,9 +107,9 @@ CreateQWordField(MCRS, ^PM02._LEN, P2LN) // MMIO High is saved in NVS - Store(\MMHB, P2MN) - Store(\MMHL, P2MX) - Add(Subtract(P2MX,P2MN),1,P2LN) + P2MN = \MMHB + P2MX = \MMHL + P2LN = P2MX - P2MN +1 Return (MCRS) } // End _CRS @@ -132,9 +132,9 @@ { // Fix up 32-bit TSEG CreateDWordField(PDRS, ^TSMB._BAS, TSMN) - Store(\TSGB, TSMN) + TSMN = \TSGB CreateDWordField(PDRS, ^TSMB._LEN, TSLN) - Store(\TSSZ, TSLN) + TSLN = \TSSZ Return(PDRS) } } diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 68f55f2..72e12bd 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -128,7 +128,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -137,7 +137,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Gerrit-Change-Number: 46240 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer/var/voema: Update gpio and devicetree settings
by David Wu (Code Review) 22 Nov '20

22 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47667 ) Change subject: mb/google/volteer/var/voema: Update gpio and devicetree settings ...................................................................... mb/google/volteer/var/voema: Update gpio and devicetree settings Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 --- M src/mainboard/google/volteer/variants/voema/Makefile.inc A src/mainboard/google/volteer/variants/voema/gpio.c M src/mainboard/google/volteer/variants/voema/include/variant/gpio.h M src/mainboard/google/volteer/variants/voema/overridetree.cb 4 files changed, 433 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/47667/1 diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc index 9064208..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/voema/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c new file mode 100644 index 0000000..2a9299b --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> PCH_FPMCU_BOOT1 */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> CAM_DET_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> CAM_SEN_EN */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h index b5fa8c5..166c06c 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -5,11 +5,8 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -/* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_D15 +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 #endif diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 32204c5..0f964b6 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -1,6 +1,207 @@ chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + # Disable SRCCLKREQ1# and SRCCLKREQ3# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 14 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN90FC"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port3 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/47667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Gerrit-Change-Number: 47667 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 17

Change in coreboot[master]: cpu/amd/pi: Remove unused cpu code 00660F01
by Martin Roth (Code Review) 22 Nov '20

22 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47652 ) Change subject: cpu/amd/pi: Remove unused cpu code 00660F01 ...................................................................... cpu/amd/pi: Remove unused cpu code 00660F01 Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 --- D src/cpu/amd/pi/00660F01/Kconfig D src/cpu/amd/pi/00660F01/Makefile.inc D src/cpu/amd/pi/00660F01/acpi/cpu.asl D src/cpu/amd/pi/00660F01/chip_name.c D src/cpu/amd/pi/00660F01/fixme.c D src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/Kconfig M src/cpu/amd/pi/Makefile.inc M src/northbridge/amd/agesa/state_machine.h M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig M src/vendorcode/amd/pi/Makefile.inc 13 files changed, 3 insertions(+), 288 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47652/1 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig deleted file mode 100644 index 1cdfb1d..0000000 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config CPU_AMD_PI_00660F01 - bool - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_PI_00660F01 - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc deleted file mode 100644 index 69635fc..0000000 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += fixme.c -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_15_init.c - -subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr -subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl deleted file mode 100644 index ede5021..0000000 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Processor Object - * - */ -Scope (\_SB) { /* define processor scope */ - - Device (P000) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - - Device (P001) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - - Device (P002) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - - Device (P003) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - - Device (P004) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - - Device (P005) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - - Device (P006) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - - Device (P007) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } -} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c deleted file mode 100644 index 06fa444..0000000 --- a/src/cpu/amd/pi/00660F01/chip_name.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> - -struct chip_operations cpu_amd_pi_00660F01_ops = { - CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh") -}; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c deleted file mode 100644 index 9b208ec..0000000 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cpu/x86/mtrr.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/mtrr.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> - -void amd_initcpuio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; - /* set NP (non-posted) bit */ - PciData |= 1 << 7; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -} diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c deleted file mode 100644 index 4bb2896..0000000 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <device/pci.h> -#include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> -#include <cpu/cpu.h> -#include <cpu/x86/cache.h> - -#include <amdlib.h> -#include <PspBaseLib.h> - -void PSPProgBar3Msr(void *Buffer); - -void PSPProgBar3Msr(void *Buffer) -{ - u32 Bar3Addr; - u64 Tmp64; - /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig(0x20); - Tmp64 = Bar3Addr; - printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); -} - -static void model_15_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - u8 i; - msr_t msr; - int num_banks; - int msrno; -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - x86_mtrr_check(); - x86_enable_cache(); - - /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - - /* Enable the local CPU APICs */ - setup_lapic(); - -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - PSPProgBar3Msr(NULL); - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index e626ef1..c0ac2ee 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -4,7 +4,6 @@ bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 - default y if CPU_AMD_PI_00660F01 default n select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 9694347..dc9fd6b 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -2,4 +2,3 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 -subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 93a70cd..a857727 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -83,9 +83,6 @@ void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); -#if CONFIG(CPU_AMD_PI_00660F01) -typedef void AMD_S3SAVE_PARAMS; -#endif void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index cfe85a1..ac6caf9 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -61,7 +61,7 @@ config HUDSON_PSP bool - default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 + default y if CPU_AMD_PI_00730F01 config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" @@ -89,7 +89,6 @@ depends on HUDSON_PSP string "AMD public Key" default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01 config HUDSON_SATA_MODE int "SATA Mode" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 94c759e..215a5a1 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -83,18 +83,6 @@ endif -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=CZ - -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin -endif - #PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key #PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin #PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 15d2ab2..fb4935b 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,7 +26,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || SOC_AMD_STONEYRIDGE config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" @@ -34,7 +34,6 @@ default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON - default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files for AMD platform initialization. @@ -46,7 +45,6 @@ default "3rdparty/amd_blobs/stoneyridge/pi/CZ/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS - default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 8f27d64..25e3652 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += 00670F00 -ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00660F01),y) +ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) @@ -52,10 +52,6 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common -ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y) -AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern -AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib -endif ifeq ($(CONFIG_CPU_AMD_PI_00630F01),y) AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS endif @@ -111,11 +107,6 @@ agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS]) -ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) -endif ifeq ($(CONFIG_HUDSON_IMC_FWM),y) agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Gerrit-Change-Number: 47652 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/facebook/fbg1701: Add VBOOT support
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46219 ) Change subject: mb/facebook/fbg1701: Add VBOOT support ...................................................................... mb/facebook/fbg1701: Add VBOOT support Add VBOOT support. Disabled USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 --- M src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/vboot-rw.fmd 2 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46219/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index d86458f..d6d2a27 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -20,7 +20,18 @@ select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS - select USE_VENDORCODE_ELTAN + +config USE_VENDORCODE_ELTAN + depends on !VBOOT + default y + +config VBOOT_VBNV_CMOS + depends on VBOOT + default y + +config VBOOT_SLOTS_RW_AB + depends on VBOOT + default n config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" @@ -88,4 +99,16 @@ bool default n +config FMDFILE + depends on VBOOT + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw.fmd" + +config RW_REGION_ONLY + depends on VBOOT + default "%/payload logo.bmp %/ramstage vbt.bin %/dsdt.aml config %/postcar" + +config RO_REGION_ONLY + depends on VBOOT + default "spd.bin fsp.bin cpu_microcode_blob.bin" + endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd new file mode 100644 index 0000000..51ee470 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -0,0 +1,21 @@ +FLASH 8M { + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x08000 { + RW_MRC_CACHE@0 0x08000 + } + RW_SECTION_A@0x08000 0x578000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x567FC0 + } + WP_RO@0x580000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x400 + RO_FRID@0xA00 0x40 + RO_FRID_PAD@0xA40 0x5c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Gerrit-Change-Number: 46219 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: drivers/i2c/hid: Use ACPI device name if provided by config
by Matt DeVillier (Code Review) 22 Nov '20

22 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47782 ) Change subject: drivers/i2c/hid: Use ACPI device name if provided by config ...................................................................... drivers/i2c/hid: Use ACPI device name if provided by config Follow model of drivers/i2c/generic and use user-supplied device name if specified in the chip config. Change-Id: Ia783bac2797e239989c03a3421b9293a055db3d0 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/drivers/i2c/hid/hid.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47782/1 diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 0755852..2d213eb 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -28,6 +28,10 @@ static const char *i2c_hid_acpi_name(const struct device *dev) { static char name[5]; + struct drivers_i2c_hid_config *config = dev->chip_info; + if (config->generic.name) + return config->generic.name; + snprintf(name, sizeof(name), "H%03.3X", dev->path.i2c.device); name[4] = '\0'; return name; -- To view, visit https://review.coreboot.org/c/coreboot/+/47782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia783bac2797e239989c03a3421b9293a055db3d0 Gerrit-Change-Number: 47782 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: drivers/i2c/generic: Only write DDN field if description not empty
by Matt DeVillier (Code Review) 22 Nov '20

22 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47781 ) Change subject: drivers/i2c/generic: Only write DDN field if description not empty ...................................................................... drivers/i2c/generic: Only write DDN field if description not empty DDN field isn't required, no point in writing an empty string to it. Change-Id: Ifea6e48c324598f114178e86a79f519ee35f5258 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/drivers/i2c/generic/generic.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47781/1 diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index cd74068..1c7267e 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -72,7 +72,8 @@ if (config->cid) acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); - acpigen_write_name_string("_DDN", config->desc); + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(acpi_device_status(dev)); /* Resources */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea6e48c324598f114178e86a79f519ee35f5258 Gerrit-Change-Number: 47781 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Mention newer Intel μ-code updates in 4.13 release notes
by Paul Menzel (Code Review) 22 Nov '20

22 Nov '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47762 ) Change subject: Documentation: Mention newer Intel μ-code updates in 4.13 release notes ...................................................................... Documentation: Mention newer Intel μ-code updates in 4.13 release notes Start a new section *Notes* for these kind of information. Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47762/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index c9447a3..a5d05ac 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -120,3 +120,27 @@ In order to minimize the usage of PCI bus mastering, the options we introduced in this release will be dropped in a future release again. For more details, please see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). + +Notes +----- + +### Intel microcode updates + +Intel microcode updates tagged *microcode-20200616* are still included in our +builds. Note, [Intel released new microcode updates] +(https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) +tagged + +1. *microcode-20201110* +1. *microcode-20201112* +1. *microcode-20201118* + +with security updates for [INTEL-SA-00381] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00381.html) +and [INTEL-SA-00389] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00389.html). + +Due to too short time for rigorous testing, and bad experience with botched +microcode updates in the past, these new updates are not included. Users wanting +to use those, can apply them in the operating system, or update the submodule +pointer themselves. -- To view, visit https://review.coreboot.org/c/coreboot/+/47762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Gerrit-Change-Number: 47762 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c: Add a driver for Semtech SX9324
by EricR Lai (Code Review) 22 Nov '20

22 Nov '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47640 ) Change subject: drivers/i2c: Add a driver for Semtech SX9324 ...................................................................... drivers/i2c: Add a driver for Semtech SX9324 This adds a new driver for the SX9324 proximity detector device. BUG=b:172397658 BRANCH=zork TEST=Test sx9324 is working as expect. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ifd582482728a2f535ed85f6696b2f5a4529ba421 --- A src/drivers/i2c/sx9324/Kconfig A src/drivers/i2c/sx9324/Makefile.inc A src/drivers/i2c/sx9324/chip.h A src/drivers/i2c/sx9324/registers.h A src/drivers/i2c/sx9324/sx9324.c 5 files changed, 200 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47640/1 diff --git a/src/drivers/i2c/sx9324/Kconfig b/src/drivers/i2c/sx9324/Kconfig new file mode 100644 index 0000000..77f6967 --- /dev/null +++ b/src/drivers/i2c/sx9324/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_SX9324 + bool + default n + depends on HAVE_ACPI_TABLES + help + Board has a Semtech SX9324 proximity sensor. diff --git a/src/drivers/i2c/sx9324/Makefile.inc b/src/drivers/i2c/sx9324/Makefile.inc new file mode 100644 index 0000000..8811c99 --- /dev/null +++ b/src/drivers/i2c/sx9324/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_SX9324) += sx9324.c diff --git a/src/drivers/i2c/sx9324/chip.h b/src/drivers/i2c/sx9324/chip.h new file mode 100644 index 0000000..f813c0f --- /dev/null +++ b/src/drivers/i2c/sx9324/chip.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_I2C_SX9324_CHIP_H__ +#define __DRIVERS_I2C_SX9324_CHIP_H__ + +#include <acpi/acpi_device.h> +#include <device/i2c_simple.h> + +#define REGISTER(NAME) uint8_t NAME + +struct drivers_i2c_sx9324_config { + /* ACPI _HID */ + const char *hid; + + /* Device Name */ + const char *name; + + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; +#include "registers.h" +}; + +#undef REGISTER + +#endif /* __DRIVERS_I2C_SX9324_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h new file mode 100644 index 0000000..8098648 --- /dev/null +++ b/src/drivers/i2c/sx9324/registers.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef REGISTER +#error "define REGISTER(NAME) before including this file" +#endif + +REGISTER(reg_gnrl_ctrl0); +REGISTER(reg_gnrl_ctrl1); + +REGISTER(reg_afe_ctrl0); +REGISTER(reg_afe_ctrl1); +REGISTER(reg_afe_ctrl2); +REGISTER(reg_afe_ctrl3); +REGISTER(reg_afe_ctrl4); +REGISTER(reg_afe_ctrl5); +REGISTER(reg_afe_ctrl6); +REGISTER(reg_afe_ctrl7); +REGISTER(reg_afe_ctrl8); +REGISTER(reg_afe_ctrl9); + +REGISTER(reg_prox_ctrl0); +REGISTER(reg_prox_ctrl1); +REGISTER(reg_prox_ctrl2); +REGISTER(reg_prox_ctrl3); +REGISTER(reg_prox_ctrl4); +REGISTER(reg_prox_ctrl5); +REGISTER(reg_prox_ctrl6); +REGISTER(reg_prox_ctrl7); + +REGISTER(reg_adv_ctrl0); +REGISTER(reg_adv_ctrl1); +REGISTER(reg_adv_ctrl2); +REGISTER(reg_adv_ctrl3); +REGISTER(reg_adv_ctrl4); +REGISTER(reg_adv_ctrl5); +REGISTER(reg_adv_ctrl6); +REGISTER(reg_adv_ctrl7); +REGISTER(reg_adv_ctrl8); +REGISTER(reg_adv_ctrl9); +REGISTER(reg_adv_ctrl10); +REGISTER(reg_adv_ctrl11); +REGISTER(reg_adv_ctrl12); +REGISTER(reg_adv_ctrl13); +REGISTER(reg_adv_ctrl14); +REGISTER(reg_adv_ctrl15); +REGISTER(reg_adv_ctrl16); +REGISTER(reg_adv_ctrl17); +REGISTER(reg_adv_ctrl18); +REGISTER(reg_adv_ctrl19); +REGISTER(reg_adv_ctrl20); + + diff --git a/src/drivers/i2c/sx9324/sx9324.c b/src/drivers/i2c/sx9324/sx9324.c new file mode 100644 index 0000000..8e6e83f --- /dev/null +++ b/src/drivers/i2c/sx9324/sx9324.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <device/device.h> +#include <device/path.h> +#include <string.h> +#include "chip.h" + +#define I2C_SX9324_ACPI_ID "STH9324" +#define I2C_SX9324_ACPI_NAME "Semtech SX9324" + +#define REGISTER(NAME) acpi_dp_add_integer(dsd, \ + I2C_SX9324_ACPI_ID "," #NAME, \ + config->NAME) + +static void i2c_sx9324_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + + if (!scope || !config) + return; + + if (config->speed) + i2c.speed = config->speed; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", I2C_SX9324_ACPI_ID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); +#include "registers.h" + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +#undef REGISTER + +static const char *i2c_sx9324_acpi_name(const struct device *dev) +{ + static char name[5]; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + return name; +} + +static struct device_operations i2c_sx9324_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = i2c_sx9324_acpi_name, + .acpi_fill_ssdt = i2c_sx9324_fill_ssdt, +}; + +static void i2c_sx9324_enable(struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + + if (!config) { + dev->enabled = 0; + return; + } + + dev->ops = &i2c_sx9324_ops; + + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_sx9324_ops = { + CHIP_NAME(I2C_SX9324_ACPI_NAME) + .enable_dev = i2c_sx9324_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/47640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd582482728a2f535ed85f6696b2f5a4529ba421 Gerrit-Change-Number: 47640 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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