coreboot-gerrit November 2020

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Change in coreboot[master]: crossgcc: Upgrade IASL to version 20200925
by HAOUAS Elyes (Code Review) 22 Nov '20

22 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45750 ) Change subject: crossgcc: Upgrade IASL to version 20200925 ...................................................................... crossgcc: Upgrade IASL to version 20200925 Change-Id: I3559e5bd884db4dccdaa5ac7edba4faf57da7930 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20200925_iasl.patch D util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum 3 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45750/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f9cac5..8865e95 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -40,7 +40,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.35 GDB_VERSION=9.2 -IASL_VERSION=20200717 +IASL_VERSION=20200925 PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200925_iasl.patch similarity index 64% rename from util/crossgcc/patches/acpica-unix2-20200717_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200925_iasl.patch index 01dec7c..f3339c8 100644 --- a/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20200925_iasl.patch @@ -1,27 +1,28 @@ -diff -Naur acpica-unix2-20200717_/source/compiler/asloptions.c acpica-unix2-20200717/source/compiler/asloptions.c > acpica-unix2-20200717_iasl.patch ---- acpica-unix2-20200717_/source/compiler/asloptions.c -+++ acpica-unix2-20200717/source/compiler/asloptions.c -@@ -126,6 +126,7 @@ - if (Gbl_DoSignon) +diff --git a/source/compiler/asloptions.c b/source/compiler/asloptions.c +index 4bf9465ba..bcd5abf80 100644 +--- a/source/compiler/asloptions.c ++++ b/source/compiler/asloptions.c +@@ -234,6 +234,7 @@ AslCommandLine ( + if (AslGbl_DoSignon) { printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); if (AslGbl_IgnoreErrors) { printf ("Ignoring all errors, forcing AML file generation\n\n"); -@@ -753,6 +754,7 @@ +@@ -866,6 +867,7 @@ AslDoOptions ( case '^': - + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); exit (0); - + case 'a': -@@ -766,6 +768,7 @@ - +@@ -879,6 +881,7 @@ AslDoOptions ( + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); printf (ACPI_COMMON_BUILD_TIME); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); exit (0); - + case 'e': diff --git a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum deleted file mode 100644 index 9bcfe83..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -92b0177f36b5209e6a667808ca58ef7462c4a6c7 tarballs/acpica-unix2-20200717.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/45750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3559e5bd884db4dccdaa5ac7edba4faf57da7930 Gerrit-Change-Number: 45750 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

8 31

Change in coreboot[master]: vendorcode/eltan/secuirty: Add dependency for menu items
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47740 ) Change subject: vendorcode/eltan/secuirty: Add dependency for menu items ...................................................................... vendorcode/eltan/secuirty: Add dependency for menu items Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are displayed always. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/vendorcode/eltan/security/mboot/Kconfig M src/vendorcode/eltan/security/verified_boot/Kconfig 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47740/1 diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 91898fc..540b7b2 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -10,8 +10,11 @@ Enabling MBOOT will use mboot to measure the components of the firmware (stages, payload, etc). +if VENDORCODE_ELTAN_MBOOT + config VENDORCODE_ELTAN_CRTM_VERSION_STRING string "default CRTM version" default "default CRTM version" +endif # VENDORCODE_ELTAN_MBOOT endmenu # Measured Boot (mboot) diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index b4d1378..7741782 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -8,6 +8,8 @@ default n select VBOOT_LIB +if VENDORCODE_ELTAN_VBOOT + config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST bool "Enable Signed Manifest" depends on VENDORCODE_ELTAN_VBOOT @@ -52,4 +54,5 @@ int default 552 +endif # VENDORCODE_ELTAN_VBOOT endmenu # Verified Boot (verified_boot) -- To view, visit https://review.coreboot.org/c/coreboot/+/47740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Gerrit-Change-Number: 47740 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/tpm: Move PPI stub
by Patrick Rudolph (Code Review) 22 Nov '20

22 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45567 ) Change subject: drivers/tpm: Move PPI stub ...................................................................... drivers/tpm: Move PPI stub As preparation to a full PPI implementation move the acpi code out of the pc80/tpm/tis driver into the generic tpm driver folder. This doesn't change any functionality. Change-Id: I7818d0344d4a08926195bd4804565502717c48fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/pc80/tpm/tis.c M src/drivers/tpm/Makefile.inc A src/drivers/tpm/ppi_stub.c A src/drivers/tpm/tpm_ppi.h 4 files changed, 157 insertions(+), 121 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/45567/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 27d238c..48e529a 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -21,13 +21,11 @@ #include <console/console.h> #include <security/tpm/tis.h> #include <device/pnp.h> +#include <drivers/tpm/tpm_ppi.h> #include "chip.h" #define PREFIX "lpc_tpm: " -/* TCG Physical Presence Interface */ -#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" -/* TCG Memory Clear Interface */ -#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ if (CONFIG(DEBUG_TPM)) { \ @@ -777,104 +775,9 @@ } #if CONFIG(HAVE_ACPI_TABLES) - -static void tpm_ppi_func0_cb(void *arg) -{ - /* Functions 1-8. */ - u8 buf[] = {0xff, 0x01}; - acpigen_write_return_byte_buffer(buf, 2); -} - -static void tpm_ppi_func1_cb(void *arg) -{ - if (CONFIG(TPM2)) - /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); - else - /* Interface version: 1.2 */ - acpigen_write_return_string("1.2"); -} - -static void tpm_ppi_func2_cb(void *arg) -{ - /* Submit operations: drop on the floor and return success. */ - acpigen_write_return_byte(0); -} - -static void tpm_ppi_func3_cb(void *arg) -{ - /* Pending operation: none. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(2); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func4_cb(void *arg) -{ - /* Pre-OS transition method: reboot. */ - acpigen_write_return_byte(2); -} -static void tpm_ppi_func5_cb(void *arg) -{ - /* Operation response: no operation executed. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(3); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func6_cb(void *arg) -{ - /* - * Set preferred user language: deprecated and must return 3 aka - * "not implemented". - */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func7_cb(void *arg) -{ - /* Submit operations: deny. */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func8_cb(void *arg) -{ - /* All actions are forbidden. */ - acpigen_write_return_byte(1); -} -static void (*tpm_ppi_callbacks[])(void *) = { - tpm_ppi_func0_cb, - tpm_ppi_func1_cb, - tpm_ppi_func2_cb, - tpm_ppi_func3_cb, - tpm_ppi_func4_cb, - tpm_ppi_func5_cb, - tpm_ppi_func6_cb, - tpm_ppi_func7_cb, - tpm_ppi_func8_cb, -}; - -static void tpm_mci_func0_cb(void *arg) -{ - /* Function 1. */ - acpigen_write_return_singleton_buffer(0x3); -} -static void tpm_mci_func1_cb(void *arg) -{ - /* Just return success. */ - acpigen_write_return_byte(0); -} - -static void (*tpm_mci_callbacks[])(void *) = { - tpm_mci_func0_cb, - tpm_mci_func1_cb, -}; - static void lpc_tpm_fill_ssdt(const struct device *dev) { const char *path = acpi_device_path(dev->bus->dev); - u32 arg; if (!path) { path = "\\_SB_.PCI0.LPCB"; @@ -938,31 +841,12 @@ acpi_device_write_interrupt(&tpm_irq); } + acpigen_write_resourcetemplate_footer(); - if (!CONFIG(CHROMEOS)) { - /* - * _DSM method - */ - struct dsm_uuid ids[] = { - /* Physical presence interface. - * This is used to submit commands like "Clear TPM" to - * be run at next reboot provided that user confirms - * them. Spec allows user to cancel all commands and/or - * configure BIOS to reject commands. So we pretend that - * user did just this: cancelled everything. If user - * really wants to clear TPM the only option now is to - * do it manually in payload. - */ - DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], - ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), - /* Memory clearing on boot: just a dummy. */ - DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], - ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), - }; + if (!CONFIG(CHROMEOS)) + tpm_ppi_acpi_fill_ssdt(dev); - acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 4e80600..5fc4632 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1 +1,3 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c new file mode 100644 index 0000000..a4b8f57 --- /dev/null +++ b/src/drivers/tpm/ppi_stub.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <stddef.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> + +#include "tpm_ppi.h" + + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, 2); +} + +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 2.0 */ + acpigen_write_return_string("2.0"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +static void tpm_ppi_func2_cb(void *arg) +{ + /* Submit operations: drop on the floor and return success. */ + acpigen_write_return_byte(0); +} + +static void tpm_ppi_func3_cb(void *arg) +{ + /* Pending operation: none. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(2); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(2); +} +static void tpm_ppi_func5_cb(void *arg) +{ + /* Operation response: no operation executed. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(3); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 aka + * "not implemented". + */ + acpigen_write_return_byte(3); +} +static void tpm_ppi_func7_cb(void *arg) +{ + /* Submit operations: deny. */ + acpigen_write_return_byte(3); +} +static void tpm_ppi_func8_cb(void *arg) +{ + /* All actions are forbidden. */ + acpigen_write_return_byte(1); +} +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + u32 arg; + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. Spec allows user to cancel all commands and/or + * configure BIOS to reject commands. So we pretend that + * user did just this: cancelled everything. If user + * really wants to clear TPM the only option now is to + * do it manually in payload. + */ + DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], + ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], + ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h new file mode 100644 index 0000000..4bacbe5 --- /dev/null +++ b/src/drivers/tpm/tpm_ppi.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _TPM_PPI_H_ +#define _TPM_PPI_H_ + +#include <device/device.h> + +#if CONFIG(HAVE_ACPI_TABLES) +void tpm_ppi_acpi_fill_ssdt(const struct device *dev); +#else +static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ +} +#endif + +/* TCG Physical Presence Interface */ +#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TCG Memory Clear Interface */ +#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + +#endif /* _TPM_PPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45567 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7818d0344d4a08926195bd4804565502717c48fa Gerrit-Change-Number: 45567 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/facebook/fbg1701/Kconfig: Add dependency
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46218 ) Change subject: mb/facebook/fbg1701/Kconfig: Add dependency ...................................................................... mb/facebook/fbg1701/Kconfig: Add dependency VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46218/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 0f23ed2..d86458f 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -49,6 +49,7 @@ default 0xfff9c000 config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + depends on USE_VENDORCODE_ELTAN hex default 0xFFFE9000 @@ -69,14 +70,17 @@ default 0x4000 config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + depends on USE_VENDORCODE_ELTAN bool default y config VENDORCODE_ELTAN_VBOOT_MANIFEST + depends on USE_VENDORCODE_ELTAN string default "mainboard/facebook/fbg1701/manifest.h" config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + depends on USE_VENDORCODE_ELTAN hex default 0xFFFF9C00 -- To view, visit https://review.coreboot.org/c/coreboot/+/46218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Gerrit-Change-Number: 46218 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/intel/xeon_sp: Work around FSP-T not respecting its own API
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47738 ) Change subject: soc/intel/xeon_sp: Work around FSP-T not respecting its own API ...................................................................... soc/intel/xeon_sp: Work around FSP-T not respecting its own API The CPX FSP-T does not respect the FSP2.x spec and uses registers where coreboot has its initial timestamp stored. Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/bootblock.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47738/1 diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5adda44..5524c66 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -33,11 +33,20 @@ .UpdTerminator = 0x55AA, }; +static uint64_t assembly_timestamp; +static uint64_t bootblock_timestamp; + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + /* + * FSP-T does not respect its own API and trashes registers + * coreboot uses to store its initial timestamp. + */ + assembly_timestamp = base_timestamp; + bootblock_timestamp = timestamp_get(); fast_spi_cache_bios_region(); - bootblock_main_with_basetime(base_timestamp); + bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp)); } void bootblock_soc_early_init(void) @@ -55,6 +64,10 @@ { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + + if (assembly_timestamp < bootblock_timestamp) + printk(BIOS_WARNING, "Invalid initial timestamp detected\n"); + if (CONFIG(FSP_CAR)) report_fspt_output(); bootblock_pch_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/47738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Gerrit-Change-Number: 47738 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/octopus: fix droid lte sku load specific wifi sar value
by Sheng-Liang Pan (Code Review) 22 Nov '20

22 Nov '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47697 ) Change subject: mb/google/octopus: fix droid lte sku load specific wifi sar value ...................................................................... mb/google/octopus: fix droid lte sku load specific wifi sar value This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex. BUG=none BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 --- M src/mainboard/google/octopus/variants/bobba/variant.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47697/1 diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 96806a0..891da32 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -21,8 +21,9 @@ const char *filename = NULL; uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || - sku_id == 42 || sku_id == 43 || sku_id == 44) + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 37 || + sku_id == 38 || sku_id == 39 || sku_id == 40 || sku_id == 41 || sku_id == 42 || + sku_id == 43 || sku_id == 44) filename = "wifi_sar-droid.hex"; return filename; -- To view, visit https://review.coreboot.org/c/coreboot/+/47697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 Gerrit-Change-Number: 47697 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: cpu/amd/microcode: Remove dead Makefile
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47718 ) Change subject: cpu/amd/microcode: Remove dead Makefile ...................................................................... cpu/amd/microcode: Remove dead Makefile Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/cpu/amd/microcode/Makefile.inc 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/47718/1 diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc deleted file mode 100644 index f409d1f..0000000 --- a/src/cpu/amd/microcode/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-y += microcode.c -romstage-y += microcode.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Gerrit-Change-Number: 47718 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/block/pmclib.c: Properly guard apm_control()
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47757 ) Change subject: soc/intel/block/pmclib.c: Properly guard apm_control() ...................................................................... soc/intel/block/pmclib.c: Properly guard apm_control() This function is only properly implemented with SMM support. Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47757/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 02ca6de..09af749 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -713,7 +713,7 @@ void pmc_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3()) { + if (!CONFIG(NO_SMM) && !acpi_is_wakeup_s3()) { apm_control(APM_CNT_ACPI_DISABLE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Gerrit-Change-Number: 47757 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/pmc.c Don't implement a weak function that dies
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47752 ) Change subject: soc/intel/common/pmc.c Don't implement a weak function that dies ...................................................................... soc/intel/common/pmc.c Don't implement a weak function that dies Buildtime failures are better than runtime failures. Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/pmc/pmc.c 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47752/1 diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 5bfad71..c11ba79 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -9,16 +9,6 @@ #include <intelblocks/pmc.h> #include <soc/pci_devs.h> -/* SoC overrides */ - -/* Fill up PMC resource structure inside SoC directory */ -__weak int pmc_soc_get_resources( - struct pmc_resource_config *cfg) -{ - /* no-op */ - return -1; -} - /* SoC override PMC initialization */ __weak void pmc_soc_init(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Gerrit-Change-Number: 47752 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/block/pmc: Only include the PCI driver when it is not hidden
by Arthur Heymans (Code Review) 22 Nov '20

22 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47756 ) Change subject: soc/intel/block/pmc: Only include the PCI driver when it is not hidden ...................................................................... soc/intel/block/pmc: Only include the PCI driver when it is not hidden On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/Makefile.inc M src/soc/intel/skylake/Kconfig 4 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47756/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3917fea..4f762a9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -78,6 +78,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index b420865..8cd2635 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -13,6 +13,12 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y +config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + bool + help + Select this on platforms where the PMC device is discoverable + when scanning busses. + endif # SOC_INTEL_COMMON_BLOCK_PMC config PMC_INVALID_READ_AFTER_WRITE diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 49a0902..de69b63 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y) bootblock-y += pmclib.c romstage-y += pmclib.c -ramstage-y += pmc.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE) += pmc.c ramstage-y += pmclib.c pmc_ipc.c smm-y += pmclib.c verstage-y += pmclib.c diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ce46d06..ed81e24 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -55,6 +55,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SGX -- To view, visit https://review.coreboot.org/c/coreboot/+/47756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Gerrit-Change-Number: 47756 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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