coreboot-gerrit November 2020

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Change in coreboot[master]: soc/ti/am335x: Fix timer implementation
by Sam Lewis (Code Review) 22 Nov '20

22 Nov '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44383 ) Change subject: soc/ti/am335x: Fix timer implementation ...................................................................... soc/ti/am335x: Fix timer implementation Implements the monotonic timer using the am335x dmtimer peripheral. Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/soc/ti/am335x/Makefile.inc D src/soc/ti/am335x/dmtimer.c M src/soc/ti/am335x/dmtimer.h D src/soc/ti/am335x/monotonic_timer.c A src/soc/ti/am335x/timer.c 5 files changed, 59 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44383/1 diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index 06ac1ee..f5ebb7a 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -1,17 +1,14 @@ bootblock-y += bootblock.c bootblock-y += bootblock_media.c -bootblock-y += dmtimer.c +bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += pinmux.c -bootblock-y += monotonic_timer.c romstage-y += nand.c romstage-y += cbmem.c -romstage-y += dmtimer.c -romstage-y += monotonic_timer.c +romstage-y += timer.c -ramstage-y += dmtimer.c -ramstage-y += monotonic_timer.c +ramstage-y += timer.c ramstage-y += nand.c ramstage-y += soc.c diff --git a/src/soc/ti/am335x/dmtimer.c b/src/soc/ti/am335x/dmtimer.c deleted file mode 100644 index b3aa7a1..0000000 --- a/src/soc/ti/am335x/dmtimer.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "dmtimer.h" - -void dmtimer_start(int num) -{ -} - -uint64_t dmtimer_raw_value(int num) -{ - return 0; -} diff --git a/src/soc/ti/am335x/dmtimer.h b/src/soc/ti/am335x/dmtimer.h index ad8515f..c2ecb40 100644 --- a/src/soc/ti/am335x/dmtimer.h +++ b/src/soc/ti/am335x/dmtimer.h @@ -5,9 +5,31 @@ #include <stdint.h> -#define OSC_HZ 24000000 +#define M_OSC_MHZ (24) -void dmtimer_start(int num); -uint64_t dmtimer_raw_value(int num); +struct am335x_dmtimer { + uint32_t tidr; + uint8_t res1[12]; + uint32_t tiocp_cfg; + uint8_t res2[12]; + uint32_t irq_eoi; + uint32_t irqstatus_raw; + uint32_t irqstatus; + uint32_t irqenable_set; + uint32_t irqenable_clr; + uint32_t irqwakeen; + uint32_t tclr; + uint32_t tcrr; + uint32_t tldr; + uint32_t ttgr; + uint32_t twps; + uint32_t tmar; + uint32_t tcar1; + uint32_t tsicr; + uint32_t tcar2; +}; + +#define TCLR_ST (0x01 << 0) +#define TCLR_AR (0x01 << 1) #endif diff --git a/src/soc/ti/am335x/monotonic_timer.c b/src/soc/ti/am335x/monotonic_timer.c deleted file mode 100644 index b57258b..0000000 --- a/src/soc/ti/am335x/monotonic_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <delay.h> -#include <timer.h> - -#include "dmtimer.h" - -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint64_t last_value; -} mono_counter; - -static const uint32_t clocks_per_usec = OSC_HZ/1000000; - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t current_tick; - uint64_t usecs_elapsed; - - if (!mono_counter.initialized) { - init_timer(); - mono_counter.last_value = dmtimer_raw_value(0); - mono_counter.initialized = 1; - } - - current_tick = dmtimer_raw_value(0); - usecs_elapsed = (current_tick - mono_counter.last_value) / - clocks_per_usec; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/soc/ti/am335x/timer.c b/src/soc/ti/am335x/timer.c new file mode 100644 index 0000000..58ab811 --- /dev/null +++ b/src/soc/ti/am335x/timer.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <delay.h> +#include <device/mmio.h> + +#include "dmtimer.h" +#include "clock.h" + +struct am335x_dmtimer *dmtimer_2 = (struct am335x_dmtimer *)0x48040000; + +#define CLKSEL_M_OSC (0x01 << 0) + +static uint32_t timer_raw_value(void) +{ + return read32(&dmtimer_2->tcrr); +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / M_OSC_MHZ); +} + +void init_timer(void) +{ + write32(&am335x_cm_dpll->clksel_timer2_clk, CLKSEL_M_OSC); + + // Start the dmtimer in autoreload mode without any prescalers + // With M_OSC at 24MHz, this gives a few minutes before the timer overflows + write32(&dmtimer_2->tclr, TCLR_ST | TCLR_AR); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223 Gerrit-Change-Number: 44383 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/ti/am335x: Enable MMU in bootblock
by Sam Lewis (Code Review) 22 Nov '20

22 Nov '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44382 ) Change subject: soc/ti/am335x: Enable MMU in bootblock ...................................................................... soc/ti/am335x: Enable MMU in bootblock Enables the MMU primarily to allow the unaligned word reads that the FMAP code requires. Without enabling this, the chip gets data access exceptions. Enabling the MMU also gives some advantages in allowing the icache and dcache to be enabled, so is probably worth doing regardless. Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/soc/ti/am335x/bootblock.c M src/soc/ti/am335x/bootblock_media.c M src/soc/ti/am335x/memlayout.ld 3 files changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44382/1 diff --git a/src/soc/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c index 985e1a1..11bc459 100644 --- a/src/soc/ti/am335x/bootblock.c +++ b/src/soc/ti/am335x/bootblock.c @@ -4,13 +4,25 @@ #include <arch/cache.h> #include <bootblock_common.h> +#include <symbols.h> + +#define SRAM_START ((uintptr_t)_sram / MiB) +#define SRAM_END (DIV_ROUND_UP((uintptr_t)_esram, MiB)) + +#define DRAM_START ((uintptr_t)_dram / MiB) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) void bootblock_soc_init(void) { - uint32_t sctlr; + mmu_init(); - /* enable dcache */ - sctlr = read_sctlr(); - sctlr |= SCTLR_C; - write_sctlr(sctlr); + /* Map everything strongly ordered by default */ + mmu_config_range(0, 4096, DCACHE_OFF); + + mmu_config_range(SRAM_START, SRAM_END - SRAM_START, + DCACHE_WRITEBACK); + + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + + dcache_mmu_enable(); } diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c index 1c65c38..b7e49a6 100644 --- a/src/soc/ti/am335x/bootblock_media.c +++ b/src/soc/ti/am335x/bootblock_media.c @@ -3,7 +3,6 @@ #include <boot_device.h> #include <symbols.h> -/* FIXME: No idea how big the internal SRAM actually is. */ static const struct mem_region_device boot_dev = MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 991e401..16770a5 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -8,17 +8,16 @@ { SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) - FMAP_CACHE(0x4030b400, 2K) + FMAP_CACHE(0x402f0400+20K, 2K) + TTB(0x402F8000, 16K) + ROMSTAGE(0x402F8000+16K, 40K) + STACK(0x4030be00, 4K) SRAM_END(0x40310000) DRAM_START(0x80000000) RAMSTAGE(0x80200000, 192K) - /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x81000000, 16K) - #ifdef OMAP_HEADER .header : { *(.header); @@ -26,6 +25,6 @@ /DISCARD/ : { *(*) - } +} #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/44382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Gerrit-Change-Number: 44382 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/ocp/deltalake: Override SMBIOS type 4 cpu voltage
by Tim Chu (Code Review) 22 Nov '20

22 Nov '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47562 ) Change subject: mb/ocp/deltalake: Override SMBIOS type 4 cpu voltage ...................................................................... mb/ocp/deltalake: Override SMBIOS type 4 cpu voltage Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/47562/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9d57090..d48f85e 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -59,6 +59,12 @@ return slot_id_str; } +/* Override SMBIOS type 4 cpu voltage */ +unsigned int smbios_cpu_get_voltage(void) +{ + return 0x90; /* This will return 1.6V which is expected value for Delta Lake */ +} + /* System Slot Socket, Stack, Type and Data bus width Information */ typedef struct { u8 stack; -- To view, visit https://review.coreboot.org/c/coreboot/+/47562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Gerrit-Change-Number: 47562 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: cpu/intel/common: Fill cpu voltage in SMBIOS tables
by Patrick Rudolph (Code Review) 22 Nov '20

22 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43904 ) Change subject: cpu/intel/common: Fill cpu voltage in SMBIOS tables ...................................................................... cpu/intel/common: Fill cpu voltage in SMBIOS tables Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc A src/cpu/intel/common/voltage.c M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/include/smbios.h M src/soc/intel/common/block/cpu/Kconfig 8 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43904/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 9a7029b..8600fba 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -575,6 +575,12 @@ return 0; /* Unknown */ } +/* Returns the processor voltage in 100mV units */ +unsigned int __weak smbios_cpu_get_voltage(void) +{ + return 0; /* Unknown */ +} + const char *__weak smbios_system_sku(void) { return ""; @@ -748,6 +754,9 @@ t->max_speed = smbios_cpu_get_max_speed_mhz(); t->current_speed = smbios_cpu_get_current_speed_mhz(); } + if (smbios_cpu_get_voltage() > 0) + t->voltage = 0x80 | smbios_cpu_get_voltage(); + *current += len; return len; } diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 0f2a652..1e8bb6c 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,6 +22,9 @@ config CPU_INTEL_COMMON_TIMEBASE bool +config CPU_INTEL_COMMON_VOLTAGE + bool + config CPU_INTEL_COMMON_HYPERTHREADING bool diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 1612012..0dda339 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,6 @@ ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/voltage.c b/src/cpu/intel/common/voltage.c new file mode 100644 index 0000000..82765b0 --- /dev/null +++ b/src/cpu/intel/common/voltage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/msr.h> +#include <smbios.h> + +/* This is not an architectural MSR. */ +#define MSR_PERF_STATUS 0x198 + +#if CONFIG(GENERATE_SMBIOS_TABLES) +unsigned int smbios_cpu_get_voltage(void) +{ + return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192; +} +#endif diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 54cb99f..127ae82 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -22,6 +22,7 @@ select PARALLEL_MP select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select CPU_INTEL_COMMON_VOLTAGE config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 39beb22..6cb2e4c 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,6 +19,7 @@ select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE + select CPU_INTEL_COMMON_VOLTAGE select PARALLEL_MP config SMM_TSEG_SIZE diff --git a/src/include/smbios.h b/src/include/smbios.h index 25ea897..48a4de4 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -40,6 +40,7 @@ unsigned int smbios_cpu_get_max_speed_mhz(void); unsigned int smbios_cpu_get_current_speed_mhz(void); +unsigned int smbios_cpu_get_voltage(void); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 3c29b24..70343fc 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_CPU bool + select CPU_INTEL_COMMON_VOLTAGE default n help This option selects Intel Common CPU Model support code -- To view, visit https://review.coreboot.org/c/coreboot/+/43904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Gerrit-Change-Number: 43904 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 24

Change in coreboot[master]: util/docker: Minor Makefile updates
by Martin Roth (Code Review) 22 Nov '20

22 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47342 ) Change subject: util/docker: Minor Makefile updates ...................................................................... util/docker: Minor Makefile updates - Update url for docker install instructions. - Update docker-cleanall target to require verification. - Update docker-jenkins-attach target to check for docker and use docker variable. - Update spaces to tabs in the docs targets. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ic1e1a545024fe1fdc37d7d8c7e6f54f124d1697b --- M util/docker/Makefile 1 file changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47342/1 diff --git a/util/docker/Makefile b/util/docker/Makefile index eaa26e1..8b1d0ef 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -31,8 +31,8 @@ test-docker: $(if $(DOCKER),,\ - $(warning Docker command not found. Please install docker) \ - $(warning https://docs.docker.com/engine/installation ) \ + $(warning Error: Docker command not found. Please install docker) \ + $(warning Instructions: https://docs.docker.com/engine/install/ ) \ $(error halting)) test-docker-login: test-docker @@ -82,14 +82,19 @@ docker-clean: clean-coreboot-containers @$(MAKE) clean-coreboot-images -docker-cleanall: +docker-cleanall: test-docker +ifeq($(Y),1) @if [ -n "$$($(DOCKER) ps -a | grep -v "CONTAINER")" ]; then \ - $(DOCKER) kill $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ + $(DOCKER) kill $$($(DOCKER) ps | grep -v "CONTAINER" | sed 's|\s.*$$||') ; \ $(DOCKER) rm $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ fi @if [ -n "$$($(DOCKER) images | grep -v "REPOSITORY")" ]; then \ $(DOCKER) rmi $$($(DOCKER) images | grep -v "REPOSITORY" | tr -s ' ' | cut -f3 -d ' '); \ fi +else + echo "This will remove *ALL* docker containers from your machine." + echo "If this is what you want, run 'make docker-cleanall Y=1'" +endif $(DOCKER_CCACHE): @mkdir -p $@ @@ -153,8 +158,8 @@ /bin/bash -l docker-jenkins-attach: USER=root -docker-jenkins-attach: - docker exec --user $(USER) \ +docker-jenkins-attach: test-docker + $(DOCKER) exec --user $(USER) \ -e COLUMNS=$(shell tput cols) -e LINES=$(shell tput lines) -e TERM=$(TERM) \ -it "$$(docker ps | grep coreboot-jenkins-node | cut -f1 -d' ')" \ /bin/bash -l @@ -162,16 +167,16 @@ docker-build-docs: test-docker docker-build-docs: $(DOCKER) run -it --rm \ - --user $(UID):$(GID) \ - -v "$(top)/:/data-in/:ro" \ - -v "$(top)/Documentation/_build/:/data-out/" \ - doc.coreboot.org + --user $(UID):$(GID) \ + -v "$(top)/:/data-in/:ro" \ + -v "$(top)/Documentation/_build/:/data-out/" \ + doc.coreboot.org docker-livehtml-docs: test-docker docker-livehtml-docs: $(DOCKER) run -it --rm \ - --net=host -v "$(top)/:/data-in/:ro" \ - doc.coreboot.org livehtml + --net=host -v "$(top)/:/data-in/:ro" \ + doc.coreboot.org livehtml help: @echo "Commands for working with docker images:" -- To view, visit https://review.coreboot.org/c/coreboot/+/47342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1e1a545024fe1fdc37d7d8c7e6f54f124d1697b Gerrit-Change-Number: 47342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/puff/var/dooly: update USB2 type-c strength
by Tony Huang (Code Review) 22 Nov '20

22 Nov '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47687 ) Change subject: mb/google/puff/var/dooly: update USB2 type-c strength ...................................................................... mb/google/puff/var/dooly: update USB2 type-c strength Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47687/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 6e23448..efa7d71 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -27,7 +27,14 @@ .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -37,7 +44,14 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" -- To view, visit https://review.coreboot.org/c/coreboot/+/47687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Gerrit-Change-Number: 47687 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/amd/pi: Remove 00660F01 directory & files
by Martin Roth (Code Review) 22 Nov '20

22 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47649 ) Change subject: nb/amd/pi: Remove 00660F01 directory & files ...................................................................... nb/amd/pi: Remove 00660F01 directory & files These files are not used by any platform, so remove them. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d --- D src/northbridge/amd/pi/00660F01/Kconfig D src/northbridge/amd/pi/00660F01/Makefile.inc D src/northbridge/amd/pi/00660F01/acpi/northbridge.asl D src/northbridge/amd/pi/00660F01/chip.h D src/northbridge/amd/pi/00660F01/dimmSpd.c D src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc 7 files changed, 0 insertions(+), 1,187 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47649/1 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig deleted file mode 100644 index e42ba80..0000000 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config NORTHBRIDGE_AMD_PI_00660F01 - bool - select RESOURCE_ALLOCATOR_V3 - -if NORTHBRIDGE_AMD_PI_00660F01 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MMCONF_BASE_ADDRESS - hex - default 0xF8000000 - -config MMCONF_BUS_NUMBER - int - default 64 - -config VGA_BIOS_ID - string - default "1002,9870" - help - The default VGA BIOS PCI vendor/device ID should be set to the - result of the map_oprom_vendev() function in northbridge.c. - -config VGA_BIOS_FILE - string - default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" - -endif diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc deleted file mode 100644 index 7fd37f2..0000000 --- a/src/northbridge/amd/pi/00660F01/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += dimmSpd.c - -ramstage-y += northbridge.c diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl deleted file mode 100644 index ada775d..0000000 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Note: Only need HID on Primary Bus */ -External (TOM1) -External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - -/* Describe the Northbridge devices */ - -Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ -{ - Return(Zero) -} - -Method(_STA, 0, NotSerialized) -{ - Return(0x0B) /* Status is visible */ -} - -Method(_PRT,0, NotSerialized) -{ - If(PMOD) - { - Return(APR0) /* APIC mode */ - } - Return (PR0) /* PIC Mode */ -} - -Device(AMRT) { - Name(_ADR, 0x00000000) -} /* end AMRT */ - -/* Gpp 0 */ -Device(PBR4) { - Name(_ADR, 0x00020001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR4 */ - -/* Gpp 1 */ -Device(PBR5) { - Name(_ADR, 0x00020002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR5 */ - -/* Gpp 2 */ -Device(PBR6) { - Name(_ADR, 0x00020003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR6 */ - -/* Gpp 3 */ -Device(PBR7) { - Name(_ADR, 0x00020004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR7 */ - -/* Gpp 4 */ -Device(PBR8) { - Name(_ADR, 0x00020005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS8) } /* APIC mode */ - Return (PS8) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 1 */ -Device(PBR9) { - Name(_ADR, 0x00030002) -} /* end PBR8 */ - -/* GFX 2 */ -Device(PBRA) { - Name(_ADR, 0x00030003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 3 */ -Device(PBRB) { - Name(_ADR, 0x00030004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSB) } /* APIC mode */ - Return (PSB) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 4 */ -Device(PBRC) { - Name(_ADR, 0x00030005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSC) } /* APIC mode */ - Return (PSC) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } -} /* end AZHD */ diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h deleted file mode 100644 index 1cc7f69..0000000 --- a/src/northbridge/amd/pi/00660F01/chip.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _PI_FAM15CZ_CHIP_H_ -#define _PI_FAM15CZ_CHIP_H_ - -struct northbridge_amd_pi_00660F01_config -{ - u8 spdAddrLookup[2][2][4]; -}; - -#endif diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c deleted file mode 100644 index 0a1281f..0000000 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_def.h> -#include <device/device.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> -#include <AGESA.h> -#include "chip.h" -#include <northbridge/amd/pi/dimmSpd.h> - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress; - DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); - - if (dev == NULL) - return AGESA_ERROR; - - DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; - - if (config == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) - return AGESA_ERROR; - spdAddress = config->spdAddrLookup - [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) - return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); - if (err) - return AGESA_ERROR; - return AGESA_SUCCESS; -} diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c deleted file mode 100644 index 09bdd82..0000000 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ /dev/null @@ -1,945 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/pci_ops.h> -#include <acpi/acpi.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <string.h> -#include <lib.h> -#include <cpu/cpu.h> -#include <Porting.h> -#include <AGESA.h> -#include <Topology.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/msr.h> -#include <cpu/amd/mtrr.h> -#include <acpi/acpigen.h> -#include <northbridge/amd/pi/nb_common.h> -#include <northbridge/amd/agesa/agesa_helper.h> - -#define MAX_NODE_NUMS MAX_NODES - -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - -static unsigned int node_nums; -static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; -static unsigned int fx_devs = 0; - -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg + 4, tempreg); - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } - printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -static u32 amdfam15_nodeid(struct device *dev) -{ - return (dev->path.pci.devfn >> 3) - DEV_CDB; -} - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid << 4) | (linkn<<12); - /* it will routing - * (1)mmio 0xa0000:0xbffff - * (2)io 0x3b0:0x3bb, 0x3c0:0x3df - */ - f1_write_config32(0xf4, val); - -} - -/** - * @return - * @retval 2 resource does not exist, usable - * @retval 0 resource exists, not usable - * @retval 1 resource exist, resource has been allocated before - */ -static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, - unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - - if (!res) - result = 2; - else if ((goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - else - result = 0; - - return result; -} - -static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result >= 1) { - free_reg = reg; - } - if (result == 1) { - /* resource allocated */ - break; - } - } - resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); - return resource; -} - -static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result >= 1) { - free_reg = reg; - } - if (result == 1) { - /* I have been allocated this one */ - break; - } - } - resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); - return resource; -} - -static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam15_find_iopair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - -} - -static void read_resources(struct device *dev) -{ - u32 nodeid; - struct bus *link; - - nodeid = amdfam15_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam15_link_read_bases(dev, nodeid, link->link_num); - } - } - - /* - * This MMCONF resource must be reserved in the PCI domain. - * It is not honored by the coreboot resource allocator if it is in - * the CPU_CLUSTER. - */ - mmconf_resource(dev, MMIO_CONF_BASE); -} - -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) - return; - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) - return; - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) - return; - - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void create_vga_resource(struct device *dev, unsigned int nodeid) -{ - struct bus *link; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); - set_vga_enable_reg(nodeid, sblink); -} - -static void set_resources(struct device *dev) -{ - unsigned int nodeid; - struct bus *bus; - struct resource *res; - - /* Find the nodeid */ - nodeid = amdfam15_nodeid(dev); - - /* do we need this? */ - create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } -} - -static void northbridge_init(struct device *dev) -{ -} - -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); - - return (unsigned long)current; -} - -static void northbridge_fill_ssdt_generator(const struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - -static void patch_ssdt_processor_scope(acpi_header_t *ssdt) -{ - unsigned int len = ssdt->length - sizeof(acpi_header_t); - unsigned int i; - - for (i = sizeof(acpi_header_t); i < len; i++) { - /* Search for _PR_ scope and replace it with _SB_ */ - if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) - *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; - } - /* Recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); -} - -static unsigned long agesa_write_acpi_tables(const struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *alib; - acpi_header_t *ivrs; - acpi_hest_t *hest; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; - - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } else { - printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } else { - printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); - } - - /* ALIB */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); - if (alib != NULL) { - memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *) current; - current += alib->length; - acpi_add_table(rsdp, (void *)alib); - } - else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); - } - - /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - patch_ssdt_processor_scope(ssdt); - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - return current; -} - -static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, -}; - -static const struct pci_driver family15_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, -}; - -static void fam15_finalize(void *chip_info) -{ - struct device *dev; - u32 value; - dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = pcidev_on_root(1, 1); - if (dev != NULL) { - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); - } -} - -struct chip_operations northbridge_amd_pi_00660F01_ops = { - CHIP_NAME("AMD FAM15 Northbridge") - .enable_dev = 0, - .final = fam15_finalize, -}; - -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg += 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - -static void domain_enable_resources(struct device *dev) -{ -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -struct hw_mem_hole_info { - unsigned int hole_startk; - int node_id; -}; -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { - /* we find the hole */ - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id == -1) { - resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) - continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k > 4 *1024 * 1024) break; // don't need to go to check - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G - mem_hole.node_id = i; - break; //only one hole - } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } - return mem_hole; -} -#endif - -static void domain_set_resources(struct device *dev) -{ - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - * MMIO hole. If you fix this here, please fix amdk8, too. - */ - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - } -#endif - - idx = 0x10; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) - continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - uint64_t topmem2 = bsp_topmem2(); - basek = 4*1024*1024; - sizek = topmem2/1024 - basek; - } - } - - ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); - } - - add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -} - -static const char *domain_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - return NULL; -} - -static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, - .scan_bus = pci_domain_scan_bus, - .acpi_name = domain_acpi_name, -}; - -static void sysconf_init(struct device *dev) // first node -{ - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] -} - -static void cpu_bus_scan(struct device *dev) -{ - struct bus *cpu_bus; - struct device *dev_mc; - int i,j; - int coreid_bits; - int core_max = 0; - unsigned int ApicIdCoreIdSize; - unsigned int core_nums; - int siblings = 0; - unsigned int family; - u32 modules = 0; - int ioapic_count = 0; - - /* For binaryPI there is no multiprocessor configuration, the number of - * modules will always be 1. */ - modules = 1; - ioapic_count = CONFIG_NUM_OF_IOAPICS; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - struct device *cdb_dev; - unsigned int devn; - struct bus *pbus; - - devn = DEV_CDB + i; - pbus = dev_mc->bus; - - /* Find the cpu's pci device */ - cdb_dev = pcidev_on_root(devn, 0); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = pcidev_on_root(devn, 0); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 4); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 6 || family == 7) { - /* f15 and f16 */ - cdb_dev = pcidev_on_root(devn, 5); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - /* default one core */ - siblings = 0; - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - u32 lapicid_start = 0; - - /* - * APIC ID calculation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply APIC enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - if ((node_nums * core_max) + ioapic_count >= 0x10) { - lapicid_start = (ioapic_count - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); - } - u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", - i, j, apic_id); - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } -} - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, -}; - -static void root_complex_enable_dev(struct device *dev) -{ - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { - CHIP_NAME("AMD FAM16 Root Complex") - .enable_dev = root_complex_enable_dev, -}; - -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); - - return new_vendev; -} diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 7c66b56..0cdf326 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -4,6 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Gerrit-Change-Number: 47649 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/google/volteer/var/terrador: Remove unuse devices
by David Wu (Code Review) 22 Nov '20

22 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47690 ) Change subject: mb/google/volteer/var/terrador: Remove unuse devices ...................................................................... mb/google/volteer/var/terrador: Remove unuse devices Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade --- M src/mainboard/google/volteer/variants/terrador/overridetree.cb 1 file changed, 0 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47690/1 diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index c3b5df7..9d659a6 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -101,21 +101,6 @@ end device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end - end - chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" @@ -130,38 +115,6 @@ device i2c 10 on end end end - device ref i2c2 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR0 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "0" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end device ref i2c5 on chip drivers/i2c/hid register "generic.hid" = ""ELAN2700"" -- To view, visit https://review.coreboot.org/c/coreboot/+/47690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Gerrit-Change-Number: 47690 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/kontron/bsl6/dsdt.asl: Use macro for DSDT revision
by HAOUAS Elyes (Code Review) 22 Nov '20

22 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46353 ) Change subject: mb/kontron/bsl6/dsdt.asl: Use macro for DSDT revision ...................................................................... mb/kontron/bsl6/dsdt.asl: Use macro for DSDT revision Change-Id: I9f09023a3e02635c7379299fcbb85b6cea432cfe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/kontron/bsl6/dsdt.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46353/1 diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl index 225c8a5..3be5115 100644 --- a/src/mainboard/kontron/bsl6/dsdt.asl +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 -- To view, visit https://review.coreboot.org/c/coreboot/+/46353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f09023a3e02635c7379299fcbb85b6cea432cfe Gerrit-Change-Number: 46353 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: crossgcc: Upgrade nasm to version 2.15.04
by HAOUAS Elyes (Code Review) 22 Nov '20

22 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44694 ) Change subject: crossgcc: Upgrade nasm to version 2.15.04 ...................................................................... crossgcc: Upgrade nasm to version 2.15.04 Changes: https://nasm.us/doc/nasmdocc.html "Correct the encoding of the ENQCMDS and TILELOADT1 instructions. Fix case where the COFF backend (the coff, win32 and win64 output formats) would add padding bytes in the middle of a section if a SECTION/SEGMENT directive was provided which repeated an ALIGN= attribute. This neither matched legacy behavior, other backends, or user expectations. Fix SSE instructions not being recognized with an explicit memory operation size (e.g. movsd qword [eax],xmm0)." Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum A util/crossgcc/sum/nasm-2.15.04.tar.bz2.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44694/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f9cac5..4e23f8d 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -46,7 +46,7 @@ # CLANG version number CLANG_VERSION=10.0.1 CMAKE_VERSION=3.18.1 -NASM_VERSION=2.15.03 +NASM_VERSION=2.15.04 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum deleted file mode 100644 index 6033fae..0000000 --- a/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -513ac3b800377f10833a02bc7f3fa8b84ca4f2b6 tarballs/nasm-2.15.03.tar.bz2 diff --git a/util/crossgcc/sum/nasm-2.15.04.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.04.tar.bz2.cksum new file mode 100644 index 0000000..0bbb229 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.15.04.tar.bz2.cksum @@ -0,0 +1 @@ +062aa2dea69fcb8a2b3f387e349a80531f70475c tarballs/nasm-2.15.04.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509 Gerrit-Change-Number: 44694 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020