coreboot-gerrit November 2020

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Change in coreboot[master]: Doc/releases/checklist.md: Fix up URLs
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47812 ) Change subject: Doc/releases/checklist.md: Fix up URLs ...................................................................... Doc/releases/checklist.md: Fix up URLs Use angle brackets so that they appear as links, and update a link to a Gerrit change to use the current format. Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/releases/checklist.md 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47812/1 diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 1cfb110..d777f0e 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -198,16 +198,16 @@ ```` People can now see the release tarballs on the website at -https://www.coreboot.org/releases/ +<https://www.coreboot.org/releases/> -The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at https://review.coreboot.org/cgit/homepage.git/tree/downloads.html +The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html> -Here is an example commit to change it: https://review.coreboot.org/#/c/19515/ +Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515> ## Upload crossgcc sources Sometimes the source files for older revisions of crossgcc disappear. To deal with that we maintain a mirror at -https://www.coreboot.org/releases/crossgcc-sources/ where we host the +<https://www.coreboot.org/releases/crossgcc-sources/> where we host the sources used by the crossgcc scripts that are part of coreboot releases. Run @@ -221,7 +221,7 @@ directory on the server. ## After the release is complete -Post the release notes on https://blogs.coreboot.org +Post the release notes on <https://blogs.coreboot.org> ## Making a branch At times we will need to create a branch, generally for patch fixes. -- To view, visit https://review.coreboot.org/c/coreboot/+/47812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Gerrit-Change-Number: 47812 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/releases/checklist.md: Add reminder to unpack relnotes
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47811 ) Change subject: Doc/releases/checklist.md: Add reminder to unpack relnotes ...................................................................... Doc/releases/checklist.md: Add reminder to unpack relnotes Explicitly add this easy-to-forget step. Also add a missing period. Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/releases/checklist.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47811/1 diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index a80fd85..1cfb110 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -75,7 +75,8 @@ - [ ] Test the release from the actual release tarballs. - [ ] Push signed Tag to repo. - [ ] Announce that the release tag is done on IRC. -- [ ] Upload release files to web server +- [ ] Upload release files to web server. +- [ ] Also extract the release notes and place them on the web server. - [ ] Upload crossgcc sources to web server. - [ ] Update download page to point to files, push to repo. - [ ] Write and publish blog post with release notes. -- To view, visit https://review.coreboot.org/c/coreboot/+/47811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Gerrit-Change-Number: 47811 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external: Fix up SPDX license headers
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47815 ) Change subject: payloads/external: Fix up SPDX license headers ...................................................................... payloads/external: Fix up SPDX license headers Remove copyright notices and other unnecessary churn. Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile M payloads/external/LinuxBoot/targets/linux.mk M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.inc M payloads/external/Memtest86Plus/Makefile M payloads/external/U-Boot/Makefile M payloads/external/Yabits/Makefile M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile M payloads/external/tianocore/Makefile 12 files changed, 0 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/47815/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 6171217..c2689e1 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only if PAYLOAD_LINUXBOOT diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index 0138732..4d3decd 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -1,6 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only config PAYLOAD_LINUXBOOT diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 45b1764..c91b1d4 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=linuxboot diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 5dec401..9906729 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only SHELL := /bin/bash diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 07c453d..0cf91fe 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=$(shell pwd)/linuxboot diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 0300581..823cd87 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -1,10 +1,3 @@ -################################################################################ -## -## -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # set up payload config and version files for later inclusion diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 5aec5c8..3853cb9 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_MEMTEST_MASTER)=origin/master diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 6d186ad..38dfe99 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2015 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019-4 tag diff --git a/payloads/external/Yabits/Makefile b/payloads/external/Yabits/Makefile index 74f00ef..adac77e 100644 --- a/payloads/external/Yabits/Makefile +++ b/payloads/external/Yabits/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_YABITS_MASTER)=origin/master diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 0b81d18..6c8049a 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config PXE diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 2a9e8c9..3e12f61 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019.3 - Last commit of March 2019 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 9945411..3d3a3dd 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2017 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # force the shell to bash - the edksetup.sh script doesn't work with dash -- To view, visit https://review.coreboot.org/c/coreboot/+/47815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858 Gerrit-Change-Number: 47815 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external/Makefile.inc: Fix regressions
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47814 ) Change subject: payloads/external/Makefile.inc: Fix regressions ...................................................................... payloads/external/Makefile.inc: Fix regressions Fixes: 14ca7407196 (Makefile.inc: Move adding SeaBIOS cbfs config files) Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47814/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 6208578..0300581 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -121,14 +121,14 @@ INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" -# $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" - $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads + $(CBFSTOOL) $< add-int -i 2 -n etc/threads endif # Depthcharge -- To view, visit https://review.coreboot.org/c/coreboot/+/47814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a Gerrit-Change-Number: 47814 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Patrick Georgi (Code Review) 22 Nov '20

22 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... mb/kontron: Add Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/kontron/mal10.md A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc A src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt A src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c A src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h A src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/mal10/Makefile.inc A src/mainboard/kontron/mal10/variants/mal10/board_info.txt A src/mainboard/kontron/mal10/variants/mal10/data.vbt A src/mainboard/kontron/mal10/variants/mal10/devicetree.cb A src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/variants/mal10/gpio.c A src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h 26 files changed, 961 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d6aed22..4b46b7c 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -76,6 +76,10 @@ - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Kontron + +- [mAL-10](kontron/mal10.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md new file mode 100644 index 0000000..b2eefc3 --- /dev/null +++ b/Documentation/mainboard/kontron/mal10.md @@ -0,0 +1,106 @@ +# Kontron mAL10 Computer-on-Modules platform + +The Kontron [mAL10] COMe is a credit card sized Computer-on-Modules +platform based on the Intel Atom E3900 Series, Pentium and Celeron +processors. + +## Technology + +```eval_rst ++------------------+----------------------------------+ +| COMe Type | mini pin-out type 10 | ++------------------+----------------------------------+ +| SoC | Intel Atom x5-E3940 (4 core) | ++------------------+----------------------------------+ +| GPU | Intel HD Graphics 500 | ++------------------+----------------------------------+ +| Coprocessor | Intel TXE 3.0 | ++------------------+----------------------------------+ +| RAM | 8GB DDR3L | ++------------------+----------------------------------+ +| eMMC Flash | 32GB eMMC pSLC | ++------------------+----------------------------------+ +| USB3 | x2 | ++------------------+----------------------------------+ +| USB2 | x6 | ++------------------+----------------------------------+ +| SATA | x2 | ++------------------+----------------------------------+ +| LAN | Intel I210IT, I211AT | ++------------------+----------------------------------+ +| Super IO/EC | Kontron CPLD/EC | ++------------------+----------------------------------+ +| HWM | NCT7802 | ++------------------+----------------------------------+ +``` + +## Building coreboot + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.kontron_mal10 +make +``` +## Payloads +- SeaBIOS +- Tianocore +- Linux as payload + +## Flashing coreboot + +The SPI flash can be accessed internally using [flashrom]. +The following command is used to flash BIOS region. + +```bash +$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all +``` + +## Hardware Monitor + +The Nuvoton [NCT7802Y] is a hardware monitoring IC, capable of monitor critical +system parameters including power supply voltages, fan speeds, and temperatures. +The remote inputs can be connected to CPU/GPU thermal diode or any thermal diode +sensors and thermistor. + +- 6 temperature sensors; +- 5 voltage sensors; +- 3 fan speed sensors; +- 4 sets of temperature setting points. + +PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU +temperature value is taken from a thermal resistor (NTC) that is placed very +close to the CPU. + +## Known issues + +- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 + Booting with the "CorebootPayload" [crashes]. +- Tianocore outputs video through an external GPU only. + +## Untested + +- IGD/LVDS +- SDIO + +## Tested and working + +- Kontron CPLD/EC (Serial ports, I2C port) +- NCT7802 [HWM](#Hardware Monitor) +- USB2/3 +- Gigabit Ethernet ports +- eMMC +- SATA +- PCIe ports +- IGD/DP + +## TODO +- Onboard audio (codec IDT 92HD73C1X5, currently disabled) +- S3 suspend/resume + +[mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-… +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.p… +[flashrom]: https://flashrom.org/Flashrom +[NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-… +[crashes]: https://pastebin.com/cpCfrPCL diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig new file mode 100644 index 0000000..1705b91 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig @@ -0,0 +1,58 @@ +if BOARD_KONTRON_COME_MAL10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_CRB_TPM + select EC_KONTRON_KEMPLD + select DRIVERS_I2C_NCT7802Y + +config MAINBOARD_DIR + string + default "kontron/mal10" + +# TODO: Add a new carrier boards here +choice + prompt "Carrier board" + default BOARD_KONTRON_T10_TNI + help + This option sets the type of carrier board to be used with + the Kontron mAL10 COMe module. + +config BOARD_KONTRON_T10_TNI + bool "Kontron i-T10-TNIx" + help + By selecting this option, the target ROM image will be built for + the Kontron Ref.Carrier-i T10-TNI carrier board. + +endchoice + +config VARIANT_DIR + string + default "mal10" + +config CARRIER_DIR + string + default "t10-tni" if BOARD_KONTRON_T10_TNI + +config MAINBOARD_PART_NUMBER + string + default "COMe-mAL10" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "carriers/$(CONFIG_CARRIER_DIR)/overridetree.cb" + +endif diff --git a/src/mainboard/kontron/mal10/Kconfig.name b/src/mainboard/kontron/mal10/Kconfig.name new file mode 100644 index 0000000..ac54165 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_KONTRON_COME_MAL10 + bool "COMe-mAL10" diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc new file mode 100644 index 0000000..885786f --- /dev/null +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += carriers/$(CARRIER_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/carriers/$(CARRIER_DIR)/include diff --git a/src/mainboard/kontron/mal10/acpi/dptf.asl b/src/mainboard/kontron/mal10/acpi/dptf.asl new file mode 100644 index 0000000..240da45 --- /dev/null +++ b/src/mainboard/kontron/mal10/acpi/dptf.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/kontron/mal10/board_info.txt b/src/mainboard/kontron/mal10/board_info.txt new file mode 100644 index 0000000..d93d125 --- /dev/null +++ b/src/mainboard/kontron/mal10/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/bootblock.c b/src/mainboard/kontron/mal10/bootblock.c new file mode 100644 index 0000000..5c40e2d --- /dev/null +++ b/src/mainboard/kontron/mal10/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <intelblocks/lpc_lib.h> +#include <ec/kontron/kempld/kempld.h> +#include <variant/gpio.h> + +static void init_cpld(void) +{ + /* Set up LPC decoding for CPLD I/O port ranges */ + lpc_open_pmio_window(0x0A80, 2); + + /* Enable console serial ports */ + lpc_io_setup_comm_a_b(); + kempld_enable_uart_for_console(); +} + +void bootblock_mainboard_early_init(void) +{ + variant_early_gpio_configure(); + init_cpld(); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc new file mode 100644 index 0000000..c291d45 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += gpio.c diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt new file mode 100644 index 0000000..2902dc4 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-Ref-Carrier-i-T10-TNI +Board URL: https://www.kontron.com/products/boards-and-standard-form-factors/com-expre… +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c new file mode 100644 index 0000000..f1f93bf --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/carrier/gpio.h" + +static const struct pad_config gpio_table[] = { + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_5, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_6, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_7, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_8, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_9, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_10, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_11, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_12, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_13, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_14, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_17, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_19, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_20, DN_20K, DEEP, OFF, TxDRxE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, DRIVER), + /* GPIO_22 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_22, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_23 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_23, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE : PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_23, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_24 - GPIO (DW0: 0x40800102, DW1: 0x00027100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, LEVEL, TxDRxE, DISPUPD, ACPI), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_24, + PAD_RESET(DEEP) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5), + PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), + PAD_CFG_GPIO_BIDIRECT(GPIO_28, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_29, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_30, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_31, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_32, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_33, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_34, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_35, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_36, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_37, DN_20K, DEEP, HIZCRx0, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_38, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_39, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_40, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_41, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_48, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_49, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPIO_62, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_63, 0, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_64, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_65, 0, NONE, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_66, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_67, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_68, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_69, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_70, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_71, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_72, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_73, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP), + PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, UP_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_189, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_190, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_191, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_192, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_193, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_194, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_195, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_197, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_198, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_199, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_PWRGOOD, NONE, DEEP, NF1), + PAD_CFG_NF(PMIC_RESET_B, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_213, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_214, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_215, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_STDBY, DN_20K, DEEP, NF1), + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_74, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_75, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_76, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_77, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_78, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_79, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_80, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_81, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_82, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_83, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2), + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_88, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_89, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_90, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_91, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_92, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_104, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_105, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_106, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_109, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_110, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_111, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_112, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_113, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_116, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_117, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_118, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_119, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_120, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_121, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_122, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_123, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_124, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_125, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_126, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_127, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_128, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_129, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_130, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_131, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_132, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_133, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_134, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_135, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_137, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_138, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_139, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_146, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_147, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_148, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_149, DN_20K, DEEP, NF3), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_150, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_151, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_152, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_153, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_154, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_155, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_209, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_AC_PRESENT, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S3_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S4_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SUSCLK, NONE, DEEP, NF1), + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUS_STAT_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUSPWRDNACK, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_205, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_206, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_207, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_208, NONE, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_166, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_167, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_168, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_169, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_170, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_171, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER), + PAD_CFG_NF_IOSSTATE(GPIO_178, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void carrier_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h new file mode 100644 index 0000000..9c9c8ed --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef T10_TNI_CFG_GPIO_H +#define T10_TNI_CFG_GPIO_H + +#include <gpio.h> +#include <stddef.h> + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void carrier_gpio_configure(void); + +#endif /* T10_TNI_CFG_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb new file mode 100644 index 0000000..9248c0c2 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC1)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "usb3_port[1]" = "PORT_EN(OC0)" + + device domain 0 on + device pci 0e.0 off end # TODO: Audio + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "0" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "0" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "0" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "0" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "1" + end + end +end diff --git a/src/mainboard/kontron/mal10/cmos.default b/src/mainboard/kontron/mal10/cmos.default new file mode 100644 index 0000000..55cac79 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.default @@ -0,0 +1,6 @@ +baud_rate = 115200 +debug_level = Info +power_on_after_fail = Enable +boot_devices = (hd0,0);(hd1,0) +boot_default = 0xff +cmos_defaults_loaded = No diff --git a/src/mainboard/kontron/mal10/cmos.layout b/src/mainboard/kontron/mal10/cmos.layout new file mode 100644 index 0000000..cc5359f --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.layout @@ -0,0 +1,55 @@ +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/mal10/dsdt.asl b/src/mainboard/kontron/mal10/dsdt.asl new file mode 100644 index 0000000..78d2c28 --- /dev/null +++ b/src/mainboard/kontron/mal10/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB) + { + Device(PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + } + #include "acpi/dptf.asl" + #include <soc/intel/apollolake/acpi/dptf.asl> + #include <soc/intel/common/acpi/dptf/dptf.asl> + } +} diff --git a/src/mainboard/kontron/mal10/mal10.fmd b/src/mainboard/kontron/mal10/mal10.fmd new file mode 100644 index 0000000..21d780a --- /dev/null +++ b/src/mainboard/kontron/mal10/mal10.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC 0x1000 + SI_BIOS 0xefe000 { + IFWI 0x2ff000 + OBB 0xbff000 { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + CONSOLE 0x20000 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 + } +} diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c new file mode 100644 index 0000000..48194e6 --- /dev/null +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <carrier/gpio.h> +#include <stddef.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + carrier_gpio_configure(); + + /* + * CPU Power Management Configuration correspond to the BIOS Setup menu settings + * in the AMI UEFI v112. + * TODO: move these FSP options to device tree + */ + silconfig->EnableCx = 1; /* Enable CPU power states */ + silconfig->C1e = 1; /* enable Enhanced C-states */ + /* + * Attention! Do not change PkgCStateLimit! This causes spikes in the power + * consumption of the SoC when the system comes out of power saving mode, and + * voltage sagging at the output of DC-DC converters on the COMe module. In the + * AMI BIOS Setup shows this parameter, but does not allow changing it. + */ + silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */ + silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */ + silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */ + silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */ + silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */ + silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */ + silconfig->PmSupport = 1; /* GT PM Support */ + silconfig->EnableRenderStandby = 1; /* enable render standby */ + silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */ + silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */ + + /* Override High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* Override APIC options */ + silconfig->IoApicId = 1; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; +} diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c new file mode 100644 index 0000000..9f1d7eb --- /dev/null +++ b/src/mainboard/kontron/mal10/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/romstage.h> +#include <FspmUpd.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.Profile = 0x19; + mupd->FspmConfig.MemoryDown = 0; + mupd->FspmConfig.DDR3LPageSize = 2; + mupd->FspmConfig.DualRankSupportEnable = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.DIMM0SPDAddress = 0xA0; + mupd->FspmConfig.DIMM1SPDAddress = 0xA4; + + mupd->FspmConfig.RmtCheckRun = 1; + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0; + mupd->FspmConfig.EnhancePort8xhDecoding = 1; + + mupd->FspmConfig.MsgLevelMask = 0; + mupd->FspmConfig.MrcDataSaving = 0; + mupd->FspmConfig.MrcFastBoot = 1; + + mupd->FspmConfig.PrimaryVideoAdaptor = 2; +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc new file mode 100644 index 0000000..4b48156 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += gpio.c diff --git a/src/mainboard/kontron/mal10/variants/mal10/board_info.txt b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt new file mode 100644 index 0000000..ce66892 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-mAL10 +Board URL: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-… +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/variants/mal10/data.vbt b/src/mainboard/kontron/mal10/variants/mal10/data.vbt new file mode 100644 index 0000000..25be675 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/data.vbt Binary files differ diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb new file mode 100644 index 0000000..1421cb7 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + register "enable_vtd" = "1" + register "dptf_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # iGPU + device pci 03.0 off end # Iunit + device pci 0d.0 on end # P2SB + device pci 0d.1 on end # PMC + device pci 0d.2 on end # SPI + device pci 0d.3 on end # Shared SRAM + device pci 0e.0 on end # Audio + device pci 0f.0 on end # TXE + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + end + device pci 14.1 off # PCIe-B 2 (Root Port 1) + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + end + device pci 15.0 on end # XHCI + device pci 15.1 off end # XDCI + device pci 16.0 off end # I2C 0 + device pci 16.1 off end # I2C 1 + device pci 16.2 off end # I2C 2 + device pci 16.3 off end # I2C 3 + device pci 17.0 off end # I2C 4 + device pci 17.1 off end # I2C 5 + device pci 17.2 off end # I2C 6 + device pci 17.3 off end # I2C 7 + device pci 18.0 off end # HSUART 0 + device pci 18.1 off end # HSUART 1 + device pci 18.2 off end # UART 2 + device pci 18.3 off end # UART 3 + device pci 19.0 off end # SPI 0 + device pci 19.1 off end # SPI 1 + device pci 19.2 off end # SPI 2 + device pci 1a.0 on end # PWM + device pci 1b.0 on end # SDCARD + device pci 1c.0 on end # eMMC + device pci 1d.0 off end # UFS + device pci 1e.0 off end # SDIO + device pci 1f.0 on # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip ec/kontron/kempld + device generic 0.0 on # UART #0 + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + end + device generic 0.1 on # UART #1 + register "uart[1]" = "{ KEMPLD_UART_2F8, 3 }" + end + device generic 1.0 on # I2C + register "i2c_frequency" = "KEMPLD_I2C_FREQ_FAST_MODE_400KHZ" + end + end + end # LPC + device pci 1f.1 on # SMBUS + chip drivers/i2c/nct7802y # Hardware Monitor + register "sensors" = "{ \ + .local_enable = 1, \ + .rtd[2] = RTD_VOLTAGE_MODE, \ + .rtd[1] = RTD_VOLTAGE_MODE, \ + .rtd[0] = RTD_THERMISTOR_MODE, \ + }" + # FAN0 + register "fan[0].mode" = "FAN_SMART" + register "fan[0].smart.mode" = "SMART_FAN_RPM" + register "fan[0].smart.tempsrc" = "TEMP_SOURCE_REMOTE_1" + register "fan[0].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[0].smart.critical_temp" = "95" + # FAN1 + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_RPM" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_LOCAL" + register "fan[1].smart.table" = "{ { 49, 0 }, + { 50, 6350 }, + { 70, 9550 }, + { 90, 12750 } }" + register "fan[1].smart.critical_temp" = "95" + device i2c 0x2e on end + end + end # SMBUS + end + chip drivers/crb + # Resource allocation reserves memory. + # This is required for correct use of TPM + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads new file mode 100644 index 0000000..fee0ce8 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP1, eDP, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c new file mode 100644 index 0000000..1e88e38 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" + +static const struct pad_config gpio_table[] = { + /* SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + + /* SMBUS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + + /* LPC */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void variant_early_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h new file mode 100644 index 0000000..d97e199 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAL_10_CFG_GPIO_H +#define MAL_10_CFG_GPIO_H + +#include <gpio.h> +#include <stddef.h> + +void variant_early_gpio_configure(void); + +#endif /* MAL_10_CFG_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 60 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47759 ) Change subject: soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output ...................................................................... soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output Report the FSP temporary RAM location Tested on Facebook FBG1701 Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/bootblock/bootblock.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47759/1 diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 10ac025..ae1c97a 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -5,6 +5,7 @@ #include <build.h> #include <console/console.h> #include <device/pci_ops.h> +#include <fsp/util.h> #include <pc80/mc146818rtc.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -117,6 +118,8 @@ } void bootblock_soc_init(void) { + report_fsp_output(); + /* Continue chipset initialization */ soc_rtc_init(); set_max_freq(); -- To view, visit https://review.coreboot.org/c/coreboot/+/47759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41 Gerrit-Change-Number: 47759 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: drivers/intel/fsp1_1: Add function to report FSP-T output
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47758 ) Change subject: drivers/intel/fsp1_1: Add function to report FSP-T output ...................................................................... drivers/intel/fsp1_1: Add function to report FSP-T output This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols. Tested on Facebook FBG1701 Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/cache_as_ram.S A src/drivers/intel/fsp1_1/fsp_report.c M src/drivers/intel/fsp1_1/include/fsp/util.h 4 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47758/1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 5fc100a..dc9dcb3 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -7,6 +7,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S +bootblock-y += fsp_report.c bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..07e91d4 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -144,6 +144,8 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ + movl %edx, temp_memory_end + movl %ecx, temp_memory_start /* coreboot assumes stack/heap region will be zero */ cld diff --git a/src/drivers/intel/fsp1_1/fsp_report.c b/src/drivers/intel/fsp1_1/fsp_report.c new file mode 100644 index 0000000..0103cfa --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/symbols.h> +#include <console/console.h> +#include <fsp/util.h> + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fsp_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 41ffedd..cab867a 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -31,6 +31,7 @@ void *get_first_resource_hob(const EFI_GUID *guid); void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); +void report_fsp_output(void); /* Return version of FSP associated with fih. */ static inline uint32_t fsp_version(FSP_INFO_HEADER *fih) -- To view, visit https://review.coreboot.org/c/coreboot/+/47758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda Gerrit-Change-Number: 47758 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47760 ) Change subject: src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only ...................................................................... src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only Whole car region is cleared, while only small part needs to be done. Clear .bss area only Tested on Facebook FBG1701 Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47760/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 31c3580..e8d5091 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -144,15 +144,16 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - - /* coreboot assumes stack/heap region will be zero */ + movl %edx, temp_memory_end + movl %ecx, temp_memory_start + + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl /* Need to align stack to 16 bytes at call instruction. Account for -- To view, visit https://review.coreboot.org/c/coreboot/+/47760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Gerrit-Change-Number: 47760 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/google/sarien: Configure IRQs as level triggered for HID over I2C
by Karthik Ramasubramanian (Code Review) 22 Nov '20

22 Nov '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47424 ) Change subject: mb/google/sarien: Configure IRQs as level triggered for HID over I2C ...................................................................... mb/google/sarien: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3… BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47424/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 74529d0..9e05213 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -337,7 +337,7 @@ chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2a on end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 519c3eb..005a783 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -326,7 +326,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" -- To view, visit https://review.coreboot.org/c/coreboot/+/47424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e Gerrit-Change-Number: 47424 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS
by Furquan Shaikh (Code Review) 22 Nov '20

22 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47832 ) Change subject: vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS ...................................................................... vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/47832/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 46af655..71898a3 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -170,6 +170,7 @@ else $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) +regions-for-file-$(CONFIG_AGESA_CBFS_NAME) = COREBOOT endif # CONFIG_AGESA_BINARY_PI_AS_STAGE endif # AGESA_BINARYPI_INPUT_FILE == "" -- To view, visit https://review.coreboot.org/c/coreboot/+/47832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Gerrit-Change-Number: 47832 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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