coreboot-gerrit November 2020

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Change in coreboot[master]: util/inteltool/ivy_memory.c: Do not rely on MR0 values
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47750 ) Change subject: util/inteltool/ivy_memory.c: Do not rely on MR0 values ...................................................................... util/inteltool/ivy_memory.c: Do not rely on MR0 values MR0 may not always be programmed in the training result registers. Thus, do not rely on its values. Also account for per-channel differences. Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/ivy_memory.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47750/1 diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 3836c11..15d3a10 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -60,7 +60,7 @@ u32 mr0[2]; u32 mr1[2]; u32 reg; - unsigned int CAS = 0; + unsigned int CAS[2] = { 0 }; int tWR = 0, tRFC = 0; int tFAW[2], tWTR[2], tCKE[2], tRTP[2], tRRD[2]; int channel, slot; @@ -108,14 +108,16 @@ tCK = (64 * 10 * 3) / reg; - if (mr0[0] & 1) { - CAS = ((mr0[0] >> 4) & 0x7) + 12; - } else { - CAS = ((mr0[0] >> 4) & 0x7) + 4; - } - for (channel = 0; channel < 2; channel++) { mad_dimm[channel] = read_mchbar32(0x5004 + 4 * channel); + + if (mr0[channel]) { + if (mr0[channel] & 1) { + CAS[channel] = ((mr0[channel] >> 4) & 0x7) + 12; + } else { + CAS[channel] = ((mr0[channel] >> 4) & 0x7) + 4; + } + } } printf(".rankmap = { 0x%x, 0x%x },\n", rankmap[0], rankmap[1]); @@ -135,7 +137,7 @@ ctWR); if (!tWR) tWR = ctWR; - if (((mr0[channel] >> 9) & 7) != mr0_wr_t[tWR - 5]) + if (mr0[channel] && ((mr0[channel] >> 9) & 7) != mr0_wr_t[tWR - 5]) printf("/* encoded tWR mismatch: %d, %d */\n", ((mr0[channel] >> 9) & 7), mr0_wr_t[tWR - 5]); @@ -149,9 +151,13 @@ reg = read_mchbar32(0x4000 + 0x400 * channel); tRAS[channel] = reg >> 16; tCWL[channel] = (reg >> 12) & 0xf; - if (CAS != ((reg >> 8) & 0xf)) - printf("/* CAS mismatch: %d, %d. */\n", CAS, - (reg >> 8) & 0xf); + if (CAS[channel]) { + if (CAS[channel] != ((reg >> 8) & 0xf)) + printf("/* CAS mismatch: %d, %d. */\n", CAS[channel], + (reg >> 8) & 0xf); + } else { + CAS[channel] = (reg >> 8) & 0xf; + } tRP[channel] = (reg >> 4) & 0xf; tRCD[channel] = reg & 0xf; @@ -161,7 +167,10 @@ tAONPD[channel] = (reg >> 8) & 0xf; } printf(".mobile = %d,\n", (mr0[0] >> 12) & 1); - print_time("CAS", CAS, tCK); + + if (two_channels && CAS[0] != CAS[1]) + printf("/* CAS mismatch: %d, %d */\n", CAS[0], CAS[1]); + print_time("CAS", CAS[0], tCK); print_time("tWR", tWR, tCK); printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], @@ -315,10 +324,10 @@ spd[channel][slot][12] = make_spd_time(1, tCK); spd[channel][slot][13] = 0; spd[channel][slot][14] = - (1 << (CAS - 4)) & 0xff; - spd[channel][slot][15] = (1 << (CAS - 4)) >> 8; + (1 << (CAS[channel] - 4)) & 0xff; + spd[channel][slot][15] = (1 << (CAS[channel] - 4)) >> 8; spd[channel][slot][16] = - make_spd_time(CAS, tCK); + make_spd_time(CAS[channel], tCK); spd[channel][slot][17] = make_spd_time(tWR, tCK); spd[channel][slot][18] = -- To view, visit https://review.coreboot.org/c/coreboot/+/47750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Gerrit-Change-Number: 47750 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: util/inteltool/ivy_memory.c: Properly mask tAONPD
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47749 ) Change subject: util/inteltool/ivy_memory.c: Properly mask tAONPD ...................................................................... util/inteltool/ivy_memory.c: Properly mask tAONPD This field is only 4 bits wide. Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/ivy_memory.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47749/1 diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 7a81a92..3836c11 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -158,7 +158,7 @@ reg = read_mchbar32(0x400c + channel * 0x400); tXPDLL[channel] = reg & 0x1f; tXP[channel] = (reg >> 5) & 7; - tAONPD[channel] = (reg >> 8) & 0xff; + tAONPD[channel] = (reg >> 8) & 0xf; } printf(".mobile = %d,\n", (mr0[0] >> 12) & 1); print_time("CAS", CAS, tCK); -- To view, visit https://review.coreboot.org/c/coreboot/+/47749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Gerrit-Change-Number: 47749 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/sandybridge: Clean up COMPOFST1 logic
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47766 ) Change subject: nb/intel/sandybridge: Clean up COMPOFST1 logic ...................................................................... nb/intel/sandybridge: Clean up COMPOFST1 logic This register needs to be updated differently depending on the CPU generation and stepping. Handle this as per reference code. Further, introduce a bitfield for the register to make the code easier to read. Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 2 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47766/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index f2d0fb5..debfaa2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -140,6 +140,23 @@ u32 raw; }; +union comp_ofst_1_reg { + struct { + u32 dq_odt_down : 3; /* [ 2.. 0] */ + u32 dq_odt_up : 3; /* [ 5.. 3] */ + u32 clk_odt_down : 3; /* [ 8.. 6] */ + u32 clk_odt_up : 3; /* [11.. 9] */ + u32 dq_drv_down : 3; /* [14..12] */ + u32 dq_drv_up : 3; /* [17..15] */ + u32 clk_drv_down : 3; /* [20..18] */ + u32 clk_drv_up : 3; /* [23..21] */ + u32 ctl_drv_down : 3; /* [26..24] */ + u32 ctl_drv_up : 3; /* [29..27] */ + u32 : 2; + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e7a3352..3522e96 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -176,6 +176,43 @@ return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC; } +/* Get updated COMP1 based on CPU generation and stepping */ +static u32 get_COMP1(ramctr_timing *ctrl, const int channel) +{ + const union comp_ofst_1_reg orig_comp = { + .raw = MCHBAR32(CRCOMPOFST1_ch(channel)), + }; + + if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) { + union comp_ofst_1_reg comp_ofst_1 = orig_comp; + + comp_ofst_1.clk_odt_up = 1; + comp_ofst_1.clk_drv_up = 1; + comp_ofst_1.ctl_drv_up = 1; + + return comp_ofst_1.raw; + } + + /* Fix PCODE COMP offset bug: revert to default values */ + union comp_ofst_1_reg comp_ofst_1 = { + .dq_odt_down = 4, + .dq_odt_up = 4, + .clk_odt_down = 4, + .clk_odt_up = orig_comp.clk_odt_up, + .dq_drv_down = 4, + .dq_drv_up = orig_comp.dq_drv_up, + .clk_drv_down = 4, + .clk_drv_up = orig_comp.clk_drv_up, + .ctl_drv_down = 4, + .ctl_drv_up = orig_comp.ctl_drv_up, + }; + + if (IS_IVY_CPU(ctrl->cpu)) + comp_ofst_1.dq_drv_up = 2; /* 28p6 ohms */ + + return comp_ofst_1.raw; +} + static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) { if (ctrl->tCK <= TCK_1200MHZ) { @@ -568,8 +605,6 @@ static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg; - int channel; /* IO clock */ @@ -600,11 +635,7 @@ /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); - reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ - reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ - reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ - MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; + MCHBAR32(CRCOMPOFST1_ch(channel)) = get_COMP1(ctrl, channel); } printram("COMP1 done\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Gerrit-Change-Number: 47766 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Correct get_COMP2 function
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47765 ) Change subject: nb/intel/sandybridge: Correct get_COMP2 function ...................................................................... nb/intel/sandybridge: Correct get_COMP2 function Values differ between Sandy and Ivy Bridge. Remove the lookup table, since it contains duplicated values and is hard to see which values correspond to which frequencies. New values come from reference code. Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/raminit_tables.c M src/northbridge/intel/sandybridge/raminit_tables.h 3 files changed, 15 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47765/1 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index aec6a85..e7a3352 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -157,14 +157,23 @@ return frq_aonpd_map[0][FRQ - 3]; } -/* Get COMP2 based on frequency index */ -static u32 get_COMP2(u32 FRQ, u8 base_freq) +/* Get COMP2 based on CPU generation and clock speed */ +static u32 get_COMP2(const ramctr_timing *ctrl) { - if (base_freq == 100) - return frq_comp2_map[1][FRQ - 7]; + const bool is_ivybridge = IS_IVY_CPU(ctrl->cpu); + if (ctrl->tCK <= TCK_1066MHZ) + return is_ivybridge ? 0x0C235924 : 0x0C21410C; + else if (ctrl->tCK <= TCK_933MHZ) + return is_ivybridge ? 0x0C446964 : 0x0C42514C; + else if (ctrl->tCK <= TCK_800MHZ) + return is_ivybridge ? 0x0C6671E4 : 0x0C6369CC; + else if (ctrl->tCK <= TCK_666MHZ) + return is_ivybridge ? 0x0CA8C264 : 0x0CA57A4C; + else if (ctrl->tCK <= TCK_533MHZ) + return is_ivybridge ? 0x0CEBDB64 : 0x0CE7C34C; else - return frq_comp2_map[0][FRQ - 3]; + return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC; } static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) @@ -586,7 +595,7 @@ printram("done\n"); /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl); printram("COMP2 done\n"); /* Set COMP1 */ diff --git a/src/northbridge/intel/sandybridge/raminit_tables.c b/src/northbridge/intel/sandybridge/raminit_tables.c index c3ba9de..3643dcb 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.c +++ b/src/northbridge/intel/sandybridge/raminit_tables.c @@ -91,23 +91,6 @@ }, }; -const u32 frq_comp2_map[2][8] = { - { /* 133 MHz */ - /* FRQ: 7, 8, 9, 10, */ - 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, - - /* FRQ: 11, 12, N/A, N/A, */ - 0x0C235924, 0x0C235924, 0, 0, - }, - { /* 100 MHz */ - /* FRQ: 3, 4, 5, 6, */ - 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, - - /* FRQ: 7, 8, 9, 10, */ - 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, - }, -}; - const u32 pattern[32][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h index 49101cb..308448f 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.h +++ b/src/northbridge/intel/sandybridge/raminit_tables.h @@ -21,8 +21,6 @@ extern const u8 frq_aonpd_map[2][8]; -extern const u32 frq_comp2_map[2][8]; - extern const u32 pattern[32][16]; extern const u8 use_base[63][32]; -- To view, visit https://review.coreboot.org/c/coreboot/+/47765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Gerrit-Change-Number: 47765 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Rename and refactor `discover_timC_write`
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47748 ) Change subject: nb/intel/sandybridge: Rename and refactor `discover_timC_write` ...................................................................... nb/intel/sandybridge: Rename and refactor `discover_timC_write` This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 28 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47748/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 01dfcc4..399ba5a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2438,7 +2438,7 @@ return 0; } -static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) +static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); @@ -2450,9 +2450,15 @@ wait_for_iosav(channel); } -int discover_timC_write(ramctr_timing *ctrl) +static void set_write_vref(const int channel, const u8 wr_vref) { - const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; + MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24), wr_vref << 24); + udelay(2); +} + +int aggressive_write_training(ramctr_timing *ctrl) +{ + const u8 wr_vref_offsets[3] = { 0, 0x0f, 0x2f }; int i, pat; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2471,21 +2477,17 @@ upper[channel][slotrank][lane] = MAX_TIMC; } - /* - * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. - */ - MCHBAR32(MCMNTS_SPARE) = 1; + /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ + const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu); + + if (enable_iosav_opt) + MCHBAR32(MCMNTS_SPARE) = 1; + printram("discover timC write:\n"); - for (i = 0; i < 3; i++) + for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { - - /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); - - udelay(2); + set_write_vref(channel, wr_vref_offsets[i]); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2505,9 +2507,8 @@ } program_timings(ctrl, channel); - test_timC_write (ctrl, channel, slotrank); + test_aggressive_write(ctrl, channel, slotrank); - /* FIXME: Another IVB-only register! */ raw_stats[timC] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); } @@ -2546,18 +2547,16 @@ } } } - - FOR_ALL_CHANNELS { - /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); - udelay(2); } - /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. - */ - MCHBAR32(MCMNTS_SPARE) = 0; + FOR_ALL_CHANNELS { + /* Restore nominal write Vref after training */ + set_write_vref(channel, 0); + } + + /* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization */ + if (enable_iosav_opt) + MCHBAR32(MCMNTS_SPARE) = 0; printram("CPB\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 80d3074..f2d0fb5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -417,7 +417,7 @@ int command_training(ramctr_timing *ctrl); int read_mpr_training(ramctr_timing *ctrl); int aggressive_read_training(ramctr_timing *ctrl); -int discover_timC_write(ramctr_timing *ctrl); +int aggressive_write_training(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index eecd938..aec6a85 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -706,7 +706,7 @@ if (err) return err; - err = discover_timC_write(ctrl); + err = aggressive_write_training(ctrl); if (err) return err; -- To view, visit https://review.coreboot.org/c/coreboot/+/47748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Gerrit-Change-Number: 47748 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Only use write Vref if supported
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47747 ) Change subject: nb/intel/sandybridge: Only use write Vref if supported ...................................................................... nb/intel/sandybridge: Only use write Vref if supported Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/registers/host_bridge.h 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47747/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d533ca8..01dfcc4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2459,6 +2459,13 @@ int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ + if (!IS_IVY_CPU(ctrl->cpu)) + return 0; + + if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) + return 0; + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; upper[channel][slotrank][lane] = MAX_TIMC; diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h index 4814b94..9599871 100644 --- a/src/northbridge/intel/sandybridge/registers/host_bridge.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -52,6 +52,7 @@ #define CAPID_ECCDIS (1 << 25) #define CAPID_DDPCD (1 << 14) #define CAPID_PDCD (1 << 12) +#define CAPID_WRTVREF (1 << 1) #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) #define CAPID0_B 0xe8 /* Capabilities Register B */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Gerrit-Change-Number: 47747 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Lower tPRPDEN to 1
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47745 ) Change subject: nb/intel/sandybridge: Lower tPRPDEN to 1 ...................................................................... nb/intel/sandybridge: Lower tPRPDEN to 1 This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47745/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6ba91c9..b06734c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -175,7 +175,7 @@ .tXP = ctrl->tXP, .tAONPD = ctrl->tAONPD, .tCPDED = 2, - .tPRPDEN = 2, + .tPRPDEN = 1, }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Gerrit-Change-Number: 47745 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Increase tRWDRDD with fast RAM
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47744 ) Change subject: nb/intel/sandybridge: Increase tRWDRDD with fast RAM ...................................................................... nb/intel/sandybridge: Increase tRWDRDD with fast RAM This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47744/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7e93786..6ba91c9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2778,6 +2778,9 @@ void set_read_write_timings(ramctr_timing *ctrl) { + /* Use a larger delay when running fast to improve stability */ + const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; + int channel, slotrank; FOR_ALL_POPULATED_CHANNELS { @@ -2800,7 +2803,7 @@ .tRRDD = val, .tWWDR = val, .tWWDD = val, - .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, .tWRDRDD = tWRDRDD, .tRWSR = 2, .dec_wrd = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/47744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Gerrit-Change-Number: 47744 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Rename and clean up `discover_edges_write`
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47679 ) Change subject: nb/intel/sandybridge: Rename and clean up `discover_edges_write` ...................................................................... nb/intel/sandybridge: Rename and clean up `discover_edges_write` This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47679/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 709a8f6..d60271b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2286,25 +2286,23 @@ return 0; } -static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { - int edge; + const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; + u32 raw_stats[MAX_EDGE_TIMING + 1]; - int stats[MAX_EDGE_TIMING + 1]; - const int reg3000b24[] = { 0, 0xc, 0x2c }; - int lane, i; int lower[NUM_LANES]; int upper[NUM_LANES]; - int pat; + int lane, i, read_pi, pat; FOR_ALL_LANES { lower[lane] = 0; upper[lane] = MAX_EDGE_TIMING; } - for (i = 0; i < 3; i++) { + for (i = 0; i < ARRAY_SIZE(rd_vref_offsets); i++) { const union gdcr_training_mod_reg training_mod = { - .vref_gen_ctl = reg3000b24[i], + .vref_gen_ctl = rd_vref_offsets[i], }; MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); @@ -2313,12 +2311,12 @@ fill_pattern5(ctrl, channel, pat); printram("using pattern %d\n", pat); - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { + for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. - rising = edge; + rising = read_pi; ctrl->timings[channel][slotrank].lanes[lane]. - falling = edge; + falling = read_pi; } program_timings(ctrl, channel); @@ -2339,13 +2337,15 @@ } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); + raw_stats[read_pi] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { + int stats[MAX_EDGE_TIMING + 1]; struct run rn; - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) - stats[edge] = !!(raw_stats[edge] & (1 << lane)); + + for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) + stats[read_pi] = !!(raw_stats[read_pi] & (1 << lane)); rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); @@ -2373,7 +2373,7 @@ return 0; } -int discover_edges_write(ramctr_timing *ctrl) +int aggressive_read_training(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2384,20 +2384,20 @@ * also use a single loop. It would seem that it is a debugging configuration. */ MCHBAR32(IOSAV_DC_MASK) = 0x300; - printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); + printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_write_real(ctrl, channel, slotrank, + err = find_agrsv_read_margin(ctrl, channel, slotrank, falling_edges[channel][slotrank]); if (err) return err; } MCHBAR32(IOSAV_DC_MASK) = 0x200; - printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); + printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_write_real(ctrl, channel, slotrank, + err = find_agrsv_read_margin(ctrl, channel, slotrank, rising_edges[channel][slotrank]); if (err) return err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 44f4768..050aa70 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -407,7 +407,7 @@ int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); int read_mpr_training(ramctr_timing *ctrl); -int discover_edges_write(ramctr_timing *ctrl); +int aggressive_read_training(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ae9a4f4..eecd938 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -702,7 +702,7 @@ printram("CP5c\n"); - err = discover_edges_write(ctrl); + err = aggressive_read_training(ctrl); if (err) return err; -- To view, visit https://review.coreboot.org/c/coreboot/+/47679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Gerrit-Change-Number: 47679 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Relocate PREA-ACT-RD sequence
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47622 ) Change subject: nb/intel/sandybridge: Relocate PREA-ACT-RD sequence ...................................................................... nb/intel/sandybridge: Relocate PREA-ACT-RD sequence Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_iosav.c 3 files changed, 99 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/47622/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 1b517b1..4f54016 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1563,99 +1563,7 @@ wait_for_iosav(channel); - const struct iosav_ssq rd_sequence[] = { - /* DRAM command PREA */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - /* DRAM command ACT */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 8, - .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->CAS, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 500, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command PREA */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - }; - iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); + iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 8424e8f..cb565a9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,7 @@ void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); void iosav_write_jedec_write_leveling_sequence( ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 25f5ae7..d83dfd8 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -199,6 +199,103 @@ iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + /* DRAM command ACT */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->CAS, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 500, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PREA */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + void iosav_write_jedec_write_leveling_sequence( ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Gerrit-Change-Number: 47622 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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