coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/zork: update berknip CHTC thermal setting
by Kevin Chiu (Code Review) 22 Nov '20

22 Nov '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47158 ) Change subject: mb/google/zork: update berknip CHTC thermal setting ...................................................................... mb/google/zork: update berknip CHTC thermal setting Update APU CHTC thermal temperature protection point: Temperature limit(C'): 90 BUG=b:162377903 BRANCH=zork TEST=1. emerge-zork coreboot 2. check CHTC temperature by AMD utility Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47158/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index d97a2b5..9018bdd 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -14,6 +14,7 @@ register "slow_ppt_time_constant" = "5" #second register "stapm_time_constant" = "200" #second register "sustained_power_limit" = "12000" #mw + register "thermctl_limit" = "90" #degrees C register "telemetry_vddcr_vdd_slope" = "65599" #mA register "telemetry_vddcr_vdd_offset" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/47158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Gerrit-Change-Number: 47158 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 22 Nov '20

22 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 15: Thank you for the review -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 22 Nov 2020 17:35:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Use correct NHLT_PDM_DEV definition
by Benjamin Doron (Code Review) 22 Nov '20

22 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45010 ) Change subject: soc/intel/skylake: Use correct NHLT_PDM_DEV definition ...................................................................... Patch Set 8: Thanks for the review -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 22 Nov 2020 17:34:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lenovo/g505s: proper way of IRQ table programming
by Mike Banon (Code Review) 22 Nov '20

22 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46587 ) Change subject: lenovo/g505s: proper way of IRQ table programming ...................................................................... lenovo/g505s: proper way of IRQ table programming IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for Lenovo G505S: all the fam15h boards have these "bad IRQs". With this change applied, G505S boots fine to Linux, but a KolibriOS sees only 1 interrupt - which is still better than a previous 0. So an approach is correct, but the code should be improved. Any advice? Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I32341878e31047f888502291bbdaa76dad268223 --- M src/mainboard/lenovo/g505s/irq_tables.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lenovo/g505s/mptable.c 3 files changed, 193 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46587/1 diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 0baf079..8ae363e 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,88 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x3, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1002, /* Vendor */ + 0x4384, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3b, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index d900c94..3d666a8 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -7,8 +7,81 @@ #include <cpu/x86/smm.h> #include <device/device.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> #include <southbridge/amd/agesa/hudson/smi.h> +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F, + /* RSVD, SATA */ + [0x40] = 0x1F, 0x07 +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F, + /* RSVD, SATA */ + [0x40] = 0x1F, 0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -17,10 +90,16 @@ lenovo_g505s_ec_init(); } +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable(); diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a..4f7272f 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -5,23 +5,48 @@ #include <arch/smp/mpspec.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* RSVD, SATA */ + [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x1F,0x1F,0x1F,0x1F }; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* RSVD, SATA */ + [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x10,0x11,0x12,0x13 }; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) @@ -56,44 +81,60 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + for (byte = 0x0; byte < sizeof(picr_data_ptr); byte ++) { outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); + outb(mainboard_picr_data[byte], 0xC01); } /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data_ptr); byte ++) { outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); + outb(mainboard_intr_data[byte], 0xC01); } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* IOMMU */ PCI_INT(0x0, 0x00, 0x0, 0x10); @@ -102,27 +143,27 @@ PCI_INT(0x0, 0x00, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ @@ -161,9 +202,12 @@ /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32341878e31047f888502291bbdaa76dad268223 Gerrit-Change-Number: 46587 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 57

Change in coreboot[master]: soc/amd/picasso: correct USB2 phy parameter naming problem
by Kevin Chiu (Code Review) 22 Nov '20

22 Nov '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47734 to review the following change. Change subject: soc/amd/picasso: correct USB2 phy parameter naming problem ...................................................................... soc/amd/picasso: correct USB2 phy parameter naming problem From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0". correct rx_vref_tune -> tx_vref_tune BUG=None BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Change-Id: I50af0d28eeb89aaca20b0d89d8a9890564d538fc --- M src/soc/amd/picasso/chip.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47734/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9d8fb8e..28d2040 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -30,7 +30,7 @@ /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */ uint8_t tx_rise_tune; /* HS DC Voltage Level Adjustment. Range 0 - 0xF */ - uint8_t rx_vref_tune; + uint8_t tx_vref_tune; /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */ uint8_t tx_hsxv_tune; /* USB Source Impedance Adjustment. Range 0 - 0x3. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50af0d28eeb89aaca20b0d89d8a9890564d538fc Gerrit-Change-Number: 47734 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47816 ) Change subject: sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs ...................................................................... sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs These two IDs are for Cougar Point and Panther Point, the previous generation of Platform Controller Hubs. So, drop their device IDs. Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/smbus.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47816/1 diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index f616473..2741951 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -80,7 +80,7 @@ }; static const unsigned short pci_device_ids[] = { - 0x1c22, 0x1e22, 0x8c22, 0x9c22, + 0x8c22, 0x9c22, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954 Gerrit-Change-Number: 47816 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 22 Nov 2020 10:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Use correct NHLT_PDM_DEV definition
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45010 ) Change subject: soc/intel/skylake: Use correct NHLT_PDM_DEV definition ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed Gerrit-Change-Number: 45010 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 22 Nov 2020 10:21:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in em100[master]: Handle exit requests in all long-running functions
by Stefan Reinauer (Code Review) 22 Nov '20

22 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47780 ) Change subject: Handle exit requests in all long-running functions ...................................................................... Handle exit requests in all long-running functions Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I5fb37bba1b7398cb6db96d23b226c8b87abee9cf --- M em100.c M em100.h M sdram.c M spi.c 4 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/80/47780/1 diff --git a/em100.c b/em100.c index 6cbae64..14e9805 100644 --- a/em100.c +++ b/em100.c @@ -15,7 +15,6 @@ #include <stdlib.h> #include <string.h> #include <strings.h> -#include <signal.h> #include <getopt.h> #include <unistd.h> #include <dirent.h> @@ -29,12 +28,12 @@ char *database_version; int debug = 0; -static volatile int do_exit_flag = 0; +volatile sig_atomic_t exit_requested = 0; static struct em100 em100_state; static void exit_handler(int sig __unused) { - do_exit_flag = 1; + exit_requested = 1; } struct em100_hold_pin_states { @@ -1212,7 +1211,7 @@ printf(". Press CTL-C to exit.\n\n"); - while (!do_exit_flag) { + while (!exit_requested) { if (trace) read_spi_trace(em100, terminal, address_offset); diff --git a/em100.h b/em100.h index b003bd6..d49339b 100644 --- a/em100.h +++ b/em100.h @@ -15,6 +15,7 @@ #define __EM100_H__ #include <libusb.h> +#include <signal.h> #define __unused __attribute__((unused)) #define __packed __attribute__((packed)) @@ -196,6 +197,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); extern int debug; +extern volatile sig_atomic_t exit_requested; /* Chips */ int parse_dcfg(chipdesc *chip, TFILE *dcfg); diff --git a/sdram.c b/sdram.c index 408afd8..6a9252a 100644 --- a/sdram.c +++ b/sdram.c @@ -42,7 +42,7 @@ return 0; } - while (bytes_read < length) { + while (!exit_requested && bytes_read < length) { actual = 0; bytes_left = length - bytes_read; @@ -92,7 +92,7 @@ return 0; } - while ( bytes_sent < length) { + while (!exit_requested && bytes_sent < length) { actual = 0; bytes_left = length - bytes_sent; diff --git a/spi.c b/spi.c index c088a11..b06c72a 100644 --- a/spi.c +++ b/spi.c @@ -114,7 +114,7 @@ return 0; } - while ( bytes_sent < length) { + while (!exit_requested && bytes_sent < length) { actual = 0; bytes_left = length - bytes_sent; @@ -268,7 +268,7 @@ return 0; } - while ( bytes_sent < length) { + while (!exit_requested && bytes_sent < length) { actual = 0; bytes_left = length - bytes_sent; -- To view, visit https://review.coreboot.org/c/em100/+/47780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I5fb37bba1b7398cb6db96d23b226c8b87abee9cf Gerrit-Change-Number: 47780 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 21 Nov '20

21 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 15: Any comments? -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 15 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 21 Nov 2020 22:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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