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Change in coreboot[master]: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47572 ) Change subject: nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register ...................................................................... nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 55 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/47572/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4b28eff..f20181e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1324,7 +1324,12 @@ /* Execute command queue */ iosav_run_once(channel); - MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; + const union gdcr_training_mod_reg training_mod = { + .receive_enable_mode = 1, + .training_rank_sel = slotrank, + .odt_always_on = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].roundtrip_latency = 55; @@ -1754,7 +1759,14 @@ int statistics[NUM_LANES][128]; int lane; - MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .training_rank_sel = slotrank, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1824,7 +1836,12 @@ static void train_write_flyby(ramctr_timing *ctrl) { int channel, slotrank, lane, old; - MCHBAR32(GDCRTRAININGMOD) = 0x200; + + const union gdcr_training_mod_reg training_mod = { + .dq_dqs_training_res = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); } @@ -1983,7 +2000,13 @@ write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); - MCHBAR32(GDCRTRAININGMOD) = 0x108052; + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; toggle_io_reset(); @@ -2483,8 +2506,11 @@ } for (i = 0; i < 3; i++) { - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + const union gdcr_training_mod_reg training_mod = { + .vref_gen_ctl = reg3000b24[i], + }; + MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 2244048..de74af5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -117,6 +117,29 @@ u32 raw; }; +union gdcr_training_mod_reg { + struct { + u32 receive_enable_mode : 1; /* [ 0.. 0] */ + u32 write_leveling_mode : 1; /* [ 1.. 1] */ + u32 training_rank_sel : 2; /* [ 3.. 2] */ + u32 enable_dqs_wl : 4; /* [ 7.. 4] */ + u32 dqs_logic_delay_wl : 1; /* [ 8.. 8] */ + u32 dq_dqs_training_res : 1; /* [ 9.. 9] */ + u32 : 4; + u32 delay_dq : 1; /* [14..14] */ + u32 odt_always_on : 1; /* [15..15] */ + u32 : 4; + u32 force_drive_enable : 1; /* [20..20] */ + u32 dft_tx_pi_clk_view : 1; /* [21..21] */ + u32 dft_tx_pi_clk_swap : 4; /* [22..22] */ + u32 early_odt_en : 1; /* [23..23] */ + u32 vref_gen_ctl : 6; /* [29..24] */ + u32 ext_vref_sel : 1; /* [30..30] */ + u32 tx_fifo_always_on : 1; /* [31..31] */ + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Gerrit-Change-Number: 47572 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47571 ) Change subject: nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING ...................................................................... nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING This register's layout makes no sense, so use bitfields for clarity. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 31 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/47571/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 697167a..4b28eff 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -911,7 +911,7 @@ void program_timings(ramctr_timing *ctrl, int channel) { - u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; + u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; int lane; int slotrank, slot; int full_shift = 0; @@ -944,13 +944,18 @@ } /* Enable CMD XOVER */ - reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); - reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; - reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; - reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; - reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); + union gdcr_cmd_pi_coding_reg cmd_pi_coding = { + .raw = get_XOVER_CMD(ctrl->rankmap[channel]), + }; + cmd_pi_coding.cmd_pi_code = full_shift & 0x3f; + cmd_pi_coding.cmd_logic_delay = !!(full_shift & 0x40); - MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; + cmd_pi_coding.ctl_pi_code_d0 = pi_coding_ctrl[0] & 0x3f; + cmd_pi_coding.ctl_pi_code_d1 = pi_coding_ctrl[1] & 0x3f; + cmd_pi_coding.ctl_logic_delay_d0 = !!(pi_coding_ctrl[0] & 0x40); + cmd_pi_coding.ctl_logic_delay_d1 = !!(pi_coding_ctrl[1] & 0x40); + + MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; /* Enable CLK XOVER */ reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 1847074..3844f86 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,25 @@ } addr_update; }; +union gdcr_cmd_pi_coding_reg { + struct { + u32 cmd_pi_code : 6; /* [ 5.. 0] */ + u32 ctl_pi_code_d0 : 6; /* [11.. 6] */ + u32 cmd_logic_delay : 1; /* [12..12] */ + u32 cmd_phase_delay : 1; /* [13..13] */ + u32 cmd_xover_enable : 1; /* [14..14] */ + u32 ctl_logic_delay_d0 : 1; /* [15..15] */ + u32 ctl_phase_delay_d0 : 1; /* [16..16] */ + u32 ctl_xover_enable_d0 : 1; /* [14..14] */ + u32 ctl_pi_code_d1 : 6; /* [23..18] */ + u32 ctl_logic_delay_d1 : 1; /* [24..24] */ + u32 ctl_phase_delay_d1 : 1; /* [25..25] */ + u32 ctl_xover_enable_d1 : 1; /* [26..26] */ + u32 : 5; + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Gerrit-Change-Number: 47571 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in em100[master]: Limit USB errors in trace / terminal mode
by Stefan Reinauer (Code Review) 22 Nov '20

22 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47841 ) Change subject: Limit USB errors in trace / terminal mode ...................................................................... Limit USB errors in trace / terminal mode If the device gets into a bad state (or, say, gets disconnected), bail out after 10 errors instead of continuing ad infinitum. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I1474386c69d267dba3bccaa740213753c06fee0c --- M em100.c 1 file changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/41/47841/1 diff --git a/em100.c b/em100.c index f7bbb2d..2866f91 100644 --- a/em100.c +++ b/em100.c @@ -1190,6 +1190,8 @@ } if (trace || terminal) { + int usb_errors = 0; + if ((holdpin == NULL) && (!set_hold_pin_state(em100, 3))) { printf("Error: Failed to set EM100 to input\n"); return 1; @@ -1212,12 +1214,15 @@ printf(". Press CTL-C to exit.\n\n"); - while (!do_exit_flag) { - if (trace) - read_spi_trace(em100, terminal, - address_offset); - else - read_spi_terminal(em100, 0); + while (!do_exit_flag && usb_errors < 10) { + if (trace) { + if (!read_spi_trace(em100, terminal, + address_offset)) + usb_errors++; + } else { + if (!read_spi_terminal(em100, 0)) + usb_errors++; + } } if (!do_start && !do_stop) -- To view, visit https://review.coreboot.org/c/em100/+/47841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I1474386c69d267dba3bccaa740213753c06fee0c Gerrit-Change-Number: 47841 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/clevo/cml-u: Move hda_verb.c to mainboard's Makefile
by Felix Singer (Code Review) 22 Nov '20

22 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47820 to look at the new patch set (#3). Change subject: mb/clevo/cml-u: Move hda_verb.c to mainboard's Makefile ...................................................................... mb/clevo/cml-u: Move hda_verb.c to mainboard's Makefile Move hda_verb.c from the variant's Makefile to the mainboard's Makefile, because every variant needs one. Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc M src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/47820/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c Gerrit-Change-Number: 47820 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: nb/intel/sandybridge: Move constants out of for-loop
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47513 ) Change subject: nb/intel/sandybridge: Move constants out of for-loop ...................................................................... nb/intel/sandybridge: Move constants out of for-loop Some per-channel registers are programmed with the same values. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 60 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/47513/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 98b14ff..3d82a00 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -148,69 +148,82 @@ { int channel; + /* BIN parameters */ + const union tc_dbp_reg tc_dbp = { + .tRCD = ctrl->tRCD, + .tRP = ctrl->tRP, + .tAA = ctrl->CAS, + .tCWL = ctrl->CWL, + .tRAS = ctrl->tRAS, + }; + + /* Regular access parameters */ + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = 3, + }; + + /* Other parameters */ + const union tc_othp_reg tc_othp = { + .tXPDLL = ctrl->tXPDLL, + .tXP = ctrl->tXP, + .tAONPD = ctrl->tAONPD, + .tCPDED = 2, + .tPRPDEN = 2, + }; + + /* + * If tXP and tXPDLL are very high, we need to increase them by one. + * This can only happen on Ivy Bridge, and when overclocking the RAM. + */ + const union tc_dtp_reg tc_dtp = { + .overclock_tXP = ctrl->tXP >= 8, + .overclock_tXPDLL = ctrl->tXPDLL >= 32, + }; + + /* + * TC-Refresh timing parameters: + * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow + * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. + */ + const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + + const union tc_rftp_reg tc_rftp = { + .tREFI = ctrl->tREFI, + .tRFC = ctrl->tRFC, + .tREFIx9 = val32 / 1024, + }; + + /* Self-refresh timing parameters */ + const union tc_srftp_reg tc_srftp = { + .tXSDLL = tDLLK, + .tXS_offset = ctrl->tXSOffset, + .tZQOPER = tDLLK - ctrl->tXSOffset, + .tMOD = ctrl->tMOD - 8, + }; + FOR_ALL_CHANNELS { - /* BIN parameters */ - const union tc_dbp_reg tc_dbp = { - .tRCD = ctrl->tRCD, - .tRP = ctrl->tRP, - .tAA = ctrl->CAS, - .tCWL = ctrl->CWL, - .tRAS = ctrl->tRAS, - }; printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; - /* Regular access parameters */ - const union tc_rap_reg tc_rap = { - .tRRD = ctrl->tRRD, - .tRTP = ctrl->tRTP, - .tCKE = ctrl->tCKE, - .tWTR = ctrl->tWTR, - .tFAW = ctrl->tFAW, - .tWR = ctrl->tWR, - .tCMD = 3, - }; printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; - /* Other parameters */ - const union tc_othp_reg tc_othp = { - .tXPDLL = ctrl->tXPDLL, - .tXP = ctrl->tXP, - .tAONPD = ctrl->tAONPD, - .tCPDED = 2, - .tPRPDEN = 2, - }; printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; - /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { - /* - * If tXP and tXPDLL are very high, we need to increase them by one. - * This can only happen on Ivy Bridge, and when overclocking the RAM. - */ - const union tc_dtp_reg tc_dtp = { - .overclock_tXP = ctrl->tXP >= 8, - .overclock_tXPDLL = ctrl->tXPDLL >= 32, - }; + /* Debug parameters - only applies to Ivy Bridge */ MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; } dram_odt_stretch(ctrl, channel); - /* - * TC-Refresh timing parameters: - * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow - * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. - */ - const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - - const union tc_rftp_reg tc_rftp = { - .tREFI = ctrl->tREFI, - .tRFC = ctrl->tRFC, - .tREFIx9 = val32 / 1024, - }; printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; @@ -220,13 +233,6 @@ tc_rfp.oref_ri = 0xff; MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; - /* Self-refresh timing parameters */ - const union tc_srftp_reg tc_srftp = { - .tXSDLL = tDLLK, - .tXS_offset = ctrl->tXSOffset, - .tZQOPER = tDLLK - ctrl->tXSOffset, - .tMOD = ctrl->tMOD - 8, - }; printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; } -- To view, visit https://review.coreboot.org/c/coreboot/+/47513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Gerrit-Change-Number: 47513 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: nb/intel/sandybridge: Use bitfields to program MCMAIN timings
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47512 ) Change subject: nb/intel/sandybridge: Use bitfields to program MCMAIN timings ...................................................................... nb/intel/sandybridge: Use bitfields to program MCMAIN timings Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 2 files changed, 210 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47512/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5d4a767..98b14ff 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -134,63 +134,67 @@ printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18)); + union tc_othp_reg tc_othp = { + .raw = MCHBAR32(addr), + }; + tc_othp.odt_delay_d0 = stretch; + tc_othp.odt_delay_d1 = stretch; + MCHBAR32(addr) = tc_othp.raw; printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } void dram_timing_regs(ramctr_timing *ctrl) { - u32 reg, val32; int channel; FOR_ALL_CHANNELS { /* BIN parameters */ - reg = 0; - reg |= (ctrl->tRCD << 0); - reg |= (ctrl->tRP << 4); - reg |= (ctrl->CAS << 8); - reg |= (ctrl->CWL << 12); - reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); - MCHBAR32(TC_DBP_ch(channel)) = reg; + const union tc_dbp_reg tc_dbp = { + .tRCD = ctrl->tRCD, + .tRP = ctrl->tRP, + .tAA = ctrl->CAS, + .tCWL = ctrl->CWL, + .tRAS = ctrl->tRAS, + }; + printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); + MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; /* Regular access parameters */ - reg = 0; - reg |= (ctrl->tRRD << 0); - reg |= (ctrl->tRTP << 4); - reg |= (ctrl->tCKE << 8); - reg |= (ctrl->tWTR << 12); - reg |= (ctrl->tFAW << 16); - reg |= (ctrl->tWR << 24); - reg |= (3 << 30); - printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); - MCHBAR32(TC_RAP_ch(channel)) = reg; + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = 3, + }; + printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; /* Other parameters */ - reg = 0; - reg |= (ctrl->tXPDLL << 0); - reg |= (ctrl->tXP << 5); - reg |= (ctrl->tAONPD << 8); - reg |= 0xa0000; - printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg); - MCHBAR32(TC_OTHP_ch(channel)) = reg; + const union tc_othp_reg tc_othp = { + .tXPDLL = ctrl->tXPDLL, + .tXP = ctrl->tXP, + .tAONPD = ctrl->tAONPD, + .tCPDED = 2, + .tPRPDEN = 2, + }; + printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); + MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { - reg = 0; - /* * If tXP and tXPDLL are very high, we need to increase them by one. * This can only happen on Ivy Bridge, and when overclocking the RAM. */ - if (ctrl->tXP >= 8) - reg |= (1 << 12); - - if (ctrl->tXPDLL >= 32) - reg |= (1 << 13); - - MCHBAR32(TC_DTP_ch(channel)) = reg; + const union tc_dtp_reg tc_dtp = { + .overclock_tXP = ctrl->tXP >= 8, + .overclock_tXPDLL = ctrl->tXPDLL >= 32, + }; + MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; } dram_odt_stretch(ctrl, channel); @@ -200,28 +204,31 @@ * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. */ - val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - reg = ((ctrl->tREFI & 0xffff) << 0) | - ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); + const union tc_rftp_reg tc_rftp = { + .tREFI = ctrl->tREFI, + .tRFC = ctrl->tRFC, + .tREFIx9 = val32 / 1024, + }; + printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); + MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; - printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); - MCHBAR32(TC_RFTP_ch(channel)) = reg; - - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + union tc_rfp_reg tc_rfp = { + .raw = MCHBAR32(TC_RFP_ch(channel)), + }; + tc_rfp.oref_ri = 0xff; + MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; /* Self-refresh timing parameters */ - reg = 0; - val32 = tDLLK; - reg = (reg & ~0x00000fff) | (val32 << 0); - val32 = ctrl->tXSOffset; - reg = (reg & ~0x0000f000) | (val32 << 12); - val32 = tDLLK - ctrl->tXSOffset; - reg = (reg & ~0x03ff0000) | (val32 << 16); - val32 = ctrl->tMOD - 8; - reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); - MCHBAR32(TC_SRFTP_ch(channel)) = reg; + const union tc_srftp_reg tc_srftp = { + .tXSDLL = tDLLK, + .tXS_offset = ctrl->tXSOffset, + .tZQOPER = tDLLK - ctrl->tXSOffset, + .tMOD = ctrl->tMOD - 8, + }; + printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); + MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; } } @@ -2169,14 +2176,16 @@ ctrl->cmd_stretch[channel] = cmd_stretch; - MCHBAR32(TC_RAP_ch(channel)) = - (ctrl->tRRD << 0) - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = ctrl->cmd_stretch[channel], + }; + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; if (ctrl->cmd_stretch[channel] == 2) delta = 2; @@ -2926,7 +2935,6 @@ int channel, slotrank; FOR_ALL_POPULATED_CHANNELS { - u32 b20, b4_8_12; int min_pi = 10000; int max_pi = -10000; @@ -2935,14 +2943,23 @@ min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); } - b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; + const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; - b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; + const u32 val = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 3 : 2; dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) | - ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; + const union tc_rwp_reg tc_rwp = { + .tRRDR = 0, + .tRRDD = val, + .tWWDR = val, + .tWWDD = val, + .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tWRDRDD = tWRDRDD, + .tRWSR = 2, + .dec_wrd = 1, + }; + MCHBAR32(TC_RWP_ch(channel)) = tc_rwp.raw; } } @@ -2974,8 +2991,13 @@ /* FIXME: This register only exists on Ivy Bridge */ MCHBAR32(WMM_READ_CONFIG) = 0x46; - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12); + FOR_ALL_CHANNELS { + union tc_othp_reg tc_othp = { + .raw = MCHBAR32(TC_OTHP_ch(channel)), + }; + tc_othp.tCPDED = 1; + MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; + } if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3013,8 +3035,13 @@ MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + FOR_ALL_CHANNELS { + union tc_rfp_reg tc_rfp = { + .raw = MCHBAR32(TC_RFP_ch(channel)), + }; + tc_rfp.refresh_2x_control = 1; + MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; + } MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); @@ -3053,14 +3080,16 @@ int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(TC_RAP_ch(channel)) = - (ctrl->tRRD << 0) - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = ctrl->cmd_stretch[channel], + }; + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; } udelay(1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index e6858c9..1847074 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,108 @@ } addr_update; }; +union tc_dbp_reg { + struct { + u32 tRCD : 4; /* [ 3.. 0] */ + u32 tRP : 4; /* [ 7.. 4] */ + u32 tAA : 4; /* [11.. 8] */ + u32 tCWL : 4; /* [15..12] */ + u32 tRAS : 8; /* [23..16] */ + u32 : 8; + }; + u32 raw; +}; + +union tc_rap_reg { + struct { + u32 tRRD : 4; /* [ 3.. 0] */ + u32 tRTP : 4; /* [ 7.. 4] */ + u32 tCKE : 4; /* [11.. 8] */ + u32 tWTR : 4; /* [15..12] */ + u32 tFAW : 8; /* [23..16] */ + u32 tWR : 5; /* [28..24] */ + u32 dis_3st : 1; /* [29..29] */ + u32 tCMD : 2; /* [31..30] */ + }; + u32 raw; +}; + +union tc_rwp_reg { + struct { + u32 tRRDR : 3; /* [ 2.. 0] */ + u32 : 1; + u32 tRRDD : 3; /* [ 6.. 4] */ + u32 : 1; + u32 tWWDR : 3; /* [10.. 8] */ + u32 : 1; + u32 tWWDD : 3; /* [14..12] */ + u32 : 1; + u32 tRWDRDD : 3; /* [18..16] */ + u32 : 1; + u32 tWRDRDD : 3; /* [22..20] */ + u32 : 1; + u32 tRWSR : 3; /* [26..24] */ + u32 dec_wrd : 1; /* [27..27] */ + u32 : 4; + }; + u32 raw; +}; + +union tc_othp_reg { + struct { + u32 tXPDLL : 5; /* [ 4.. 0] */ + u32 tXP : 3; /* [ 7.. 5] */ + u32 tAONPD : 4; /* [11.. 8] */ + u32 tCPDED : 2; /* [13..12] */ + u32 tPRPDEN : 2; /* [15..14] */ + u32 odt_delay_d0 : 2; /* [17..16] */ + u32 odt_delay_d1 : 2; /* [19..18] */ + u32 : 12; + }; + u32 raw; +}; + +union tc_dtp_reg { + struct { + u32 : 12; + u32 overclock_tXP : 1; /* [12..12] */ + u32 overclock_tXPDLL : 1; /* [13..13] */ + u32 : 18; + }; + u32 raw; +}; + +union tc_rfp_reg { + struct { + u32 oref_ri : 8; /* [ 7.. 0] */ + u32 refresh_high_wm : 4; /* [11.. 8] */ + u32 refresh_panic_wm : 4; /* [15..12] */ + u32 refresh_2x_control : 2; /* [17..16] */ + u32 : 14; + }; + u32 raw; +}; + +union tc_rftp_reg { + struct { + u32 tREFI : 16; /* [15.. 0] */ + u32 tRFC : 9; /* [24..16] */ + u32 tREFIx9 : 7; /* [31..25] */ + }; + u32 raw; +}; + +union tc_srftp_reg { + struct { + u32 tXSDLL : 12; /* [11.. 0] */ + u32 tXS_offset : 4; /* [15..12] */ + u32 tZQOPER : 10; /* [25..16] */ + u32 : 2; + u32 tMOD : 4; /* [31..28] */ + }; + u32 raw; +}; + typedef struct ramctr_timing_st ramctr_timing; void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); -- To view, visit https://review.coreboot.org/c/coreboot/+/47512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Gerrit-Change-Number: 47512 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: nb/intel/sandybridge: Clean up TC_OTHP writes
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47490 ) Change subject: nb/intel/sandybridge: Clean up TC_OTHP writes ...................................................................... nb/intel/sandybridge: Clean up TC_OTHP writes ODT stretch is configured for both slots in `dram_odt_stretch`. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47490/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 20c048f..8a4b25b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -166,7 +166,7 @@ void dram_timing_regs(ramctr_timing *ctrl) { - u32 reg, addr, val32; + u32 reg, val32; int channel; FOR_ALL_CHANNELS { @@ -193,14 +193,13 @@ MCHBAR32(TC_RAP_ch(channel)) = reg; /* Other parameters */ - addr = TC_OTHP_ch(channel); reg = 0; reg |= (ctrl->tXPDLL << 0); reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printram("OTHP [%x] = %x\n", addr, reg); - MCHBAR32(addr) = reg; + printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg); + MCHBAR32(TC_OTHP_ch(channel)) = reg; /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { @@ -219,8 +218,6 @@ MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); - dram_odt_stretch(ctrl, channel); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Gerrit-Change-Number: 47490 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: nb/intel/sandybridge: Use one sequence for write leveling
by Angel Pons (Code Review) 22 Nov '20

22 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47614 ) Change subject: nb/intel/sandybridge: Use one sequence for write leveling ...................................................................... nb/intel/sandybridge: Use one sequence for write leveling In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 48 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47614/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 60ce50b..2a3fb8c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1716,15 +1716,40 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { - /* enable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7); + /* First DQS/DQS# rising edge after write leveling mode is programmed */ + const u32 tWLMRD = 40; + + u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + int bank = 1; + + if (ctrl->rank_mirror[channel][slotrank]) + ddr3_mirror_mrreg(&bank, &mr1reg); wait_for_iosav(channel); const struct iosav_ssq sequence[] = { - /* DRAM command NOP */ + /* DRAM command MRS: enable DQs on this slotrank */ [0] = { .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tWLMRD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [1] = { + .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, }, @@ -1742,7 +1767,7 @@ }, }, /* DRAM command NOP */ - [1] = { + [2] = { .sp_cmd_ctrl = { .command = IOSAV_NOP_ALT, .ranksel_ap = 1, @@ -1760,6 +1785,25 @@ .rank = slotrank, }, }, + /* DRAM command MRS: disable DQs on this slotrank */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg | 1 << 12, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); @@ -1767,10 +1811,6 @@ iosav_run_once(channel); wait_for_iosav(channel); - - /* disable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); } static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) -- To view, visit https://review.coreboot.org/c/coreboot/+/47614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Gerrit-Change-Number: 47614 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in em100[master]: Cosmetic debug output fix
by Stefan Reinauer (Code Review) 22 Nov '20

22 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47844 ) Change subject: Cosmetic debug output fix ...................................................................... Cosmetic debug output fix Ever since the hold pin code was implemented, there were two newlines in debug mode. Remove one. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I3e406fb45f155ba3e1fcc86b92dc068b6c69cc33 --- M em100.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/44/47844/1 diff --git a/em100.c b/em100.c index 1af0f03..6d35b76 100644 --- a/em100.c +++ b/em100.c @@ -289,7 +289,7 @@ static int em100_debug(struct em100 *em100) { int i; - printf("\nVoltages:\n"); + printf("Voltages:\n"); set_led(em100, both_off); printf(" 1.2V: %dmV\n", get_voltage(em100, in_v1_2)); printf(" E_VCC: %dmV\n", get_voltage(em100, in_e_vcc)); -- To view, visit https://review.coreboot.org/c/em100/+/47844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I3e406fb45f155ba3e1fcc86b92dc068b6c69cc33 Gerrit-Change-Number: 47844 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 2

Change in em100[master]: Rename do_exit_flag to exit_requested
by Stefan Reinauer (Code Review) 22 Nov '20

22 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47842 ) Change subject: Rename do_exit_flag to exit_requested ...................................................................... Rename do_exit_flag to exit_requested ... and change the type to sig_atomic_t. Also, make it globally available again (because it is indeed useful in other parts of the code) Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Ifd6f0d9145c689ecce0609a2d04b2221f8533181 --- M em100.c M em100.h 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/42/47842/1 diff --git a/em100.c b/em100.c index 2866f91..d66b89e 100644 --- a/em100.c +++ b/em100.c @@ -29,12 +29,12 @@ char *database_version; int debug = 0; -static volatile int do_exit_flag = 0; +volatile int exit_requested = 0; static struct em100 em100_state; static void exit_handler(int sig __unused) { - do_exit_flag = 1; + exit_requested = 1; } struct em100_hold_pin_states { @@ -1214,7 +1214,7 @@ printf(". Press CTL-C to exit.\n\n"); - while (!do_exit_flag && usb_errors < 10) { + while (!exit_requested && usb_errors < 10) { if (trace) { if (!read_spi_trace(em100, terminal, address_offset)) diff --git a/em100.h b/em100.h index b003bd6..d49339b 100644 --- a/em100.h +++ b/em100.h @@ -15,6 +15,7 @@ #define __EM100_H__ #include <libusb.h> +#include <signal.h> #define __unused __attribute__((unused)) #define __packed __attribute__((packed)) @@ -196,6 +197,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); extern int debug; +extern volatile sig_atomic_t exit_requested; /* Chips */ int parse_dcfg(chipdesc *chip, TFILE *dcfg); -- To view, visit https://review.coreboot.org/c/em100/+/47842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ifd6f0d9145c689ecce0609a2d04b2221f8533181 Gerrit-Change-Number: 47842 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 5

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