coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Angel Pons (Code Review) 23 Nov '20

23 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 30 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 23 Nov 2020 12:59:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl1: Use `pci_or_config16` function
by Angel Pons (Code Review) 23 Nov '20

23 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47400 ) Change subject: mb/siemens/mc_apl1: Use `pci_or_config16` function ...................................................................... mb/siemens/mc_apl1: Use `pci_or_config16` function Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 5 files changed, 5 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47400/1 diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index bff97ea..0d93563 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -187,7 +187,6 @@ static void mainboard_final(void *chip_info) { - uint16_t cmd = 0; struct device *dev = NULL; /* Do board specific things */ @@ -196,9 +195,7 @@ /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); if (dev) { - cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } /* Set up SPI OPCODE menu before the controller is locked. */ fast_spi_set_opcode_menu(); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index e7bc589..000ee08 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -16,14 +16,11 @@ void variant_mainboard_final(void) { struct device *dev; - uint16_t cmd = 0; /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); if (dev) { - cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 07fa01d..8b1a0e1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -22,7 +22,6 @@ void variant_mainboard_final(void) { struct device *dev = NULL; - uint16_t cmd = 0; /* PIR6 register mapping for PCIe root ports * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# @@ -43,9 +42,7 @@ /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); if (dev) { - cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index e85161b..c0a7d53 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -20,7 +20,6 @@ void variant_mainboard_final(void) { struct device *dev = NULL; - uint16_t cmd; /* * PIR6 register mapping for PCIe root ports @@ -50,9 +49,7 @@ /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); if (dev) { - cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe * to PCI Bridge. */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index 33160d0..f9345f4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -22,7 +22,6 @@ void variant_mainboard_final(void) { struct device *dev = NULL; - uint16_t cmd = 0; /* PIR6 register mapping for PCIe root ports * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# @@ -43,9 +42,7 @@ /* Set Master Enable for on-board PCI device. */ dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); if (dev) { - cmd = pci_read_config16(dev, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, cmd); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Disable clock outputs 0-3 (CLKOUT) for upstream * XIO2001 PCIe to PCI Bridge. -- To view, visit https://review.coreboot.org/c/coreboot/+/47400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe Gerrit-Change-Number: 47400 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Add ICC limits for CFL-S DT 4
by Angel Pons (Code Review) 23 Nov '20

23 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47445 ) Change subject: soc/intel/cannonlake: Add ICC limits for CFL-S DT 4 ...................................................................... soc/intel/cannonlake: Add ICC limits for CFL-S DT 4 TEST=Boot with an i3-9100F and see no vr_config errors. Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47445/1 diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 2b621f7..1f85588 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -206,6 +206,11 @@ { 54, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 58, 45, 45) }, { 0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) }, }; +VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) { + { 71, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 100, 45, 45) }, + { 62, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 79, 45, 45) }, + { 35, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 66, 35, 35) }, +}; VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) { { 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) }, { 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) }, @@ -304,6 +309,7 @@ VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_H_4), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2), + VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8), VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8), -- To view, visit https://review.coreboot.org/c/coreboot/+/47445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db Gerrit-Change-Number: 47445 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns: Hook up SMMSTORE
by Angel Pons (Code Review) 23 Nov '20

23 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47450 ) Change subject: soc/intel/denverton_ns: Hook up SMMSTORE ...................................................................... soc/intel/denverton_ns: Hook up SMMSTORE UNTESTED. Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47450/1 diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7..cae8b9b 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -10,6 +10,7 @@ #include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> +#include <smmstore.h> #include <spi-generic.h> #include <soc/iomap.h> #include <soc/soc_util.h> @@ -197,6 +198,26 @@ fast_spi_init(); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -245,6 +266,10 @@ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- To view, visit https://review.coreboot.org/c/coreboot/+/47450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e Gerrit-Change-Number: 47450 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 23 Nov '20

23 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... Patch Set 30: (1 comment) https://review.coreboot.org/c/coreboot/+/46231/29/src/soc/intel/xeon_sp/smm… File src/soc/intel/xeon_sp/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/46231/29/src/soc/intel/xeon_sp/smm… PS29, Line 17: const uint32_t rmask = ~(4 * KiB - 1); > Why not use ALIGN_DOWN and friends? more or less done. If one checks that tseg_base is aligned to tseg_size and that tseg_size is aligned to the minimum 4K, that should do it. -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 30 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 23 Nov 2020 12:05:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 23 Nov '20

23 Nov '20

Arthur Heymans has uploaded a new patch set (#30) to the change originally created by Rocky Phagura. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smmrelocate.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 12 files changed, 205 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46231/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 30 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/cml-u: Get rid of gpio.h and use C files instead
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47836 ) Change subject: mb/clevo/cml-u: Get rid of gpio.h and use C files instead ...................................................................... mb/clevo/cml-u: Get rid of gpio.h and use C files instead Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc M src/mainboard/clevo/cml-u/bootblock.c M src/mainboard/clevo/cml-u/ramstage.c D src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h 4 files changed, 7 insertions(+), 261 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/47836/1 diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc index de3c774..b69c257 100644 --- a/src/mainboard/clevo/cml-u/Makefile.inc +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -1,8 +1,10 @@ -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index 427b023..70da17e 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -2,9 +2,9 @@ #include <bootblock_common.h> #include <gpio.h> -#include <variant/gpio.h> +#include <mainboard/gpio.h> void bootblock_mainboard_init(void) { - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + mainboard_configure_gpios(); } diff --git a/src/mainboard/clevo/cml-u/ramstage.c b/src/mainboard/clevo/cml-u/ramstage.c index 824adfc..771c6aa 100644 --- a/src/mainboard/clevo/cml-u/ramstage.c +++ b/src/mainboard/clevo/cml-u/ramstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <variant/gpio.h> +#include <mainboard/gpio.h> static void init_mainboard(void *chip_info) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h b/src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h deleted file mode 100644 index 1f7d119..0000000 --- a/src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h +++ /dev/null @@ -1,256 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -#ifndef __ACPI__ - -/* Name format: <pad name> / <net/pin name in schematics> */ - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - PAD_NC(GPP_C22, UP_20K), - PAD_NC(GPP_C23, UP_20K), -}; - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - /* ------- GPIO Group GPD ------- */ - PAD_NC(GPD0, NONE), - PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */ - PAD_NC(GPD2, UP_20K), - PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */ - PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */ - PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */ - PAD_NC(GPD6, UP_20K), - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */ - PAD_NC(GPD9, UP_20K), - PAD_NC(GPD10, UP_20K), - PAD_NC(GPD11, UP_20K), - - /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* RCIN# / SB_KBCRST# */ - PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LAD0 / LPC_AD0 */ - PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LAD1 / LPC_AD1 */ - PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LAD2 / LPC_AD2 */ - PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LAD3 / LPC_AD3 */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LFRAME# / LPC_FRAME# */ - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* SERIRQ */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PIRQA# / TPM_PIRQ# */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKRUN# / PM_CLKRUN# - Note: R209 is populated despite being - marked no-stuff in schematic - */ - PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* CLKOUT_LPC0 / PCLK_KBC */ - PAD_NC(GPP_A10, UP_20K), - PAD_NC(GPP_A11, UP_20K), /* INTP_OUT - (Type-C VBUS_SENSE; unused in cb) - */ - PAD_NC(GPP_A12, UP_20K), - PAD_NC(GPP_A13, UP_20K), /* SUSWARN# - (unused due to missing DeepSx support) - */ - PAD_NC(GPP_A14, UP_20K), - PAD_NC(GPP_A15, UP_20K), - PAD_NC(GPP_A16, UP_20K), - PAD_NC(GPP_A17, NONE), /* LEDKB_DET# - (unused in cb; all devices of that - model have KB LED) - */ - PAD_NC(GPP_A18, UP_20K), - PAD_NC(GPP_A19, UP_20K), - PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_A20 / TEST_R */ - PAD_NC(GPP_A21, UP_20K), - PAD_NC(GPP_A22, UP_20K), - PAD_NC(GPP_A23, UP_20K), - - /* ------- GPIO Group GPP_B ------- */ - PAD_NC(GPP_B0, UP_20K), - PAD_NC(GPP_B1, UP_20K), - PAD_NC(GPP_B2, UP_20K), /* CNVI_WAKE# - (UART_WAKE# in M.2 spec; unused) - */ - PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST),/* GPP_B3 (touchpad interrupt) */ - PAD_NC(GPP_B4, UP_20K), - PAD_NC(GPP_B5, UP_20K), - PAD_NC(GPP_B6, UP_20K), - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* SRCCLKREQ2# / WLAN_CLKREQ# */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* SRCCLKREQ3# / CARD_CLKREQ# */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* SRCCLKREQ4# / SSD2_CLKREQ# */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* SRCCLKREQ5# / SSD1_CLKREQ# */ - PAD_NC(GPP_B11, NONE), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */ - PAD_NC(GPP_B15, UP_20K), - PAD_NC(GPP_B16, UP_20K), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, UP_20K), - PAD_NC(GPP_B19, UP_20K), - PAD_NC(GPP_B20, UP_20K), - PAD_NC(GPP_B21, UP_20K), - PAD_NC(GPP_B22, UP_20K), - PAD_NC(GPP_B23, UP_20K), - - /* ------- GPIO Group GPP_C ------- */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */ - PAD_NC(GPP_C2, UP_20K), - PAD_NC(GPP_C3, UP_20K), - PAD_NC(GPP_C4, UP_20K), - PAD_NC(GPP_C5, UP_20K), - PAD_NC(GPP_C6, UP_20K), - PAD_NC(GPP_C7, UP_20K), - PAD_NC(GPP_C8, UP_20K), - PAD_NC(GPP_C9, UP_20K), - PAD_NC(GPP_C10, UP_20K), - PAD_NC(GPP_C11, UP_20K), - PAD_NC(GPP_C12, UP_20K), - PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPP_C13 / SSD1_PWR_DN# */ - PAD_NC(GPP_C14, UP_20K), - PAD_NC(GPP_C15, UP_20K), - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL */ - PAD_NC(GPP_C18, UP_20K), - PAD_NC(GPP_C19, UP_20K), - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - PAD_NC(GPP_C22, UP_20K), - PAD_NC(GPP_C23, UP_20K), - - /* ------- GPIO Group GPP_D ------- */ - PAD_NC(GPP_D0, UP_20K), - PAD_NC(GPP_D1, UP_20K), - PAD_NC(GPP_D2, UP_20K), - PAD_NC(GPP_D3, UP_20K), - PAD_NC(GPP_D4, UP_20K), - PAD_NC(GPP_D5, UP_20K), - PAD_NC(GPP_D6, UP_20K), - PAD_NC(GPP_D7, UP_20K), - PAD_CFG_GPO(GPP_D8, 1, DEEP), /* SB_BLON */ - PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), /* EC SWI# */ - PAD_NC(GPP_D10, NONE), /* DDR_TYPE_D10 - (unused; there is only one on-board - ram type/model) - */ - PAD_NC(GPP_D11, NONE), /* BOARD_ID - (unused in cb; we already know the - device model) - */ - PAD_NC(GPP_D12, UP_20K), - PAD_NC(GPP_D13, UP_20K), - PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* SSD2_PWR_DN# */ - PAD_NC(GPP_D15, UP_20K), - PAD_NC(GPP_D16, UP_20K), - PAD_NC(GPP_D17, UP_20K), - PAD_NC(GPP_D18, UP_20K), - PAD_NC(GPP_D19, UP_20K), - PAD_NC(GPP_D20, UP_20K), - PAD_NC(GPP_D21, NONE), /* TPM_DET# - (currently unused in cb; there seem - to be no devices without TPM) - */ - PAD_NC(GPP_D22, NONE), /* DDR_TYPE_D22 - (unused in cb; there is only one - on-board ram type) - */ - PAD_NC(GPP_D23, UP_20K), - - /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, UP_20K), - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 */ - PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* SATAXPCIE2 / SATAGP2 */ - PAD_NC(GPP_E3, UP_20K), - PAD_NC(GPP_E4, UP_20K), - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */ - PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* DEVSLP2 */ - PAD_NC(GPP_E7, UP_20K), - PAD_NC(GPP_E8, NONE), - PAD_NC(GPP_E9, NONE), - PAD_NC(GPP_E10, NONE), - PAD_NC(GPP_E11, NONE), - PAD_NC(GPP_E12, NONE), - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPB_HPD0 / MUX_HPD */ - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPC_HPD1 / HDMI_HPD */ - PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), /* EC SMI# */ - PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), /* EC SCI# */ - PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ - PAD_NC(GPP_E18, UP_20K), - PAD_NC(GPP_E19, NONE), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DPPC_CTRLCLK / HDMI_CTRLCLK */ - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DPPC_CTRLDATA / HDMI_CTRLDATA */ - PAD_NC(GPP_E22, UP_20K), - PAD_NC(GPP_E23, UP_20K), - - /* ------- GPIO Group GPP_F ------- */ - PAD_NC(GPP_F0, UP_20K), - PAD_NC(GPP_F1, UP_20K), - PAD_NC(GPP_F2, UP_20K), - PAD_NC(GPP_F3, UP_20K), - PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */ - PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */ - PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */ - PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */ - PAD_NC(GPP_F8, UP_20K), - PAD_NC(GPP_F9, UP_20K), - PAD_NC(GPP_F10, UP_20K), - PAD_NC(GPP_F11, UP_20K), - PAD_NC(GPP_F12, UP_20K), - PAD_NC(GPP_F13, UP_20K), - PAD_NC(GPP_F14, UP_20K), - PAD_NC(GPP_F15, UP_20K), - PAD_NC(GPP_F16, UP_20K), - PAD_NC(GPP_F17, UP_20K), - PAD_NC(GPP_F18, UP_20K), - PAD_NC(GPP_F19, UP_20K), - PAD_NC(GPP_F20, UP_20K), - PAD_NC(GPP_F21, UP_20K), - PAD_NC(GPP_F22, UP_20K), - PAD_NC(GPP_F23, NONE), - - /* ------- GPIO Group GPP_G ------- */ - PAD_NC(GPP_G0, UP_20K), - PAD_NC(GPP_G1, UP_20K), - PAD_NC(GPP_G2, UP_20K), - PAD_NC(GPP_G3, UP_20K), - PAD_NC(GPP_G4, UP_20K), - PAD_NC(GPP_G5, UP_20K), - PAD_NC(GPP_G6, UP_20K), - PAD_NC(GPP_G7, UP_20K), - - /* ------- GPIO Group GPP_H ------- */ - PAD_NC(GPP_H0, UP_20K), - PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# / CNVI_RST# */ - PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), /* MODEM_CLKREQ / CNVI_CLKREQ */ - PAD_NC(GPP_H3, UP_20K), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C2_SDA / SMD_7411 */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C2_SCL / SMC_7411 */ - PAD_NC(GPP_H6, UP_20K), - PAD_NC(GPP_H7, UP_20K), - PAD_NC(GPP_H8, UP_20K), - PAD_NC(GPP_H9, UP_20K), - PAD_NC(GPP_H10, UP_20K), - PAD_NC(GPP_H11, UP_20K), - PAD_NC(GPP_H12, UP_20K), - PAD_NC(GPP_H13, UP_20K), - PAD_NC(GPP_H14, UP_20K), - PAD_NC(GPP_H15, UP_20K), - PAD_NC(GPP_H16, UP_20K), - PAD_NC(GPP_H17, UP_20K), - PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */ - PAD_NC(GPP_H19, UP_20K), - PAD_NC(GPP_H20, UP_20K), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, UP_20K), - PAD_NC(GPP_H23, UP_20K), -}; - -#endif - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339 Gerrit-Change-Number: 47836 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: mb/clevo/cml-u: Get rid of cnl_configure_pads()
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47835 ) Change subject: mb/clevo/cml-u: Get rid of cnl_configure_pads() ...................................................................... mb/clevo/cml-u: Get rid of cnl_configure_pads() Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/ramstage.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47835/1 diff --git a/src/mainboard/clevo/cml-u/ramstage.c b/src/mainboard/clevo/cml-u/ramstage.c index 037409c..824adfc 100644 --- a/src/mainboard/clevo/cml-u/ramstage.c +++ b/src/mainboard/clevo/cml-u/ramstage.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/ramstage.h> +#include <device/device.h> #include <variant/gpio.h> -void mainboard_silicon_init_params(FSP_S_CONFIG *params) +static void init_mainboard(void *chip_info) { - /* Configure pads prior to SiliconInit() in case there's any - dependencies during hardware initialization. */ - cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/47835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c Gerrit-Change-Number: 47835 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb level
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47834 ) Change subject: mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb level ...................................................................... mb/clevo/cml-u: Move bootblock.c and ramstage.c to mb level Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc R src/mainboard/clevo/cml-u/bootblock.c R src/mainboard/clevo/cml-u/ramstage.c M src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc 4 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47834/1 diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc index 3af82dd..de3c774 100644 --- a/src/mainboard/clevo/cml-u/Makefile.inc +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -1,4 +1,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +bootblock-y += bootblock.c + +ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c similarity index 100% rename from src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c rename to src/mainboard/clevo/cml-u/bootblock.c diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c b/src/mainboard/clevo/cml-u/ramstage.c similarity index 100% rename from src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c rename to src/mainboard/clevo/cml-u/ramstage.c diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc index 57ad0ca..0e47d86 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc @@ -1,4 +1,2 @@ -bootblock-y += bootblock.c romstage-y += romstage.c -ramstage-y += ramstage.c SPD_SOURCES = samsung-K4AAG165WA-BCTD -- To view, visit https://review.coreboot.org/c/coreboot/+/47834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266 Gerrit-Change-Number: 47834 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/clevo/cml-u: Move gpio.h to include folder
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47833 ) Change subject: mb/clevo/cml-u: Move gpio.h to include folder ...................................................................... mb/clevo/cml-u: Move gpio.h to include folder Change-Id: I50be3d9b829f624cbe460060c40482047f39774c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Makefile.inc M src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c R src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h M src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c 4 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/47833/1 diff --git a/src/mainboard/clevo/cml-u/Makefile.inc b/src/mainboard/clevo/cml-u/Makefile.inc index 1d9ed2d..3af82dd 100644 --- a/src/mainboard/clevo/cml-u/Makefile.inc +++ b/src/mainboard/clevo/cml-u/Makefile.inc @@ -1,2 +1,4 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c b/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c index 2b67302..427b023 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/bootblock.c @@ -2,7 +2,7 @@ #include <bootblock_common.h> #include <gpio.h> -#include "gpio.h" +#include <variant/gpio.h> void bootblock_mainboard_init(void) { diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.h b/src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h similarity index 100% rename from src/mainboard/clevo/cml-u/variants/l140cu/gpio.h rename to src/mainboard/clevo/cml-u/variants/l140cu/include/variant/gpio.h diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c index 46651e8..037409c 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include "gpio.h" +#include <variant/gpio.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50be3d9b829f624cbe460060c40482047f39774c Gerrit-Change-Number: 47833 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020