coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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3243 discussions

Change in coreboot[master]: mb/asrock/h110m: add libgfxinit support
by Maxim Polyakov (Code Review) 23 Nov '20

23 Nov '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39104 ) Change subject: mb/asrock/h110m: add libgfxinit support ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/39104/10//COMMIT_MSG@7 PS10, Line 7: mb/asrock/h110m: add libgfxinit support I understand, but maybe we should configure ptn3356 bridge somehow? For example, ptn3460: https://github.com/coreboot/coreboot/blob/77cc3267fc970c710299a164ecbc471f9… > Does VGA light up with libgfxinit *before* an OS takes over? No, in the powerdown mode > Also, does VGA work on linux with vendor firmware? Yes, sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/39104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d87413f87d00986111ecb7b046423ff5eac1bf1 Gerrit-Change-Number: 39104 Gerrit-PatchSet: 15 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 23 Nov 2020 15:43:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47808 to look at the new patch set (#8). Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... sb/intel/lynxpoint: Replace hard-coded IDs with defines Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 9 files changed, 81 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47808/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47808 ) Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/47808/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47808/5//COMMIT_MSG@15 PS5, Line 15: Built with BUILD_TIMELESS=1 and generated coreboot.rom stays the same. > Which board, though? I usually write the following: […] Done https://review.coreboot.org/c/coreboot/+/47808/5/src/southbridge/intel/lynx… File src/southbridge/intel/lynxpoint/azalia.c: https://review.coreboot.org/c/coreboot/+/47808/5/src/southbridge/intel/lynx… PS5, Line 136: /* 0x8c20 */ > If you're going to keep the values as comments, why use the defines in the first place? It might be useful to keep the IDs as comments, I don't know. I don't have a strong opinion on that. In the first place I want to give these meaningless numbers a name, and it's also useful if you use them more than once. -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 23 Nov 2020 15:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47808 to look at the new patch set (#7). Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... sb/intel/lynxpoint: Replace hard-coded IDs with defines Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built with BUILD_TIMELESS=1, lenovo/t440p remains identical. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 9 files changed, 81 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47808/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/lynxpoint: Reorder defines for PCI IDs
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47809 ) Change subject: sb/intel/lynxpoint: Reorder defines for PCI IDs ...................................................................... Abandoned Not really an improvement -- To view, visit https://review.coreboot.org/c/coreboot/+/47809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0c568a32a6ce7bf1c27578bbe757747c6b2cae Gerrit-Change-Number: 47809 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47807 ) Change subject: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/47807/3/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/47807/3/src/include/device/pci_ids… PS3, Line 3264: 0x8c06 > This one is RAID_PREM Done https://review.coreboot.org/c/coreboot/+/47807/3/src/include/device/pci_ids… PS3, Line 3270: 0x8c07 > same, this is RAID_PREM Done https://review.coreboot.org/c/coreboot/+/47807/3/src/include/device/pci_ids… PS3, Line 3275: 0x9c07 > RAID_PREM Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Gerrit-Change-Number: 47807 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 23 Nov 2020 14:46:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47808 to look at the new patch set (#6). Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... sb/intel/lynxpoint: Replace hard-coded IDs with defines Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built with BUILD_TIMELESS=1 and generated coreboot.rom stays the same. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 9 files changed, 81 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47808/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets
by Felix Singer (Code Review) 23 Nov '20

23 Nov '20

Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47807 to look at the new patch set (#4). Change subject: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets ...................................................................... include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets Used documents: - 328904-003 - 329003-003 Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/include/device/pci_ids.h 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47807/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Gerrit-Change-Number: 47807 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/fsp2_0: Add soc_validate_fsp_version for FSP version check
by Johnny Lin (Code Review) 23 Nov '20

23 Nov '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47559 ) Change subject: intel/fsp2_0: Add soc_validate_fsp_version for FSP version check ...................................................................... intel/fsp2_0: Add soc_validate_fsp_version for FSP version check Only need to check this once so check it at romstage where the console is usually ready. Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/util.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47559/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index a57b1bb..2d2a58b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -90,6 +90,7 @@ void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); +void soc_validate_fsp_version(const struct fsp_header *hdr); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index acc3f4b..dc54d46 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -85,6 +85,9 @@ return CB_ERR; } + if (ENV_ROMSTAGE) + soc_validate_fsp_version(hdr); + return CB_SUCCESS; } @@ -243,3 +246,5 @@ rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); memcpy(rec->string, fsp_version, len+1); } + +__weak void soc_validate_fsp_version(const struct fsp_header *hdr) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/47559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Gerrit-Change-Number: 47559 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Drop invalid SATA registers
by Angel Pons (Code Review) 23 Nov '20

23 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47097 ) Change subject: sb/intel/lynxpoint: Drop invalid SATA registers ...................................................................... sb/intel/lynxpoint: Drop invalid SATA registers Code was copy-pasted from older chips and has no effect on Lynxpoint. Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 4 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47097/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e..41199da 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -215,51 +215,11 @@ /* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) -#define INTR_LN 0x3c + #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index e4aa083..fdbe062 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -57,22 +57,10 @@ /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/47097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e Gerrit-Change-Number: 47097 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020