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Change in coreboot[master]: soc/intel/common: Add PCIe Runtime D3 driver for ACPI
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46260 ) Change subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI ...................................................................... soc/intel/common: Add PCIe Runtime D3 driver for ACPI This driver is for devices attached to a PCIe root port that support Runtime D3. It creates the necessary PowerResource in the root port to provide _ON/_OFF methods for which will turn off power and clocks to the device when it is in the D3cold state. The mainboard declares the driver in devicetree and provides the GPIOs that control power/reset for the device attached to the root port and the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock. An additional device property is created for storage devices if it matches the PCI storage class which is used to indicate that the storage device should use D3 for power savings. BUG=b:160996445 TEST=boot on volteer device with this driver enabled in the devicetree and disassemble the SSDT to ensure this code exists. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/Kconfig A src/soc/intel/common/block/pcie/rtd3/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/chip.h A src/soc/intel/common/block/pcie/rtd3/rtd3.c 6 files changed, 306 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46260/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index 9c42af6..25cde37 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -7,6 +7,8 @@ if SOC_INTEL_COMMON_BLOCK_PCIE +source "src/soc/intel/common/block/pcie/*/Kconfig" + config PCIEXP_CLK_PM default y diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index 0cded9d..e2ad685 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,2 +1,4 @@ +subdirs-y += ./* + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/rtd3/Kconfig b/src/soc/intel/common/block/pcie/rtd3/Kconfig new file mode 100644 index 0000000..03e13da --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + bool + default n + depends on HAVE_ACPI_TABLES + select PMC_IPC_MAILBOX_ACPI_INTERFACE + help + When enabled, this driver will add support for ACPI controlled + Runtime D3 using GPIOs for power/reset control of the device + attached to a PCIe root port. diff --git a/src/soc/intel/common/block/pcie/rtd3/Makefile.inc b/src/soc/intel/common/block/pcie/rtd3/Makefile.inc new file mode 100644 index 0000000..7edea97 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE_RTD3) += rtd3.c diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h new file mode 100644 index 0000000..062ce30 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ +#define __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ + +#include <acpi/acpi_device.h> + +struct soc_intel_common_block_pcie_rtd3_config { + struct acpi_gpio power_gpio; /* Power GPIO for this device */ + struct acpi_gpio reset_gpio; /* Reset GPIO for this device (optional) */ + unsigned int clock_pin; /* SRCCLK assigned to this root port */ +}; + +#endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c new file mode 100644 index 0000000..0331e95 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci.h> +#include <intelblocks/pmc.h> + +#include "chip.h" + +/* + * This UUID and the resulting ACPI Device Property is defined by the + * Power Management for Storage Hardware Devices: + * + * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelin… + */ +#define PCIE_RTD3_STORAGE_UUID "5025030F-842F-4AB4-A561-99A5189762D0" + +/* Address for start of PCIe port control and status registers. */ +#define PCIE_PXCS_ADDRESS (CONFIG_MMCONF_BASE_ADDRESS + 0xe8000) + +#define PCH_PCIE_PXCS_CFG_LSTS 0x52 /* Link Status Register */ +#define PCH_PCIE_PXCS_CFG_SPR 0xe0 /* Scratchpad */ +#define PCH_PCIE_PXCS_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ +#define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ + +/* + * Delay up to wait_ms until provided register matches expected value. + * + * Local7 = segments + * While (Local7 > 0) + * { + * If (name == val) { + * Break + * } + * Sleep (wait_ms_segment) + * Local7++ + * } + */ +static void pcie_rtd3_delay(uint32_t wait_ms, const char *name, uint64_t val) +{ + uint32_t wait_ms_segment = 1; + uint32_t segments = wait_ms; + + if (wait_ms > 32) { + wait_ms_segment = 16; + segments = wait_ms / 16; + } + + acpigen_write_store_int_to_op(segments, LOCAL7_OP); + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_emit_byte(ZERO_OP); + if (name) { + acpigen_write_if_lequal_namestr_int(name, val); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } + acpigen_write_sleep(wait_ms_segment); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_pop_len(); /* While */ +} + +/* Called from _ON to get PCIe link back to active state. */ +static void pcie_rtd3_l23_exit(void) +{ + /* Skip if port is not in L2/L3. */ + acpigen_write_if_lequal_namestr_int("NCB7", 0); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); + + /* Initiate L2/L3 Ready To Detect transition. */ + acpigen_write_store_int_to_namestr(1, "L23R"); + + /* Wait for transition to detect. */ + pcie_rtd3_delay(320, "L23R", 0); + + /* Once in detect, wait for link active. */ + pcie_rtd3_delay(128, "LASX", 1); + + /* Track state of port if link is active. */ + acpigen_write_if_lequal_namestr_int("LASX", 1); + acpigen_write_store_int_to_namestr(0, "NCB7"); + acpigen_pop_len(); +} + +/* Called from _OFF to put PCIe link into L2/L3 state. */ +static void pcie_rtd3_l23_entry(void) +{ + /* Initiate L2/L3 Entry request. */ + acpigen_write_store_int_to_namestr(1, "L23E"); + + /* Wait for L2/L3 Entry request to clear. */ + pcie_rtd3_delay(128, "L23E", 0); + + /* Track state of port if L2/L3 entry request is clear. */ + acpigen_write_if_lequal_namestr_int("L23E", 0); + acpigen_write_store_int_to_namestr(1, "NCB7"); + acpigen_pop_len(); +} + +static void pcie_rtd3_method_on(unsigned int pcie_rp, unsigned int clock_pin, + const struct acpi_gpio *power_gpio, + const struct acpi_gpio *reset_gpio) +{ + acpigen_write_method_serialized("_ON", 0); + + /* Assert power gpio. */ + acpigen_enable_tx_gpio(power_gpio); + + /* Enable CLKSRC for root port. */ + pmc_acpi_set_pci_clock(pcie_rp, clock_pin, true); + + /* De-assert reset gpio. */ + if (reset_gpio->pin_count) + acpigen_disable_tx_gpio(reset_gpio); + + /* Trigger L3/S3 ready exit flow. */ + pcie_rtd3_l23_exit(); + + acpigen_pop_len(); +} + +static void pcie_rtd3_method_off(int pcie_rp, int clock_pin, + const struct acpi_gpio *power_gpio, + const struct acpi_gpio *reset_gpio) +{ + acpigen_write_method_serialized("_OFF", 0); + + /* Trigger L2/L3 ready entry flow. */ + pcie_rtd3_l23_entry(); + + /* Assert reset gpio. */ + if (reset_gpio->pin_count) + acpigen_enable_tx_gpio(reset_gpio); + + /* Disable CLKSRC for this root port. */ + pmc_acpi_set_pci_clock(pcie_rp, clock_pin, false); + + /* De-assert power gpio. */ + acpigen_disable_tx_gpio(power_gpio); + + acpigen_pop_len(); +} + +static void pcie_rtd3_method_status(const struct acpi_gpio *power_gpio) +{ + acpigen_write_method("_STA", 0); + + /* Read power gpio value into Local0. */ + acpigen_get_tx_gpio(power_gpio); + + acpigen_write_if_lequal_op_op(LOCAL0_OP, ZERO_OP); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); + acpigen_write_else(); + acpigen_write_return_op(ONE_OP); + acpigen_pop_len(); + + acpigen_pop_len(); +} + +static void pcie_rtd3_fill_ssdt(const struct device *dev) +{ + const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); + static const char * const power_res_states[] = { "_PR0", "_PR3" }; + const char *scope = acpi_device_scope(dev); + const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, PCIE_PXCS_ADDRESS, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_LSTS), + FIELDLIST_RESERVED(13), + FIELDLIST_NAMESTR("LASX", 1), /* Link Active Status */ + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_SPR), + FIELDLIST_RESERVED(7), + FIELDLIST_NAMESTR("NCB7", 1), + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_RPPGEN), + FIELDLIST_RESERVED(2), + FIELDLIST_NAMESTR("L23E", 1), /* L23_Rdy Entry Request */ + FIELDLIST_NAMESTR("L23R", 1), /* L23_Rdy Detect Transition */ + }; + uint8_t pcie_rp; + + if (!scope) { + printk(BIOS_ERR, "%s: scope not found: %s\n", __func__, dev_path(dev)); + return; + } + if (!config->power_gpio.pin_count) { + printk(BIOS_ERR, "%s: power gpio not provided for %s.\n", __func__, scope); + return; + } + if (config->clock_pin > CONFIG_MAX_PCIE_CLOCKS) { + printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, + config->clock_pin, scope); + return; + } + + /* Read port number of root port that this device is attached to. */ + pcie_rp = pci_read_config8(dev->bus->dev, PCH_PCIE_CFG_LCAP_PN); + if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { + printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + return; + } + /* Port number is 1-based, PMC IPC method expects 0-based. */ + pcie_rp--; + + printk(BIOS_INFO, "%s: Enable RTD3 for %s\n", scope, dev_path(dev->bus->dev)); + + /* The RTD3 power resource is added to the root port, not the device. */ + acpigen_write_scope(scope); + + acpigen_write_opregion(&opregion); + acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Power resources */ + acpigen_write_power_res("PRIC", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + pcie_rtd3_method_status(&config->power_gpio); + pcie_rtd3_method_on(pcie_rp, config->clock_pin, &config->power_gpio, + &config->reset_gpio); + pcie_rtd3_method_off(pcie_rp, config->clock_pin, &config->power_gpio, + &config->reset_gpio); + + acpigen_pop_len(); /* PowerResource */ + + /* Add property for OS to enable storage D3. */ + if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) { + struct acpi_dp *dsd, *pkg; + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_ADR(0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_name_integer("_S0W", 4); + + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); + acpi_dp_add_integer(pkg, "StorageD3Enable", 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + + printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", + acpi_device_path(dev)); + } + + acpigen_pop_len(); /* Scope */ +} + +static const char *pcie_rtd3_acpi_name(const struct device *dev) +{ + return "RTD3"; +} + +static struct device_operations pcie_rtd3_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = pcie_rtd3_fill_ssdt, + .acpi_name = pcie_rtd3_acpi_name, + .ops_pci = &pci_dev_ops_pci, +}; + +static void pcie_rtd3_enable(struct device *dev) +{ + dev->ops = &pcie_rtd3_ops; +} + +struct chip_operations soc_intel_common_block_pcie_rtd3_ops = { + CHIP_NAME("Intel PCIe Runtime D3") + .enable_dev = pcie_rtd3_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde Gerrit-Change-Number: 46260 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46471 ) Change subject: soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD ...................................................................... soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD Replace the two obsolete LPID implementations with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 UUID on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl D src/soc/intel/common/acpi/lpit.asl D src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 12 files changed, 10 insertions(+), 137 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl index 206119f..1bca44f 100644 --- a/src/mainboard/google/deltaur/dsdt.asl +++ b/src/mainboard/google/deltaur/dsdt.asl @@ -35,9 +35,6 @@ /* VPD support */ #include <vendorcode/google/chromeos/acpi/vpd.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index a6abdb8..92fa2b8 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -39,9 +39,6 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index d2170d0..1395c8f 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -36,9 +36,6 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) { diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 98aa54a..664305e 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,9 +39,6 @@ #include <southbridge/intel/common/acpi/sleepstates.asl> - /* Low power idle table */ - #include <soc/intel/common/acpi/lpit.asl> - #if CONFIG(EC_GOOGLE_WILCO) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index cf73367..ba9541e 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -38,10 +38,6 @@ // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include <soc/intel/common/acpi/lpit.asl> - // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 42f3b12..3d8e554 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -44,8 +44,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 35dc196..fafbbfd 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -46,5 +46,5 @@ /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> -/* PMC Core */ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> diff --git a/src/soc/intel/common/acpi/lpit.asl b/src/soc/intel/common/acpi/lpit.asl deleted file mode 100644 index 6159685..0000000 --- a/src/soc/intel/common/acpi/lpit.asl +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 -#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 - -#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 -#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 -#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 -#define LPID_DSM_ARG2_S0IX_ENTRY 5 -#define LPID_DSM_ARG2_S0IX_EXIT 6 - -External(\_SB.MS0X, MethodObj) -External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) -External(\_SB.PCI0.EGPM, MethodObj) -External(\_SB.PCI0.RGPM, MethodObj) - -Scope(\_SB) -{ - Device(LPID) - { - Name(_ADR, 0x00000000) - Name(_CID, EISAID("PNP0D80")) - Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) - Method(_DSM, 4) - { - If(Arg0 == ^UUID) { - /* - * Enum functions - */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) - } - /* - * Function 1 - Get Device Constraints - */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) - } - /* - * Function 2 - Get Crash Dump Device - */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) - } - /* - * Function 3 - Display Off Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { - } - /* - * Function 4 - Display On Notification - */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { - } - /* - * Function 5 - Low Power S0 Entry Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(1) - } - - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(1) - } - - /* - * Save the current PM bits then - * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG - */ - If (CondRefOf (\_SB.PCI0.EGPM)) - { - \_SB.PCI0.EGPM () - } - } - /* - * Function 6 - Low Power S0 Exit Notification - */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { - /* Inform the EC */ - If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { - \_SB.PCI0.LPCB.EC0.S0IX(0) - } - - /* provide board level S0ix hook */ - If (CondRefOf (\_SB.MS0X)) { - \_SB.MS0X(0) - } - - /* Restore GPIO all Community PM */ - If (CondRefOf (\_SB.PCI0.RGPM)) - { - \_SB.PCI0.RGPM () - } - } - } - - Return(Buffer(One) {0x00}) - } // Method(_DSM) - } // Device (LPID) -} // End Scope(\_SB) diff --git a/src/soc/intel/common/block/acpi/acpi/pmc.asl b/src/soc/intel/common/block/acpi/acpi/pmc.asl deleted file mode 100644 index ddf6470..0000000 --- a/src/soc/intel/common/block/acpi/acpi/pmc.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (PEPD) -{ - Name (_HID, "INT33A1" /* Intel Power Engine */) - Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) - Name (_UID, One) -} diff --git a/src/soc/intel/elkhartlake/acpi/southbridge.asl b/src/soc/intel/elkhartlake/acpi/southbridge.asl index 28705b1..17d1913 100644 --- a/src/soc/intel/elkhartlake/acpi/southbridge.asl +++ b/src/soc/intel/elkhartlake/acpi/southbridge.asl @@ -41,8 +41,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index b82cce5..ebc6fd8 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -47,8 +47,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> /* EMMC/SD card */ #include "scs.asl" diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 42f3b12..3d8e554 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -44,8 +44,8 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> -/* PMC Core*/ -#include <soc/intel/common/block/acpi/acpi/pmc.asl> +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: add _HID to PEPD
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46469 ) Change subject: soc/intel/common/acpi: add _HID to PEPD ...................................................................... soc/intel/common/acpi: add _HID to PEPD Add the _HID INT33A1 to PEPD to make Linux recognize it as "Intel Power Engine" in the pmc core driver. The _ADR gets dropped, because _HID and _ADR are mutually exclusive. Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46469 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index ef67076..b6a0d9d 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -16,7 +16,7 @@ Device(PEPD) { - Name(_ADR, 0x00000000) + Name(_HID, "INT33A1") /* Intel Power Engine */ Name(_CID, EISAID("PNP0D80")) Method(_DSM, 4) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Gerrit-Change-Number: 46469 Gerrit-PatchSet: 12 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: correct return value for PEPD enum function
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47140 ) Change subject: soc/intel/common/acpi: correct return value for PEPD enum function ...................................................................... soc/intel/common/acpi: correct return value for PEPD enum function The PEPD enum function returns a bitmask to announce supported/enabled PEPD functions. Add a comment describing this bitmask and correct the return value to announce function 1, 5 and 6 as supported. Also add comments to the disabled functions 3 and 4. Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47140 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 9e39a8f..ef67076 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -26,7 +26,12 @@ * Enum functions */ If(Arg2 == PEPD_DSM_LPI_ENUM_FUNCTIONS) { - Return(Buffer(One) {0x60}) + /* + * Supported functions bitmask + * bit 0: other functions than 0 are supported + * bits 1-6: function x supported + */ + Return(Buffer(1) {0x63}) } /* * Function 1 - Get Device Constraints @@ -56,16 +61,19 @@ * Function 2 - Get Crash Dump Device */ If(Arg2 == PEPD_DSM_LPI_GET_CRASH_DUMP_DEV) { + /* not yet used and not advertised by function 0 */ } /* * Function 3 - Display Off Notification */ If(Arg2 == PEPD_DSM_LPI_DISPLAY_OFF_NOTIFY) { + /* not yet used and not advertised by function 0 */ } /* * Function 4 - Display On Notification */ If(Arg2 == PEPD_DSM_LPI_DISPLAY_ON_NOTIFY) { + /* not yet used and not advertised by function 0 */ } /* * Function 5 - Low Power S0 Entry Notification -- To view, visit https://review.coreboot.org/c/coreboot/+/47140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed Gerrit-Change-Number: 47140 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. At least the following Windows versions were verified to be affected: - Windows 8.1 x64, release 6.3.9600 - Windoes 10 x64, version 1809, build 17763.379 - Windows 10 x64, version 1903, build 18362.53 - Windows 10 x64, version 2004, build 19041.508 - Windows 10 x64, version 20H2 / 2009, build 19042.450 To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries could be added at a later point, if needed. Note: to fully prevent the BSOD mentioned above the LPIT table is required on Windows, too. The patch for this is WIP, see CB:32350. If you want to test this, you need to applie the whole ACPI patch series including the hacky LPIT test implementation from CB:47242: https://review.coreboot.org/q/topic:%22low_power_idle_fix%22 Test: no bluescreen anymore on Clevo L140CU on all Windows versions listed above and S0ix gets detected in `powercfg -a`. Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 64d23c1..9e39a8f 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -30,9 +30,27 @@ } /* * Function 1 - Get Device Constraints + * + * Device constraints for low power states (may be used for debugging). + * For now there is only one disabled dummy device, because Windows + * expects at least one device and crashes without it with a bluescreen + * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. */ If(Arg2 == PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS) { - Return(Package(5) {0, Ones, Ones, Ones, Ones}) + Return (Package() { + Package() { + "\\DUMY", /* \DUMY - not existent */ + 0, /* disabled, no constraints */ + Package() { + 0, /* revision */ + Package() { + 0xff, /* apply to all LPIT states */ + 0 /* minimum D-state */ + } + } + } + } + ) } /* * Function 2 - Get Crash Dump Device -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: drop return value for disabled PEPD function 2
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47139 ) Change subject: soc/intel/common/acpi: drop return value for disabled PEPD function 2 ...................................................................... soc/intel/common/acpi: drop return value for disabled PEPD function 2 PEPD function 2 is currently unused and disabled. Thus, drop the return value, which matches the default return value. Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47139 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 2e822db..64d23c1 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -38,7 +38,6 @@ * Function 2 - Get Crash Dump Device */ If(Arg2 == PEPD_DSM_LPI_GET_CRASH_DUMP_DEV) { - Return(Buffer(One) {0x0}) } /* * Function 3 - Display Off Notification -- To view, visit https://review.coreboot.org/c/coreboot/+/47139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda Gerrit-Change-Number: 47139 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: rename PEPD/LPI macros for clarification
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47247 ) Change subject: soc/intel/common/acpi: rename PEPD/LPI macros for clarification ...................................................................... soc/intel/common/acpi: rename PEPD/LPI macros for clarification `ARG2` in the macro's names does not really provide any useful information. Drop it and add `LPI` to clarify the relation to only low-power idle states. Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47247 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 1bbecef..2e822db 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define PEPD_DSM_ARG2_ENUM_FUNCTIONS 0 -#define PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 +#define PEPD_DSM_LPI_ENUM_FUNCTIONS 0 +#define PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS 1 -#define PEPD_DSM_ARG2_GET_CRASH_DUMP_DEV 2 -#define PEPD_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 -#define PEPD_DSM_ARG2_DISPLAY_ON_NOTIFY 4 -#define PEPD_DSM_ARG2_S0IX_ENTRY 5 -#define PEPD_DSM_ARG2_S0IX_EXIT 6 +#define PEPD_DSM_LPI_GET_CRASH_DUMP_DEV 2 +#define PEPD_DSM_LPI_DISPLAY_OFF_NOTIFY 3 +#define PEPD_DSM_LPI_DISPLAY_ON_NOTIFY 4 +#define PEPD_DSM_LPI_S0IX_ENTRY 5 +#define PEPD_DSM_LPI_S0IX_EXIT 6 External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) @@ -25,35 +25,35 @@ /* * Enum functions */ - If(Arg2 == PEPD_DSM_ARG2_ENUM_FUNCTIONS) { + If(Arg2 == PEPD_DSM_LPI_ENUM_FUNCTIONS) { Return(Buffer(One) {0x60}) } /* * Function 1 - Get Device Constraints */ - If(Arg2 == PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + If(Arg2 == PEPD_DSM_LPI_GET_DEVICE_CONSTRAINTS) { Return(Package(5) {0, Ones, Ones, Ones, Ones}) } /* * Function 2 - Get Crash Dump Device */ - If(Arg2 == PEPD_DSM_ARG2_GET_CRASH_DUMP_DEV) { + If(Arg2 == PEPD_DSM_LPI_GET_CRASH_DUMP_DEV) { Return(Buffer(One) {0x0}) } /* * Function 3 - Display Off Notification */ - If(Arg2 == PEPD_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + If(Arg2 == PEPD_DSM_LPI_DISPLAY_OFF_NOTIFY) { } /* * Function 4 - Display On Notification */ - If(Arg2 == PEPD_DSM_ARG2_DISPLAY_ON_NOTIFY) { + If(Arg2 == PEPD_DSM_LPI_DISPLAY_ON_NOTIFY) { } /* * Function 5 - Low Power S0 Entry Notification */ - If(Arg2 == PEPD_DSM_ARG2_S0IX_ENTRY) { + If(Arg2 == PEPD_DSM_LPI_S0IX_ENTRY) { /* Inform the EC */ If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX(1) @@ -76,7 +76,7 @@ /* * Function 6 - Low Power S0 Exit Notification */ - If(Arg2 == PEPD_DSM_ARG2_S0IX_EXIT) { + If(Arg2 == PEPD_DSM_LPI_S0IX_EXIT) { /* Inform the EC */ If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX(0) -- To view, visit https://review.coreboot.org/c/coreboot/+/47247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6 Gerrit-Change-Number: 47247 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/kontron: Add Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 20 Nov '20

20 Nov '20

Hello Felix Singer, build bot (Jenkins), Patrick Georgi, Angel Pons, Andrey Petrov, Patrick Rudolph, Aaron Durbin, Lance Zhao, Nico Huber, Martin Roth, Werner Zeh, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39133 to look at the new patch set (#58). Change subject: mb/kontron: Add Kontron mAL10 COMe module support ...................................................................... mb/kontron: Add Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/kontron/mal10.md A src/mainboard/kontron/mal10/Kconfig A src/mainboard/kontron/mal10/Kconfig.name A src/mainboard/kontron/mal10/Makefile.inc A src/mainboard/kontron/mal10/acpi/dptf.asl A src/mainboard/kontron/mal10/board_info.txt A src/mainboard/kontron/mal10/bootblock.c A src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc A src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt A src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c A src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h A src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb A src/mainboard/kontron/mal10/cmos.default A src/mainboard/kontron/mal10/cmos.layout A src/mainboard/kontron/mal10/dsdt.asl A src/mainboard/kontron/mal10/mal10.fmd A src/mainboard/kontron/mal10/ramstage.c A src/mainboard/kontron/mal10/romstage.c A src/mainboard/kontron/mal10/variants/mal10/Makefile.inc A src/mainboard/kontron/mal10/variants/mal10/board_info.txt A src/mainboard/kontron/mal10/variants/mal10/data.vbt A src/mainboard/kontron/mal10/variants/mal10/devicetree.cb A src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads A src/mainboard/kontron/mal10/variants/mal10/gpio.c A src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h 26 files changed, 954 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/39133/58 -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 58 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... soc/intel/common/acpi: rename LPID to PEPD Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In Device" and is the name Intel and vendors usually use, so let's comply. Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46470 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl M src/mainboard/google/volteer/mainboard.asl M src/soc/intel/common/block/acpi/acpi/pep.asl 5 files changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index 5ba7be7..6219f27 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -4,7 +4,7 @@ #define TS_PD GPP_E7 #define HDMI_PD GPP_E16 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 6bc145a..96783ca 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -3,7 +3,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 6bc145a..96783ca 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -3,7 +3,7 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 -/* Method called from LPIT prior to enter s0ix state */ +/* Method called from PEPD prior to enter s0ix state */ Method (MS0X, 1) { If (Arg0) { diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl index e2f6d11..0e9bb8c 100644 --- a/src/mainboard/google/volteer/mainboard.asl +++ b/src/mainboard/google/volteer/mainboard.asl @@ -30,7 +30,7 @@ /* * S0ix Entry/Exit Notifications - * Called from \_SB.LPID._DSM + * Called from \_SB.PEPD._DSM */ Method (MS0X, 1, Serialized) { diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 0d9f1c9..1bbecef 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -1,20 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 -#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 +#define PEPD_DSM_ARG2_ENUM_FUNCTIONS 0 +#define PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 -#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 -#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 -#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 -#define LPID_DSM_ARG2_S0IX_ENTRY 5 -#define LPID_DSM_ARG2_S0IX_EXIT 6 +#define PEPD_DSM_ARG2_GET_CRASH_DUMP_DEV 2 +#define PEPD_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 +#define PEPD_DSM_ARG2_DISPLAY_ON_NOTIFY 4 +#define PEPD_DSM_ARG2_S0IX_ENTRY 5 +#define PEPD_DSM_ARG2_S0IX_EXIT 6 External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) External(\_SB.PCI0.EGPM, MethodObj) External(\_SB.PCI0.RGPM, MethodObj) -Device(LPID) +Device(PEPD) { Name(_ADR, 0x00000000) Name(_CID, EISAID("PNP0D80")) @@ -25,35 +25,35 @@ /* * Enum functions */ - If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + If(Arg2 == PEPD_DSM_ARG2_ENUM_FUNCTIONS) { Return(Buffer(One) {0x60}) } /* * Function 1 - Get Device Constraints */ - If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + If(Arg2 == PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { Return(Package(5) {0, Ones, Ones, Ones, Ones}) } /* * Function 2 - Get Crash Dump Device */ - If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + If(Arg2 == PEPD_DSM_ARG2_GET_CRASH_DUMP_DEV) { Return(Buffer(One) {0x0}) } /* * Function 3 - Display Off Notification */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + If(Arg2 == PEPD_DSM_ARG2_DISPLAY_OFF_NOTIFY) { } /* * Function 4 - Display On Notification */ - If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + If(Arg2 == PEPD_DSM_ARG2_DISPLAY_ON_NOTIFY) { } /* * Function 5 - Low Power S0 Entry Notification */ - If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + If(Arg2 == PEPD_DSM_ARG2_S0IX_ENTRY) { /* Inform the EC */ If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX(1) @@ -76,7 +76,7 @@ /* * Function 6 - Low Power S0 Exit Notification */ - If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + If(Arg2 == PEPD_DSM_ARG2_S0IX_EXIT) { /* Inform the EC */ If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { \_SB.PCI0.LPCB.EC0.S0IX(0) @@ -97,4 +97,4 @@ Return(Buffer(One) {0x00}) } // Method(_DSM) -} // Device (LPID) +} // Device (PEPD) -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: move S0ix UUID to the condition
by Nico Huber (Code Review) 20 Nov '20

20 Nov '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: move S0ix UUID to the condition ...................................................................... soc/intel/common/acpi: move S0ix UUID to the condition Move the UUID to the condition, since there is no need to assign a name when it is only used once. Also add a comment to make clear that the functions inside that condition are only used by the Low Power Idle S0 functionality, while the PEPD in general can be present on boards without S0ix capability, too. For details check CB:46469. Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46468 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl index 19ec558..0d9f1c9 100644 --- a/src/soc/intel/common/block/acpi/acpi/pep.asl +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -18,10 +18,10 @@ { Name(_ADR, 0x00000000) Name(_CID, EISAID("PNP0D80")) - Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) Method(_DSM, 4) { - If(Arg0 == ^UUID) { + /* Low Power Idle S0 helper */ + If(Arg0 == ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) { /* * Enum functions */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2020