coreboot-gerrit November 2020

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Change in coreboot[master]: mb/kontron/bsl6: Configure GPIOs using mainboard_ops
by Felix Singer (Code Review) 24 Nov '20

24 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47850 ) Change subject: mb/kontron/bsl6: Configure GPIOs using mainboard_ops ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Gerrit-Change-Number: 47850 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 24 Nov 2020 22:25:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47851 ) Change subject: mb/kontron/bsl6: Move GPIO configuration to C file ...................................................................... mb/kontron/bsl6: Move GPIO configuration to C file Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/kontron/bsl6/Makefile.inc A src/mainboard/kontron/bsl6/gpio.c M src/mainboard/kontron/bsl6/include/mainboard/gpio.h M src/mainboard/kontron/bsl6/ramstage.c 4 files changed, 229 insertions(+), 225 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc index 49c9a6c..5164272 100644 --- a/src/mainboard/kontron/bsl6/Makefile.inc +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -6,6 +6,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c +ramstage-y += gpio.c ramstage-y += ramstage.c - ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/kontron/bsl6/gpio.c b/src/mainboard/kontron/bsl6/gpio.c new file mode 100644 index 0000000..c99a53d --- /dev/null +++ b/src/mainboard/kontron/bsl6/gpio.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A21, 1, DEEP), + PAD_CFG_GPO(GPP_A22, 1, DEEP), + PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + + PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B6, 1, DEEP), + PAD_CFG_GPO(GPP_B7, 1, DEEP), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_CFG_GPO(GPP_B9, 1, DEEP), + PAD_CFG_GPO(GPP_B10, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_B17, 1, DEEP), + PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), + PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), + + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), + /* XXX: C6 not readable */ + /* XXX: C7 not readable */ + PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), + + PAD_CFG_GPO(GPP_D0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D3, 1, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), + PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), + PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), + PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), + PAD_CFG_GPO(GPP_D19, 0, DEEP), + PAD_CFG_GPO(GPP_D20, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 1, DEEP), + PAD_CFG_GPO(GPP_D22, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), + PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), + PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), + PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), + PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F18, 1, PLTRST), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + + PAD_CFG_GPO(GPP_G0, 1, PLTRST), + PAD_CFG_GPO(GPP_G1, 1, PLTRST), + PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), + PAD_CFG_GPO(GPP_G4, 1, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G7, 1, DEEP), + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_G22, 1, PLTRST), + PAD_CFG_GPO(GPP_G23, 1, PLTRST), + + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO(GPP_H1, 1, DEEP), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), + PAD_CFG_GPO(GPP_H4, 1, DEEP), + PAD_CFG_GPO(GPP_H5, 1, DEEP), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 1, DEEP), + PAD_CFG_GPO(GPP_H8, 1, DEEP), + PAD_CFG_GPO(GPP_H9, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPD1, 0, PWROK), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD9, 0, PWROK), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/bsl6/include/mainboard/gpio.h b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h index d6e976e..ef2a21c 100644 --- a/src/mainboard/kontron/bsl6/include/mainboard/gpio.h +++ b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h @@ -3,228 +3,6 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -#include <soc/gpe.h> -#include <soc/gpio.h> - -#ifndef __ACPI__ - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_A12, 1, PLTRST), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_A20, 1, DEEP), - PAD_CFG_GPO(GPP_A21, 1, DEEP), - PAD_CFG_GPO(GPP_A22, 1, DEEP), - PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), - - PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_B3, 1, DEEP), - PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_B6, 1, DEEP), - PAD_CFG_GPO(GPP_B7, 1, DEEP), - PAD_CFG_GPO(GPP_B8, 1, DEEP), - PAD_CFG_GPO(GPP_B9, 1, DEEP), - PAD_CFG_GPO(GPP_B10, 1, DEEP), - PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_B17, 1, DEEP), - PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), - PAD_CFG_TERM_GPO(GPP_B23, 1, UP_20K, DEEP), - - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPI_SCI(GPP_C2, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), - /* XXX: C6 not readable */ - /* XXX: C7 not readable */ - PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), - - PAD_CFG_GPO(GPP_D0, 1, DEEP), - PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), - PAD_CFG_GPO(GPP_D3, 1, DEEP), - PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), - PAD_CFG_GPO(GPP_D9, 0, DEEP), - PAD_CFG_GPO(GPP_D10, 0, DEEP), - PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), - PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), - PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_D17, 0, DEEP), - PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), - PAD_CFG_GPO(GPP_D19, 0, DEEP), - PAD_CFG_GPO(GPP_D20, 0, DEEP), - PAD_CFG_GPO(GPP_D21, 1, DEEP), - PAD_CFG_GPO(GPP_D22, 0, DEEP), - PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), - - PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), - PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), - PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), - PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI(GPP_E7, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), - PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), - PAD_CFG_GPI_SCI(GPP_F5, NONE, DEEP, EDGE_SINGLE, NONE), - PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), - PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), - PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), - PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_F18, 1, PLTRST), - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_F22, 1, PLTRST), - PAD_CFG_GPO(GPP_F23, 1, DEEP), - - PAD_CFG_GPO(GPP_G0, 1, PLTRST), - PAD_CFG_GPO(GPP_G1, 1, PLTRST), - PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), - PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), - PAD_CFG_GPO(GPP_G4, 1, DEEP), - PAD_CFG_GPI_APIC_HIGH(GPP_G5, NONE, PLTRST), - PAD_CFG_GPI_SCI(GPP_G6, NONE, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G7, 1, DEEP), - PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), - PAD_CFG_GPI_SCI(GPP_G12, DN_20K, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G13, 1, PLTRST), - PAD_CFG_GPI_SCI(GPP_G14, NONE, PLTRST, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G15, 0, PLTRST), - PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), - PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), - PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), - PAD_CFG_GPI_APIC_HIGH(GPP_G20, NONE, PLTRST), - PAD_CFG_GPI_SCI(GPP_G21, NONE, DEEP, EDGE_SINGLE, INVERT), - PAD_CFG_GPO(GPP_G22, 1, PLTRST), - PAD_CFG_GPO(GPP_G23, 1, PLTRST), - - PAD_CFG_GPO(GPP_H0, 1, DEEP), - PAD_CFG_GPO(GPP_H1, 1, DEEP), - PAD_CFG_GPO(GPP_H2, 1, DEEP), - PAD_CFG_GPO(GPP_H3, 1, DEEP), - PAD_CFG_GPO(GPP_H4, 1, DEEP), - PAD_CFG_GPO(GPP_H5, 1, DEEP), - PAD_CFG_GPO(GPP_H6, 1, DEEP), - PAD_CFG_GPO(GPP_H7, 1, DEEP), - PAD_CFG_GPO(GPP_H8, 1, DEEP), - PAD_CFG_GPO(GPP_H9, 1, DEEP), - PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), - PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), - PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), - PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H17, 1, PLTRST), - PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H23, 0, DEEP), - - PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPD1, 0, PWROK), - PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD7, 1, PWROK), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_CFG_GPO(GPD9, 0, PWROK), - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), - PAD_CFG_NF(GPD11, NONE, PWROK, NF1), - - PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), -}; - -#endif +void mainboard_configure_gpios(void); #endif diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index b26c62f..19518f7 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -5,5 +5,5 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Gerrit-Change-Number: 47851 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47851 ) Change subject: mb/kontron/bsl6: Move GPIO configuration to C file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Gerrit-Change-Number: 47851 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 20:23:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Use include folder for header files
by Felix Singer (Code Review) 24 Nov '20

24 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47849 ) Change subject: mb/kontron/bsl6: Use include folder for header files ...................................................................... mb/kontron/bsl6: Use include folder for header files Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/kontron/bsl6/Makefile.inc R src/mainboard/kontron/bsl6/include/mainboard/gpio.h R src/mainboard/kontron/bsl6/include/variant.h M src/mainboard/kontron/bsl6/ramstage.c M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/kontron/bsl6/variants/boxer26/romstage.c M src/mainboard/kontron/bsl6/variants/bsl6/romstage.c 7 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47849/1 diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc index 1e12ee4..49c9a6c 100644 --- a/src/mainboard/kontron/bsl6/Makefile.inc +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c romstage-y += variants/$(VARIANT_DIR)/romstage.c diff --git a/src/mainboard/kontron/bsl6/gpio.h b/src/mainboard/kontron/bsl6/include/mainboard/gpio.h similarity index 100% rename from src/mainboard/kontron/bsl6/gpio.h rename to src/mainboard/kontron/bsl6/include/mainboard/gpio.h diff --git a/src/mainboard/kontron/bsl6/variant.h b/src/mainboard/kontron/bsl6/include/variant.h similarity index 100% rename from src/mainboard/kontron/bsl6/variant.h rename to src/mainboard/kontron/bsl6/include/variant.h diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c index 2664a4f..b26c62f 100644 --- a/src/mainboard/kontron/bsl6/ramstage.c +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include "gpio.h" +#include <mainboard/gpio.h> void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index 9d9169c..0cb7b06 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -8,8 +8,7 @@ #include <soc/romstage.h> #include <fsp/soc_binding.h> #include <pc80/mc146818rtc.h> - -#include "variant.h" +#include <variant.h> /* Rcomp resistor */ static const u16 rcomp_resistors[3] = { 121, 75, 100 }; diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c index 9c14d84..f1409e0 100644 --- a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -5,8 +5,7 @@ #include <console/console.h> #include <pc80/mc146818rtc.h> #include <fsp/soc_binding.h> - -#include "../../variant.h" +#include <variant.h> void variant_memory_init_params(FSPM_UPD *const mupd) { diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c index 8b32bf5..c9122c1 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <fsp/soc_binding.h> - -#include "../../variant.h" +#include <variant.h> void variant_memory_init_params(FSPM_UPD *const mupd) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272 Gerrit-Change-Number: 47849 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Felix Singer (Code Review) 24 Nov '20

24 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47851 ) Change subject: mb/kontron/bsl6: Move GPIO configuration to C file ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/47851/2/src/mainboard/kontron/bsl6… File src/mainboard/kontron/bsl6/ramstage.c: https://review.coreboot.org/c/coreboot/+/47851/2/src/mainboard/kontron/bsl6… PS2, Line 6: void mainboard_silicon_init_params(FSP_SIL_UPD *params) > Btw. this can also be done in the mainboard's chip_operation's .init, I […] This is done in CB:47850 -- To view, visit https://review.coreboot.org/c/coreboot/+/47851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Gerrit-Change-Number: 47851 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 20:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Nico Huber (Code Review) 24 Nov '20

24 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47851 ) Change subject: mb/kontron/bsl6: Move GPIO configuration to C file ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/47851/2/src/mainboard/kontron/bsl6… File src/mainboard/kontron/bsl6/ramstage.c: https://review.coreboot.org/c/coreboot/+/47851/2/src/mainboard/kontron/bsl6… PS2, Line 6: void mainboard_silicon_init_params(FSP_SIL_UPD *params) Btw. this can also be done in the mainboard's chip_operation's .init, I guess. Not sure why I didn't take care of it during review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Gerrit-Change-Number: 47851 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 19:46:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Nico Huber (Code Review) 24 Nov '20

24 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47851 ) Change subject: mb/kontron/bsl6: Move GPIO configuration to C file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7 Gerrit-Change-Number: 47851 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 19:44:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/kontron/bsl6: Move GPIO configuration to C file
by Felix Singer (Code Review) 24 Nov '20

24 Nov '20

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47808 ) Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... sb/intel/lynxpoint: Replace hard-coded IDs with defines Replace hard-coded IDs with defines introduced in CB:47807. Used documents: - 328904-003 - 329003-003 Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47808 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/smbus.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 9 files changed, 79 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 68958f0..ef450a5 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -132,7 +132,11 @@ .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x8c20, 0x9c20, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_H_AUDIO, + PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 232ad2e..915c181 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -787,26 +787,27 @@ /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */ static const unsigned short pci_device_ids[] = { - 0x8c41, /* Mobile Full Featured Engineering Sample. */ - 0x8c42, /* Desktop Full Featured Engineering Sample. */ - 0x8c44, /* Z87 SKU */ - 0x8c46, /* Z85 SKU */ - 0x8c49, /* HM86 SKU */ - 0x8c4a, /* H87 SKU */ - 0x8c4b, /* HM87 SKU */ - 0x8c4c, /* Q85 SKU */ - 0x8c4e, /* Q87 SKU */ - 0x8c4f, /* QM87 SKU */ - 0x8c50, /* B85 SKU */ - 0x8c52, /* C222 SKU */ - 0x8c54, /* C224 SKU */ - 0x8c56, /* C226 SKU */ - 0x8c5c, /* H81 SKU */ - 0x9c41, /* LP Full Featured Engineering Sample */ - 0x9c43, /* LP Premium SKU */ - 0x9c45, /* LP Mainstream SKU */ - 0x9c47, /* LP Value SKU */ - 0 }; + PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_Z87, + PCI_DEVICE_ID_INTEL_LPT_Z85, + PCI_DEVICE_ID_INTEL_LPT_HM86, + PCI_DEVICE_ID_INTEL_LPT_H87, + PCI_DEVICE_ID_INTEL_LPT_HM87, + PCI_DEVICE_ID_INTEL_LPT_Q85, + PCI_DEVICE_ID_INTEL_LPT_Q87, + PCI_DEVICE_ID_INTEL_LPT_QM87, + PCI_DEVICE_ID_INTEL_LPT_B85, + PCI_DEVICE_ID_INTEL_LPT_C222, + PCI_DEVICE_ID_INTEL_LPT_C224, + PCI_DEVICE_ID_INTEL_LPT_C226, + PCI_DEVICE_ID_INTEL_LPT_H81, + PCI_DEVICE_ID_INTEL_LPT_LP_SAMPLE, + PCI_DEVICE_ID_INTEL_LPT_LP_PREMIUM, + PCI_DEVICE_ID_INTEL_LPT_LP_MAINSTREAM, + PCI_DEVICE_ID_INTEL_LPT_LP_VALUE, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f32ee5b..9910658 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -836,8 +836,8 @@ }; static const unsigned short pci_device_ids[] = { - 0x8c3a, /* Mobile */ - 0x9c3a, /* Low Power */ + PCI_DEVICE_ID_INTEL_LPT_H_MEI, + PCI_DEVICE_ID_INTEL_LPT_LP_MEI, 0 }; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 19eb9fa..5f21e61 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -749,10 +749,20 @@ }; static const unsigned short pci_device_ids[] = { - /* Lynxpoint Mobile */ - 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, - /* Lynxpoint Low Power */ - 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6, 0 }; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 6899e81..a0a606d 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -214,9 +214,22 @@ }; static const unsigned short pci_device_ids[] = { - 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ - 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ - 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45, + PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45, + PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM, + PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2, 0 }; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 199cf9f..d212d88 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -228,14 +228,14 @@ }; static const unsigned short pci_device_ids[] = { - 0x9c60, /* 0:15.0 - SDMA */ - 0x9c61, /* 0:15.1 - I2C0 */ - 0x9c62, /* 0:15.2 - I2C1 */ - 0x9c65, /* 0:15.3 - SPI0 */ - 0x9c66, /* 0:15.4 - SPI1 */ - 0x9c63, /* 0:15.5 - UART0 */ - 0x9c64, /* 0:15.6 - UART1 */ - 0x9c35, /* 0:17.0 - SDIO */ + PCI_DEVICE_ID_INTEL_LPT_LP_SDMA, + PCI_DEVICE_ID_INTEL_LPT_LP_I2C0, + PCI_DEVICE_ID_INTEL_LPT_LP_I2C1, + PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0, + PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1, + PCI_DEVICE_ID_INTEL_LPT_LP_UART0, + PCI_DEVICE_ID_INTEL_LPT_LP_UART1, + PCI_DEVICE_ID_INTEL_LPT_LP_SD, 0 }; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 2741951..d0a621e 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -80,7 +80,8 @@ }; static const unsigned short pci_device_ids[] = { - 0x8c22, 0x9c22, + PCI_DEVICE_ID_INTEL_LPT_H_SMBUS, + PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS, 0 }; diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index f121aa8..d718ab3 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -169,7 +169,12 @@ .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x9c26, 0x8c26, 0x8c2d, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_LP_EHCI, + PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1, + PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 6a58d41..d4611a7 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -342,9 +342,11 @@ .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x8c31, /* LynxPoint-H */ - 0x9c31, /* LynxPoint-LP */ - 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_LPT_H_XHCI, + PCI_DEVICE_ID_INTEL_LPT_LP_XHCI, + 0 +}; static const struct pci_driver pch_usb_xhci __pci_driver = { .ops = &usb_xhci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/lynxpoint: Replace hard-coded IDs with defines
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47808 ) Change subject: sb/intel/lynxpoint: Replace hard-coded IDs with defines ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc Gerrit-Change-Number: 47808 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 18:37:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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