coreboot-gerrit November 2020

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Change in coreboot[master]: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47807 ) Change subject: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets ...................................................................... include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets Used documents: - 328904-003 - 329003-003 Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47807 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h 1 file changed, 55 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index ebf02a8..c123002 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2777,6 +2777,9 @@ #define PCI_DID_INTEL_IBEXPEAK_HECI1 0x3b64 #define PCI_DID_INTEL_IBEXPEAK_THERMAL 0x3b32 +/* Intel SDMA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SDMA 0x9c60 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 @@ -2989,6 +2992,21 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_ESPI_31 0x7a9f /* Intel PCIE device ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP2 0x8c12 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP3 0x8c14 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP4 0x8c16 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP5 0x8c18 +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP6 0x8c1a +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP7 0x8c1c +#define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP8 0x8c1e +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP1 0x9c10 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP2 0x9c12 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP3 0x9c14 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP4 0x9c16 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP5 0x9c18 +#define PCI_DEVICE_ID_INTEL_LPT_LP_PCIE_RP6 0x9c1a + #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 @@ -3268,6 +3286,23 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PCIE_RP28 0x7acb /* Intel SATA device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_1 0x8c04 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM 0x8c06 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45 0x8c08 +#define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_RAID_2 0x8c0e +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE 0x8c01 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_AHCI 0x8c03 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_1 0x8c05 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM 0x8c07 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_IDE_P45 0x8c09 +#define PCI_DEVICE_ID_INTEL_LPT_H_MOBILE_SATA_RAID_2 0x8c0f +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_1 0x9c05 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_PREM 0x9c07 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SATA_RAID_2 0x9c0f + #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 #define PCI_DEVICE_ID_INTEL_SPT_KBL_SATA 0x282a @@ -3337,6 +3372,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 /* Intel I2C device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 +#define PCI_DEVICE_ID_INTEL_LPT_LP_I2C1 0x9c62 #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 #define PCI_DEVICE_ID_INTEL_SPT_I2C1 0x9d61 #define PCI_DEVICE_ID_INTEL_SPT_I2C2 0x9d62 @@ -3428,6 +3465,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_I2C5 0x7afd /* Intel UART device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 +#define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64 #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 #define PCI_DEVICE_ID_INTEL_SPT_UART1 0x9d28 #define PCI_DEVICE_ID_INTEL_SPT_UART2 0x9d66 @@ -3487,6 +3526,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_UART6 0x7adf /* Intel SPI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 +#define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66 #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 #define PCI_DEVICE_ID_INTEL_SPT_SPI2 0x9d29 #define PCI_DEVICE_ID_INTEL_SPT_SPI3 0x9d2a @@ -3786,6 +3827,8 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_ID_8 0x4661 #define PCI_DEVICE_ID_INTEL_ADL_P_ID_9 0x467f /* Intel SMBUS device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 +#define PCI_DEVICE_ID_INTEL_LPT_LP_SMBUS 0x9c22 #define PCI_DEVICE_ID_INTEL_APL_SMBUS 0x5ad4 #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 #define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123 @@ -3802,7 +3845,14 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 +/* Intel EHCI device IDs */ +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 +#define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_2 0x8c2d +#define PCI_DEVICE_ID_INTEL_LPT_LP_EHCI 0x9c26 + /* Intel XHCI device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_XHCI 0x8c31 +#define PCI_DEVICE_ID_INTEL_LPT_LP_XHCI 0x9c31 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 #define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8 #define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f @@ -3856,6 +3906,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_SRAM 0x7aa7 /* Intel AUDIO device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 +#define PCI_DEVICE_ID_INTEL_LPT_LP_AUDIO 0x9c20 #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 #define PCI_DEVICE_ID_INTEL_GLK_AUDIO 0x3198 #define PCI_DEVICE_ID_INTEL_CNL_AUDIO 0x9dc8 @@ -3883,6 +3935,8 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_AUDIO 0x51c8 /* Intel HECI/ME device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a +#define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a #define PCI_DEVICE_ID_INTEL_GLK_CSE0 0x319a #define PCI_DEVICE_ID_INTEL_CNL_CSE0 0x9de0 @@ -3932,6 +3986,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 /* Intel SD device Ids */ +#define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca #define PCI_DEVICE_ID_INTEL_SKL_SD 0x9d2d -- To view, visit https://review.coreboot.org/c/coreboot/+/47807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Gerrit-Change-Number: 47807 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets
by Michael Niewöhner (Code Review) 24 Nov '20

24 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47807 ) Change subject: include/device/pci_ids.h: Add PCI IDs used in Lynxpoint chipsets ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe Gerrit-Change-Number: 47807 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 18:37:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 2: (13 comments) https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/acpi/gpe.asl: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 8: One 1 https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 12: # Send an extra VR mailbox command for the PS4 exit issue : register "SendVrMbxCmd" = "2" Does this apply to your board? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 26: register "SaGv" = "SaGv_Enabled" I'm not sure if this has any effect on Halo https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 34: PchSerialIoPci SkipInit? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 37: # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) : register "PcieClkSrcUsage[8]" = "0x40" : register "PcieClkSrcClkReq[8]" = "8" Put under the PEG device? (01.0) https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 79: Enable Nope https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/gpio.h: PS2: This should be a gpio.c https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/hda_verb.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 25: // Enable DMIC microphone on ALC1220 : 0x02050036, : 0x02042a6a, What does the microphone have to do with beep? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 7: CH0D0/CH0D1/CH1D0/CH1D1. Two of these do not exist https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 19: /* : * For each channel, there are 3 sets of DQ byte mappings, : * where each set has a package 0 and a package 1 value (package 0 : * represents the first 64-bit lpddr4 chip combination, and package 1 : * represents the second 64-bit lpddr4 chip combination). : * The first three sets are for CLK, CMD, and CTL. : * The fsp package actually expects 6 sets, but the last 3 sets are : * not used in CNL, so we only define the three sets that are used : * and let the meminit_lpddr4() routine take care of clearing the : * unused fields for the caller. : */ : .dq_map[DDR_CH0] = { : {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, : //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} : }, : .dq_map[DDR_CH1] = { : {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, : //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} : }, : : /* : * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a : * mapping of a dq bit on the CPU to the bit it's connected to on : * the memory part. The array index represents the dqs bit number : * on the memory part, and the values in the array represent which : * pin on the CPU that DRAM pin connects to. : */ : .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, : .dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7}, Does this apply at all? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 52: DRAM This is wrong. Does this comment actually help? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 57: These will typically be the following : * values for Cannon Lake : { 80, 40, 40, 40, 30 } Why copy this comment? https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 62: /* : * Indicates whether memory is interleaved. : * Set to 1 for an interleaved design, : * set to 0 for non-interleaved design. : */ I think this is pretty obvious. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 24 Nov 2020 18:27:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/northbridge/amd/agesa: fix the device resource assignment
by Mike Banon (Code Review) 24 Nov '20

24 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41431 ) Change subject: src/northbridge/amd/agesa: fix the device resource assignment ...................................................................... src/northbridge/amd/agesa: fix the device resource assignment The chipset code was incorrectly adding memory resources to the domain device after resource allocation occurred. It's not possible to get the correct view of the address space, and it's generally incorrect to not add resources during read_resources(). This change fixes the order by adding resources during read_resources(). This successfully fixes the boot problems of fam15tn A88XM-E but fails to fix a fam16kb AM1I-A. After fam16kb will be fixed, this change should be updated with a fix for fam14 as well. Inspired by CB:41369. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5df6d0150e777cd21f6f9a2fc776f3548da8201d --- M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 2 files changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/41431/1 diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9d41e7a..0194ea8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -666,6 +666,8 @@ u32 reset_memhole = 1; #endif + domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -749,17 +751,18 @@ } add_uma_resource_below_tolm(dev, 7); - +/* for (link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); } } +*/ } static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, }; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cedc7da..0467b27 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -683,6 +683,8 @@ u32 reset_memhole = 1; #endif + domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -768,11 +770,13 @@ add_uma_resource_below_tolm(dev, 7); +/* for (link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); } } +*/ } static const char *domain_acpi_name(const struct device *dev) @@ -784,8 +788,8 @@ } static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/41431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df6d0150e777cd21f6f9a2fc776f3548da8201d Gerrit-Change-Number: 41431 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 24 Nov '20

24 Nov '20

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 18:13:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Drop unused CMOS options
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47179 ) Change subject: mainboard: Drop unused CMOS options ...................................................................... mainboard: Drop unused CMOS options None of these options are handled in coreboot code. Change-Id: If0cb1d716fa0a7da249e72c7c006849371f49835 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/inagua/cmos.layout M src/mainboard/amd/olivehill/cmos.layout M src/mainboard/amd/parmer/cmos.layout M src/mainboard/amd/persimmon/cmos.layout M src/mainboard/amd/south_station/cmos.layout M src/mainboard/amd/thatcher/cmos.layout M src/mainboard/amd/union_station/cmos.layout M src/mainboard/asrock/e350m1/cmos.layout M src/mainboard/asrock/imb-a180/cmos.layout M src/mainboard/asus/a88xm-e/cmos.layout M src/mainboard/asus/f2a85-m/cmos.layout M src/mainboard/bap/ode_e20XX/cmos.layout M src/mainboard/biostar/a68n_5200/cmos.layout M src/mainboard/biostar/am1ml/cmos.layout M src/mainboard/elmex/pcm205400/cmos.layout M src/mainboard/emulation/qemu-i440fx/cmos.default M src/mainboard/emulation/qemu-i440fx/cmos.layout M src/mainboard/emulation/qemu-q35/cmos.default M src/mainboard/emulation/qemu-q35/cmos.layout M src/mainboard/gizmosphere/gizmo/cmos.layout M src/mainboard/gizmosphere/gizmo2/cmos.layout M src/mainboard/hp/abm/cmos.layout M src/mainboard/jetway/nf81-t56n-lf/cmos.layout M src/mainboard/lenovo/g505s/cmos.layout M src/mainboard/lippert/frontrunner-af/cmos.layout M src/mainboard/msi/ms7721/cmos.layout M src/mainboard/pcengines/apu1/cmos.default M src/mainboard/pcengines/apu1/cmos.layout M src/mainboard/pcengines/apu2/cmos.layout 29 files changed, 0 insertions(+), 285 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47179/1 diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 1fb9f0f..6caaeab 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 2 e 3 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,8 +21,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 3 0 Off 3 1 On 3 2 Last @@ -38,10 +30,6 @@ 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout index 173d8c4..ad72d70 100644 --- a/src/mainboard/asus/a88xm-e/cmos.layout +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -5,15 +5,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -#456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -24,8 +18,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency @@ -37,10 +29,6 @@ 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index 6f61f97..f6dd7cf 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -30,12 +30,7 @@ #96 288 r 0 temporary_filler 0 384 r 0 reserved_memory 384 1 e 4 boot_option -386 1 e 1 ECC_memory 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first @@ -44,7 +39,6 @@ 428 4 h 0 boot_index 432 8 h 0 boot_countdown 444 1 e 1 nmi -445 1 e 1 iommu 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -55,8 +49,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice @@ -70,10 +62,6 @@ 7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index d7d5d12..42e0fea 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 r 0 reboot_bits -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.default b/src/mainboard/emulation/qemu-i440fx/cmos.default index 8594b46..57750a2 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.default +++ b/src/mainboard/emulation/qemu-i440fx/cmos.default @@ -1,4 +1,3 @@ boot_option=Fallback power_on_after_fail=Enable debug_level=Debug -ECC_memory=Disable diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index 8963e13..5e5a901 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -10,7 +10,6 @@ 448 1 e 1 power_on_after_fail 452 4 e 6 debug_level -456 1 e 1 ECC_memory # VBOOT 464 128 r 0 vbnv diff --git a/src/mainboard/emulation/qemu-q35/cmos.default b/src/mainboard/emulation/qemu-q35/cmos.default index 8594b46..57750a2 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.default +++ b/src/mainboard/emulation/qemu-q35/cmos.default @@ -1,4 +1,3 @@ boot_option=Fallback power_on_after_fail=Enable debug_level=Debug -ECC_memory=Disable diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index 8963e13..5e5a901 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -10,7 +10,6 @@ 448 1 e 1 power_on_after_fail 452 4 e 6 debug_level -456 1 e 1 ECC_memory # VBOOT 464 128 r 0 vbnv diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index 076ca9d..71bfd07 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -8,16 +8,10 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core #400 8 r 8 reserved for century byte 408 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -28,18 +22,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index d26d6aa..f6031ec 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums diff --git a/src/mainboard/pcengines/apu1/cmos.default b/src/mainboard/pcengines/apu1/cmos.default index 0906d5a..06b0433 100644 --- a/src/mainboard/pcengines/apu1/cmos.default +++ b/src/mainboard/pcengines/apu1/cmos.default @@ -1,3 +1,2 @@ boot_option=Fallback -multi_core=Enable debug_level=Debug diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index dd3cd91..e36dd6b 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -5,7 +5,6 @@ 384 4 r 0 reboot_bits # leave 3 bits to make checksummed area start byte-aligned 392 1 e 2 boot_option -393 1 e 1 multi_core 400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum @@ -13,9 +12,6 @@ enumerations #<config-id> <value> <label> -## for multi_core -1 0 Enable -1 1 Disable ## for boot_option 2 0 Fallback 2 1 Normal diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index d7d5d12..42e0fea 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -8,15 +8,9 @@ 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 r 0 reboot_bits -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -27,18 +21,12 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 5 Notice 6 6 Info 6 7 Debug 6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz checksums -- To view, visit https://review.coreboot.org/c/coreboot/+/47179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0cb1d716fa0a7da249e72c7c006849371f49835 Gerrit-Change-Number: 47179 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mainboard: Drop unused `lpt` option
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47177 ) Change subject: mainboard: Drop unused `lpt` option ...................................................................... mainboard: Drop unused `lpt` option It is only used in mainboard-specific code, which not all boards have. Change-Id: If70d053501f02ffe210d50ea6e29eb76c264466d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbook21/cmos.layout M src/mainboard/lenovo/t60/cmos.layout M src/mainboard/lenovo/x60/cmos.layout 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47177/1 diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 5d3d074..55246f1 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -28,7 +28,6 @@ 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 2af6365..11c2178 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -28,7 +28,6 @@ 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt # coreboot config options: cpu diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 61ab465..b6cbe3c 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -28,7 +28,6 @@ 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt # coreboot config options: cpu -- To view, visit https://review.coreboot.org/c/coreboot/+/47177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If70d053501f02ffe210d50ea6e29eb76c264466d Gerrit-Change-Number: 47177 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/**/cmos.layout: Drop copy-pasted `volume` entries
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47150 ) Change subject: mb/**/cmos.layout: Drop copy-pasted `volume` entries ...................................................................... mb/**/cmos.layout: Drop copy-pasted `volume` entries This option only applies to boards using the Lenovo H8 EC code. Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/cmos.layout M src/mainboard/hp/snb_ivb_laptops/cmos.layout M src/mainboard/sapphire/pureplatinumh61/cmos.layout 3 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47150/1 diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index 6a23ab6..7f153a0 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -18,7 +18,6 @@ # coreboot config options: cpu # coreboot config options: northbridge #432 5 e 11 gfx_uma_size -#440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 31889ad..f7a9390 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -28,8 +28,6 @@ # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -440 8 h 0 volume - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 8a45f42..979c8e2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -15,8 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -400 8 h 0 volume - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -- To view, visit https://review.coreboot.org/c/coreboot/+/47150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415 Gerrit-Change-Number: 47150 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNB
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47149 ) Change subject: mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNB ...................................................................... mb/**/cmos.layout: Drop copy-pasted SNB entries on non-SNB Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge boards ended up with these entries because of copy-paste programming. Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/cmos.layout M src/mainboard/google/auron/cmos.layout M src/mainboard/google/beltino/cmos.layout M src/mainboard/google/cyan/cmos.layout M src/mainboard/google/glados/cmos.layout M src/mainboard/google/jecht/cmos.layout M src/mainboard/google/rambi/cmos.layout M src/mainboard/google/slippy/cmos.layout M src/mainboard/intel/kblrvp/cmos.layout M src/mainboard/intel/kunimitsu/cmos.layout M src/mainboard/intel/strago/cmos.layout M src/mainboard/intel/wtm2/cmos.layout 12 files changed, 0 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47149/1 diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 283aa1e..77ff743 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -26,10 +26,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 283aa1e..77ff743 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -26,10 +26,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 283aa1e..77ff743 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -26,10 +26,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 283aa1e..77ff743 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -26,10 +26,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 929f7aa..80a4d21 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -28,10 +28,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 283aa1e..77ff743 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -26,10 +26,6 @@ #Used by ChromeOS: 416 128 r 0 vbnv -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - # coreboot config options: check sums 984 16 h 0 check_sum -- To view, visit https://review.coreboot.org/c/coreboot/+/47149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a Gerrit-Change-Number: 47149 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in chrome-ec[master]: util/ec_uartd: build as part of host-utils, not build-utils
by Patrick Georgi (Code Review) 24 Nov '20

24 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/chrome-ec/+/47955 ) Change subject: util/ec_uartd: build as part of host-utils, not build-utils ...................................................................... util/ec_uartd: build as part of host-utils, not build-utils It's not needed for the build, so don't draw in its dependencies Change-Id: I56d97d776a8c2aaf47aa39802cc9831c4f3416a7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/build.mk 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/chrome-ec refs/changes/55/47955/1 diff --git a/util/build.mk b/util/build.mk index 37f01e0..1e795c1 100644 --- a/util/build.mk +++ b/util/build.mk @@ -7,8 +7,7 @@ # host-util-bin=ectool lbplay stm32mon ec_sb_firmware_update lbcc \ - ec_parse_panicinfo cbi-util iteflash -build-util-bin=ec_uartd + ec_parse_panicinfo cbi-util iteflash ec_uartd build-util-art+=util/export_taskinfo.so ifeq ($(CHIP),npcx) build-util-bin+=ecst -- To view, visit https://review.coreboot.org/c/chrome-ec/+/47955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: chrome-ec Gerrit-Branch: master Gerrit-Change-Id: I56d97d776a8c2aaf47aa39802cc9831c4f3416a7 Gerrit-Change-Number: 47955 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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