coreboot-gerrit November 2020

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Change in coreboot[master]: drivers/intel/i210: Define MAC_ADDR_LEN
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Hello build bot (Jenkins), Mario Scheithauer, Uwe Poeche, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47404 to look at the new patch set (#4). Change subject: drivers/intel/i210: Define MAC_ADDR_LEN ...................................................................... drivers/intel/i210: Define MAC_ADDR_LEN Define and use the MAC_ADDR_LEN macro in place of the `6` magic value. Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/i210/i210.h M src/mainboard/siemens/mc_apl1/mainboard.c 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47404/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Gerrit-Change-Number: 47404 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Update UART0 GPIO as per latest schematics
by Subrata Banik (Code Review) 24 Nov '20

24 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47847 ) Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics ...................................................................... soc/intel/alderlake: Update UART0 GPIO as per latest schematics UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/uart.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47847/1 diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index cdbf8ec..a3bdc4a 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -21,8 +21,8 @@ { .console_index = 0, .gpios = { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ }, }, { -- To view, visit https://review.coreboot.org/c/coreboot/+/47847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Gerrit-Change-Number: 47847 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO
by Arthur Heymans (Code Review) 24 Nov '20

24 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47764 ) Change subject: soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO ...................................................................... soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO TCO is configured by FSP. This mostly makes it possible to report TCO events in SMM if enabled. Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/smbus.h M src/soc/intel/xeon_sp/pmc.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h 5 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47764/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 37c74dc..26ba0a6 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + select SOC_INTEL_COMMON_BLOCK_TCO select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 33e257c..f052b3f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -101,10 +101,12 @@ #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define HPET_BUS_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h new file mode 100644 index 0000000..00aae2c --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* SMBus I/O bits. */ +#define SMBUS_SLAVE_ADDR 0x24 + +#endif diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index a418ae5..b4f86db 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -193,3 +193,25 @@ *smi_arr = ARRAY_SIZE(smi_sts_bits); return smi_sts_bits; } + +const char *const *soc_tco_sts_array(size_t *tco_arr) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "OS_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "CPUSCI", + [10] = "CPUSMI", + [12] = "CPUSERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [20] = "SMLINK_SLV" + }; + + *tco_arr = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 429278c..d662f5b0 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -140,10 +140,12 @@ #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) #define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define CBDMA_DEV_NUM 0x04 -- To view, visit https://review.coreboot.org/c/coreboot/+/47764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467 Gerrit-Change-Number: 47764 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Hook up the PMC driver
by Arthur Heymans (Code Review) 24 Nov '20

24 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47763 ) Change subject: soc/intel/xeon_sp: Hook up the PMC driver ...................................................................... soc/intel/xeon_sp: Hook up the PMC driver The soc code was already there but it was never linked. Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/47763/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3d3e803..37c74dc 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -49,6 +49,8 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS @@ -56,6 +58,8 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select NO_SMM + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select REG_SCRIPT config MAINBOARD_USES_FSP2_0 bool -- To view, visit https://review.coreboot.org/c/coreboot/+/47763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e Gerrit-Change-Number: 47763 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP]: SPI, DMI changes to support extended BIOS region
by Srinidhi N Kaushik (Code Review) 24 Nov '20

24 Nov '20

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47907 ) Change subject: WIP]: SPI, DMI changes to support extended BIOS region ...................................................................... Patch Set 7: @Furquan, Added the initial changes, this is just a place holder CL. If you check it once I can update the relation chain. I didnt want to mess up the chain hence pushed it as WIP here. I had some questions on couple of things, 1. During GPMR programming in dmi.c I think I am missing the check PCR base address being configured. 2. The MTRR programming can be better in terms of reusing the same code block. Also I will split this into 3 CLs as per the document. -- To view, visit https://review.coreboot.org/c/coreboot/+/47907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17b0f8a21b757946168c8660aef2852c96165378 Gerrit-Change-Number: 47907 Gerrit-PatchSet: 7 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 11:58:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47402 ) Change subject: [RFC] mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev() ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47402/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47402/3//COMMIT_MSG@12 PS3, Line 12: TODO: Define a Kconfig symbol to control this? Since this is baseboard specific there is no need for a separated Kconfig switch. We can distinguish on the variant switch. So you can remove this TODO here. -- To view, visit https://review.coreboot.org/c/coreboot/+/47402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Gerrit-Change-Number: 47402 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 11:52:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

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Change in coreboot[master]: mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logic
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47405 ) Change subject: mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logic ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311 Gerrit-Change-Number: 47405 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 24 Nov 2020 09:43:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl1/mainboard.c: Refactor loop body
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47403 ) Change subject: mb/siemens/mc_apl1/mainboard.c: Refactor loop body ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Gerrit-Change-Number: 47403 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Comment-Date: Tue, 24 Nov 2020 09:42:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: fw_config: Add setting for new sd readers
by Zhuohao Lee (Code Review) 24 Nov '20

24 Nov '20

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47856 ) Change subject: mb/google/volteer: fw_config: Add setting for new sd readers ...................................................................... mb/google/volteer: fw_config: Add setting for new sd readers This patch adds three settings for the new sd readers. The new assigned values are: 1. RTS5227S: 3 2. L9750: 4 3. SD_OZ711LV2LN: 5 BUG=b:173676531 BRANCH=volteer TEST=abuild -t google/volteer Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/47856/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 1590415..7964885 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -37,6 +37,9 @@ option SD_ABSENT 0 option SD_GL9755S 1 option SD_RTS5261 2 + option SD_RTS5227S 3 + option SD_L9750 4 + option SD_OZ711LV2LN 5 end field KB_LAYOUT 20 21 option KB_LAYOUT_DEFAULT 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/47856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327 Gerrit-Change-Number: 47856 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020