coreboot-gerrit November 2020

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Change in coreboot[master]: please ignore: test commit for automatic addition of reviewers
by Patrick Georgi (Code Review) 24 Nov '20

24 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47954 ) Change subject: please ignore: test commit for automatic addition of reviewers ...................................................................... please ignore: test commit for automatic addition of reviewers Change-Id: Ie2637b33741a752c13d47defc712d8e4bb0bc2d0 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/lint/lint-008-kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/47954/1 diff --git a/util/lint/lint-008-kconfig b/util/lint/lint-008-kconfig index 31aba55..fca969c 100755 --- a/util/lint/lint-008-kconfig +++ b/util/lint/lint-008-kconfig @@ -1,4 +1,5 @@ #!/bin/sh + # # SPDX-License-Identifier: GPL-2.0-only -- To view, visit https://review.coreboot.org/c/coreboot/+/47954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2637b33741a752c13d47defc712d8e4bb0bc2d0 Gerrit-Change-Number: 47954 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/var/voxel: Update DPTF parameters
by Sheng-Liang Pan (Code Review) 24 Nov '20

24 Nov '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47858 ) Change subject: UPSTREAM: mb/google/volteer/var/voxel: Update DPTF parameters ...................................................................... UPSTREAM: mb/google/volteer/var/voxel: Update DPTF parameters update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47858/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index dd29553..9c4aa47 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -23,22 +23,22 @@ ## Active Policy register "policies.active" = "{ [0] = {.target = DPTF_CPU, - .thresholds = {TEMP_PCT(94, 100),}}, + .thresholds = {TEMP_PCT(98, 100),}}, [1] = {.target = DPTF_TEMP_SENSOR_2, .thresholds = {TEMP_PCT(64, 100), TEMP_PCT(60, 90), TEMP_PCT(56, 80), TEMP_PCT(52, 70), - TEMP_PCT(48, 60), - TEMP_PCT(44, 50), - TEMP_PCT(40, 40),}}}" + TEMP_PCT(47, 60), + TEMP_PCT(42, 50), + TEMP_PCT(35, 40),}}}" ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 52, 6000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" ## Critical Policy @@ -58,7 +58,7 @@ .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, - .pl2 = {.min_power = 15000, + .pl2 = {.min_power = 51000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/47858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Gerrit-Change-Number: 47858 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Create galtic variant
by Paul Fagerburg (Code Review) 24 Nov '20

24 Nov '20

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47900 ) Change subject: mb/google/dedede: Create galtic variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Gerrit-Change-Number: 47900 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)google.com> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 16:18:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/crossgcc: Retry package downloads on failure
by Martin Roth (Code Review) 24 Nov '20

24 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47338 ) Change subject: util/crossgcc: Retry package downloads on failure ...................................................................... util/crossgcc: Retry package downloads on failure For whatever reason, I've had buildgcc fail to download packages a number of times. Adding 2 additional retries before failing helps with that problem. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I060eaa5a0da955436169e2199c1c62044dcfd5ea --- M util/crossgcc/buildgcc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47338/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d5cca6c..196e265 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1057,7 +1057,7 @@ download_showing_percentage() { url=$1 printf "... ${red} 0%%" - wget "$url" 2>&1 | while read -r line; do + wget --tries=3 "$url" 2>&1 | while read -r line; do echo "$line" | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' done printf "${NC}... " @@ -1066,7 +1066,7 @@ download_showing_percentage() { url=$1 echo - curl -#OL "$url" + curl --progress-bar --location --retry 3 "$url" } fi -- To view, visit https://review.coreboot.org/c/coreboot/+/47338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I060eaa5a0da955436169e2199c1c62044dcfd5ea Gerrit-Change-Number: 47338 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/i210: Define MAC_ADDR_LEN
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47404 ) Change subject: drivers/intel/i210: Define MAC_ADDR_LEN ...................................................................... Patch Set 4: > Patch Set 4: Code-Review+2 > > Seems even to be binary-transparent according to the siemens-bot Yeah, I didn't check this but it makes lots of sense. After all, the compiler ends up seeing the same code after macro expansion 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/47404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Gerrit-Change-Number: 47404 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 12:50:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/i210: Define MAC_ADDR_LEN
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47404 ) Change subject: drivers/intel/i210: Define MAC_ADDR_LEN ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47404/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47404/1//COMMIT_MSG@7 PS1, Line 7: MAC_ADDR_LEN > Sorry, I only read the comment after +2. Yes, the define should be in i210.h. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Gerrit-Change-Number: 47404 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 12:49:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Enable SMI handler
by Arthur Heymans (Code Review) 24 Nov '20

24 Nov '20

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46231 ) Change subject: soc/intel/xeon_sp: Enable SMI handler ...................................................................... soc/intel/xeon_sp: Enable SMI handler SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura(a)fb.com> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/nvs.h A src/soc/intel/xeon_sp/include/soc/smmrelocate.h M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc M src/soc/intel/xeon_sp/skx/cpu.c A src/soc/intel/xeon_sp/smihandler.c A src/soc/intel/xeon_sp/smmrelocate.c 12 files changed, 205 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2b1034b..2028a5e 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -52,6 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_TCO select TSC_MONOTONIC_TIMER select UDELAY_TSC @@ -59,8 +60,11 @@ select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR - select NO_SMM + select CPU_INTEL_COMMON_SMM select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SMM_TSEG + select HAVE_SMI_HANDLER + select X86_SMM_LOADER_VERSION2 select REG_SCRIPT config MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 2e50e64..cfda7d5 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -12,6 +12,8 @@ ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c pmc.c postcar-y += spi.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 28e7b83..369d474 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -78,6 +78,10 @@ documentation says this needs to be at least 128KiB, but practice show this needs to be 256KiB or more. +config IED_REGION_SIZE + hex + default 0x400000 + config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e..a5c6848 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,6 +5,7 @@ subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/smm subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d1bcbd7..2f4ab06 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -7,7 +7,9 @@ #include <console/debug.h> #include <cpu/cpu.h> #include <cpu/intel/common/common.h> +#include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> @@ -17,6 +19,7 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/soc_util.h> +#include <soc/smmrelocate.h> #include <soc/util.h> #include "chip.h" @@ -172,16 +175,16 @@ /* Set Max Ratio */ set_max_turbo_freq(); - /* - * TODO: Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - if (0) global_smi_enable(); + if (CONFIG(HAVE_SMI_HANDLER)) + global_smi_enable(); } static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_thread_count, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_initialize, + .relocation_handler = smm_relocation_handler, .get_microcode_info = get_microcode_info, .post_mp_init = post_mp_init, }; diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index becdd76..100a442 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -8,10 +8,13 @@ /* TODO - this requires xeon sp, server board support */ /* NOTE: We do not use intelblocks/nvs.h since it includes mostly client specific attributes */ + +/* TODO: This is not aligned with the ACPI asl code */ struct __packed global_nvs { uint8_t pcnt; /* 0x00 - Processor Count */ uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t rsvd3[251]; + uint8_t uior; + uint8_t rsvd3[250]; }; #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h new file mode 100644 index 0000000..314ebd4 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_SMMRELOCATE_H_ +#define _SOC_SMMRELOCATE_H_ + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + +#endif diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 2e0778e..08242b1 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -59,4 +59,8 @@ hex default 0x80000 +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index f042d36..6ee610e 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -8,7 +8,7 @@ subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/x86/cache -subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm +subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../../cpu/x86/smm postcar-y += soc_util.c diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 874bcfd..d36f11b 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -10,9 +10,13 @@ #include <soc/msr.h> #include <soc/cpu.h> #include <soc/soc_util.h> +#include <soc/smmrelocate.h> #include <soc/util.h> #include <assert.h> #include "chip.h" +#include <cpu/intel/smm_reloc.h> +#include <cpu/intel/em64t101_save_state.h> + static const config_t *chip_config = NULL; @@ -197,11 +201,8 @@ /* Set Max Ratio */ set_max_turbo_freq(); - /* - * TODO: Now that all APs have been relocated as well as the BSP let SMIs - * start flowing. - */ - if (0) global_smi_enable(); + if (CONFIG(HAVE_SMI_HANDLER)) + global_smi_enable(); } /* @@ -214,12 +215,9 @@ static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_platform_thread_count, - //.get_smm_info = get_smm_info, /* TODO */ - .get_smm_info = NULL, - //.pre_mp_smm_init = southcluster_smm_clear_state, /* TODO */ - .pre_mp_smm_init = NULL, - //.relocation_handler = relocation_handler, /* TODO */ - .relocation_handler = NULL, + .get_smm_info = get_smm_info, + .pre_mp_smm_init = smm_initialize, + .relocation_handler = smm_relocation_handler, .post_mp_init = post_mp_init, }; diff --git a/src/soc/intel/xeon_sp/smihandler.c b/src/soc/intel/xeon_sp/smihandler.c new file mode 100644 index 0000000..db3b429 --- /dev/null +++ b/src/soc/intel/xeon_sp/smihandler.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/smihandler.h> +#include <soc/pm.h> +#include <cpu/x86/smm.h> + +/* This is needed by common SMM code */ +const smi_handler_t southbridge_smi[SMI_STS_BITS] = { + [APM_STS_BIT] = smihandler_southbridge_apmc, + [PM1_STS_BIT] = smihandler_southbridge_pm1, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) + [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif +}; diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c new file mode 100644 index 0000000..a71a740 --- /dev/null +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <assert.h> +#include <string.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/em64t101_save_state.h> +#include <cpu/intel/smm_reloc.h> +#include <console/console.h> +#include <smp/node.h> +#include <soc/msr.h> +#include <soc/smmrelocate.h> + +static void fill_in_relocation_params(struct smm_relocation_params *params) +{ + uintptr_t tseg_base; + size_t tseg_size; + + smm_region(&tseg_base, &tseg_size); + + if (!IS_ALIGNED(tseg_base, tseg_size)) { + /* + * Note SMRR2 is supported which might support base/size combinations. + * For now it looks like FSP-M always uses aligned base/size, so let's + * not care about that. + */ + printk(BIOS_WARNING, + "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n"); + return; + } + + /* SMRR has 32-bits of valid address aligned to 4KiB. */ + if (!IS_ALIGNED(tseg_size, 4 * KiB)) { + printk(BIOS_WARNING, + "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n"); + return; + } + + smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); + + params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK; + params->smrr_base.hi = 0; + params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID; + params->smrr_mask.hi = 0; +} + +static void setup_ied_area(struct smm_relocation_params *params) +{ + char *ied_base; + + const struct ied_header ied = { + .signature = "INTEL RSVD", + .size = params->ied_size, + .reserved = {0}, + }; + + ied_base = (void *)params->ied_base; + + printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base); + printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size); + + /* Place IED header at IEDBASE. */ + memcpy(ied_base, &ied, sizeof(ied)); + + assert(params->ied_size > 1 * MiB + 32 * KiB); + + /* Zero out 32KiB at IEDBASE + 1MiB */ + memset(ied_base + 1 * MiB, 0, 32 * KiB); +} + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size) +{ + fill_in_relocation_params(&smm_reloc_params); + + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + + if (smm_reloc_params.ied_size) + setup_ied_area(&smm_reloc_params); + + *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); +} + +static void update_save_state(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) +{ + u32 smbase; + u32 iedbase; + int apic_id; + em64t101_smm_state_save_area_t *save_state; + /* + * The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. + */ + smbase = staggered_smbase; + iedbase = relo_params->ied_base; + + apic_id = cpuid_ebx(1) >> 24; + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", + smbase, iedbase, apic_id); + + save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + + save_state->smbase = smbase; + save_state->iedbase = iedbase; +} + +/* + * The relocation work is actually performed in SMM context, but the code + * resides in the ramstage module. This occurs by trampolining from the default + * SMRAM entry point to here. + */ +void smm_relocation_handler(int cpu, uintptr_t curr_smbase, + uintptr_t staggered_smbase) +{ + msr_t mtrr_cap; + struct smm_relocation_params *relo_params = &smm_reloc_params; + + printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu); + + /* Make appropriate changes to the save state map. */ + update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + + /* Write SMRR MSRs based on indicated support. */ + mtrr_cap = rdmsr(MTRR_CAP_MSR); + if (mtrr_cap.lo & SMRR_SUPPORTED) + write_smrr(relo_params); +} + +void smm_initialize(void) +{ + /* Clear the SMM state in the southbridge. */ + smm_southbridge_clear_state(); + /* Run the relocation handler for on the BSP . */ + smm_initiate_relocation(); +} + +void smm_relocate(void) +{ + /* Save states via MSR does not seem to be supported on CPX */ + if (!boot_cpu()) + smm_initiate_relocation(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Gerrit-Change-Number: 46231 Gerrit-PatchSet: 31 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/i210: Define MAC_ADDR_LEN
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47404 ) Change subject: drivers/intel/i210: Define MAC_ADDR_LEN ...................................................................... Patch Set 4: Code-Review+2 Seems even to be binary-transparent according to the siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/47404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Gerrit-Change-Number: 47404 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 12:42:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/i210: Define MAC_ADDR_LEN
by Werner Zeh (Code Review) 24 Nov '20

24 Nov '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47404 ) Change subject: drivers/intel/i210: Define MAC_ADDR_LEN ...................................................................... Patch Set 4: start siemens-bot -- To view, visit https://review.coreboot.org/c/coreboot/+/47404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Gerrit-Change-Number: 47404 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 24 Nov 2020 12:37:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev()
by Angel Pons (Code Review) 24 Nov '20

24 Nov '20

Hello build bot (Jenkins), Mario Scheithauer, siemens-bot, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47402 to look at the new patch set (#4). Change subject: mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev() ...................................................................... mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev() There's one copy of this function for all variants except mc_apl4. Move one copy into common mainboard.c and exit early if running on mc_apl4. Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 6 files changed, 32 insertions(+), 141 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47402/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Gerrit-Change-Number: 47402 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2020