coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNC
by Chen Wisley (Code Review) 25 Nov '20

25 Nov '20

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47855 to review the following change. Change subject: mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNC ...................................................................... mb/google/volteer/var/elemi: Add H5ANAG6NCJR-XNC Add H5ANAG6NCJR-XNC. BUG=b:165461530 BRANCH=volteer TEST=emerge-volteer coreboot Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 --- M src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc M src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47855/1 diff --git a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc index 2685fcd..0a9e3f9 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/memory/Makefile.inc @@ -5,3 +5,4 @@ SPD_SOURCES += ddr4-spd-2.hex # ID = 0(0b0000) Parts = H5ANAG6NCMR-XNC SPD_SOURCES += ddr4-spd-7.hex # ID = 1(0b0001) Parts = MT40A1G16KD-062E:E, K4AAG165WA-BCWE SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = H5AN8G6NDJR-XNC, MT40A512M16TB-062E:J, K4A8G165WC-BCWE +SPD_SOURCES += ddr4-spd-9.hex # ID = 3(0b0011) Parts = H5ANAG6NCJR-XNC diff --git a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt index c892d9b..e85149b 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/dram_id.generated.txt @@ -5,3 +5,4 @@ H5AN8G6NDJR-XNC 2 (0010) MT40A512M16TB-062E:J 2 (0010) K4A8G165WC-BCWE 2 (0010) +H5ANAG6NCJR-XNC 3 (0011) diff --git a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt index 939d85f..b110e92 100644 --- a/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/elemi/memory/mem_list_variant.txt @@ -4,3 +4,4 @@ H5AN8G6NDJR-XNC MT40A512M16TB-062E:J K4A8G165WC-BCWE +H5ANAG6NCJR-XNC -- To view, visit https://review.coreboot.org/c/coreboot/+/47855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0 Gerrit-Change-Number: 47855 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/amd: Deduplicate nb_common.h
by Angel Pons (Code Review) 25 Nov '20

25 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47408 ) Change subject: nb/amd: Deduplicate nb_common.h ...................................................................... nb/amd: Deduplicate nb_common.h Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/pcengines/apu2/mptable.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c D src/northbridge/amd/agesa/nb_common.h R src/northbridge/amd/nb_common.h M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/00730F01/state_machine.c 10 files changed, 8 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47408/1 diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c index b52c8cc..a24863f 100644 --- a/src/mainboard/pcengines/apu2/mptable.c +++ b/src/mainboard/pcengines/apu2/mptable.c @@ -3,7 +3,7 @@ #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <stdint.h> -#include <northbridge/amd/pi/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <southbridge/amd/common/amd_pci_util.h> static void *smp_write_config_table(void *v) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7c37ff8..020c9c6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -13,7 +13,7 @@ #include <cpu/cpu.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -#include <northbridge/amd/agesa/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h> diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2d5234d..e345b50 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -18,7 +18,7 @@ #include <Porting.h> #include <Options.h> #include <Topology.h> -#include <northbridge/amd/agesa/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index addd40f..b600bc9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -18,7 +18,7 @@ #include <AGESA.h> #include <Options.h> #include <Topology.h> -#include <northbridge/amd/agesa/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h deleted file mode 100644 index 66fbf92..0000000 --- a/src/northbridge/amd/agesa/nb_common.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __AMD_NB_COMMON_H__ -#define __AMD_NB_COMMON_H__ - -#define HT_IO_HOST_ALIGN 4096 -#define HT_MEM_HOST_ALIGN (1024 * 1024) - -#define DEV_CDB 0x18 - -#endif diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/nb_common.h similarity index 100% rename from src/northbridge/amd/pi/nb_common.h rename to src/northbridge/amd/nb_common.h diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 110dc84..5242cd0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -17,7 +17,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <acpi/acpigen.h> -#include <northbridge/amd/pi/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS MAX_NODES diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 86c815c..7820c60 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -17,7 +17,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <acpi/acpigen.h> -#include <northbridge/amd/pi/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #define MAX_NODE_NUMS MAX_NODES diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 41554b8..2019fae 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -21,7 +21,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <acpi/acpigen.h> -#include <northbridge/amd/pi/nb_common.h> +#include <northbridge/amd/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <southbridge/amd/pi/hudson/pci_devs.h> diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index af1198a..ba34dab 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -8,7 +8,7 @@ #include <device/device.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <northbridge/amd/pi/nb_common.h> +#include <northbridge/amd/nb_common.h> void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Gerrit-Change-Number: 47408 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: device: Drop unused HyperTransport code
by Angel Pons (Code Review) 25 Nov '20

25 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47407 ) Change subject: device: Drop unused HyperTransport code ...................................................................... device: Drop unused HyperTransport code Only two definitions are actually used somewhere, the rest is unused. Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/Kconfig M src/device/Makefile.inc D src/device/hypertransport.c M src/device/pci_device.c D src/include/device/hypertransport.h D src/include/device/hypertransport_def.h M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/agesa/nb_common.h M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/nb_common.h 14 files changed, 6 insertions(+), 571 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47407/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 777f3f5..e716f5a 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -491,18 +491,6 @@ bool default !NO_MMCONF_SUPPORT -config HYPERTRANSPORT_PLUGIN_SUPPORT - bool - default n - -config HT_CHAIN_UNITID_BASE - int - default 0 - -config HT_CHAIN_END_UNITID_BASE - int - default 0 - config PCIX_PLUGIN_SUPPORT bool default y diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 2fae44a..f5e2c68 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -35,7 +35,6 @@ ramstage-y += pci_ops.c smm-y += pci_ops.c -ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c deleted file mode 100644 index 068c489..0000000 --- a/src/device/hypertransport.c +++ /dev/null @@ -1,499 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <device/hypertransport.h> - -struct ht_link { - struct device *dev; - unsigned int pos; - unsigned char ctrl_off, config_off, freq_off, freq_cap_off; -}; - -static struct device *ht_scan_get_devs(struct device **old_devices) -{ - struct device *first, *last; - - first = *old_devices; - last = first; - - /* - * Extract the chain of devices to (first through last) for the next - * hypertransport device. - */ - while (last && last->sibling && - (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) - { - last = last->sibling; - } - - if (first) { - struct device *child; - - /* Unlink the chain from the list of old devices. */ - *old_devices = last->sibling; - last->sibling = 0; - - /* Now add the device to the list of devices on the bus. */ - /* Find the last child of our parent. */ - for (child = first->bus->children; child && child->sibling;) - child = child->sibling; - - /* Place the chain on the list of children of their parent. */ - if (child) - child->sibling = first; - else - first->bus->children = first; - } - return first; -} - -static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos) -{ - struct ht_link cur[1]; - int linkb_to_host; - - /* Set the hypertransport link width and frequency. */ - - /* - * See which side of the device our previous write to set the unitid - * came from. - */ - cur->dev = dev; - cur->pos = pos; - linkb_to_host = - (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1; - - if (!linkb_to_host) { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } else { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } - - /* - * Remember the current link as the previous link, but look at the - * other offsets. - */ - prev->dev = cur->dev; - prev->pos = cur->pos; - if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; - } else { - prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; - prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0; - prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; - } - - return 0; -} - -static unsigned int ht_lookup_slave_capability(struct device *dev) -{ - unsigned int pos; - - pos = 0; - do { - pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos); - if (pos) { - u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - printk(BIOS_SPEW, "flags: 0x%04x\n", flags); - if ((flags >> 13) == 0) { - /* Entry is a slave secondary, success... */ - break; - } - } - } while (pos); - - return pos; -} - -static void ht_collapse_early_enumeration(struct bus *bus, - unsigned int offset_unitid) -{ - unsigned int devfn; - struct ht_link prev; - u16 ctrl; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); - - /* Is this the end of the hypertransport chain? */ - if (ctrl & (1 << 6)) - return; - - /* Has the link failed? */ - if (ctrl & (1 << 4)) { - /* - * Either the link has failed, or we have a CRC error. - * Sometimes this can happen due to link retrain, so - * lets knock it down and see if its transient. - */ - ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */ - pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, - ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "Hypertransport link\n"); - return; - } - } - } while ((ctrl & (1 << 5)) == 0); - - /* Actually, only for one HT device HT chain, and unitid is 0. */ -#if !CONFIG_HT_CHAIN_UNITID_BASE - if (offset_unitid) - return; -#endif - - /* Check if is already collapsed. */ - if ((!offset_unitid) || (offset_unitid - && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) - && (CONFIG_HT_CHAIN_END_UNITID_BASE - < CONFIG_HT_CHAIN_UNITID_BASE))))) { - - struct device dummy; - u32 id; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = PCI_DEVFN(0, 0); - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if (!((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000))) { - return; - } - } - - /* Spin through the devices and collapse any early HT enumeration. */ - for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) { - struct device dummy; - u32 id; - unsigned int pos, flags; - - dummy.bus = bus; - dummy.path.type = DEVICE_PATH_PCI; - dummy.path.pci.devfn = devfn; - - id = pci_read_config32(&dummy, PCI_VENDOR_ID); - if ((id == 0xffffffff) || (id == 0x00000000) - || (id == 0x0000ffff) || (id == 0xffff0000)) { - continue; - } - - dummy.vendor = id & 0xffff; - dummy.device = (id >> 16) & 0xffff; - dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE); - - pos = ht_lookup_slave_capability(&dummy); - if (!pos) - continue; - - /* Clear the unitid. */ - flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); - printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); - } -} - -static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, - unsigned int *ht_unitid_base, - unsigned int offset_unitid) -{ - /* - * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this - * function, because of end_of_chain check. Also, we need it to - * optimize link. - */ - unsigned int next_unitid, last_unitid, min_unitid, max_unitid; - struct device *old_devices, *dev, *func, *last_func = NULL; - struct ht_link prev; - int ht_dev_num = 0; - - printk(BIOS_SPEW, "%s for bus %02x\n", __func__, bus->secondary); - - min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - /* - * Let's record the device of last HT device, so we can set the unitid - * to CONFIG_HT_CHAIN_END_UNITID_BASE. - */ - unsigned int real_last_unitid = 0, end_used = 0; - u8 real_last_pos = 0; - struct device *real_last_dev = NULL; -#endif - - /* Restore the hypertransport chain to it's uninitialized state. */ - ht_collapse_early_enumeration(bus, offset_unitid); - - /* See which static device nodes I have. */ - old_devices = bus->children; - bus->children = 0; - - /* Initialize the hypertransport enumeration state. */ - prev.dev = bus->dev; - prev.pos = bus->cap; - - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; - prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; - prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP; - - /* If present, assign unitid to a hypertransport chain. */ - max_unitid = next_unitid = min_unitid; - do { - u8 pos; - u16 flags, ctrl; - unsigned int count, static_count; - - last_unitid = next_unitid; - - /* Wait until the link initialization is complete. */ - do { - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - - /* End of chain? */ - if (ctrl & (1 << 6)) - goto end_of_chain; - - if (ctrl & ((1 << 4) | (1 << 8))) { - /* - * Either the link has failed, or we have a CRC - * error. Sometimes this can happen due to link - * retrain, so lets knock it down and see if - * it's transient. - */ - ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC - pci_write_config16(prev.dev, - prev.pos + prev.ctrl_off, ctrl); - ctrl = pci_read_config16(prev.dev, - prev.pos + prev.ctrl_off); - if (ctrl & ((1 << 4) | (1 << 8))) { - printk(BIOS_ALERT, "Detected error on " - "hypertransport link\n"); - goto end_of_chain; - } - } - } while ((ctrl & (1 << 5)) == 0); - - /* Get and setup the device_structure. */ - dev = ht_scan_get_devs(&old_devices); - - /* See if a device is present and setup the device structure. */ - dev = pci_probe_dev(dev, bus, 0); - if (!dev || !dev->enabled) - break; - - /* Find the hypertransport link capability. */ - pos = ht_lookup_slave_capability(dev); - if (pos == 0) { - printk(BIOS_ERR, "%s Hypertransport link capability " - "not found", dev_path(dev)); - break; - } - - /* Update the unitid of the current device. */ - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); - - /* - * If the device has a unitid set and is at devfn 0 we are - * done. This can happen with shadow hypertransport devices, - * or if we have reached the bottom of a HT device chain. - */ - if (flags & 0x1f) - break; - - flags &= ~0x1f; /* Mask out base Unit ID. */ - - count = (flags >> 5) & 0x1f; /* Het unit count. */ - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */ - if (next_unitid > (max_devfn >> 3)) { - if (!end_used) { - next_unitid = - CONFIG_HT_CHAIN_END_UNITID_BASE; - end_used = 1; - } else { - goto end_of_chain; - } - } - } -#endif - - flags |= next_unitid & 0x1f; - pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags); - - /* Update the unitid in the device structure. */ - static_count = 1; - for (func = dev; func; func = func->sibling) { - func->path.pci.devfn += (next_unitid << 3); - static_count = (func->path.pci.devfn >> 3) - - (dev->path.pci.devfn >> 3) + 1; - last_func = func; - } - - /* Compute the number of unitids consumed. */ - printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", - dev_path(dev), count, static_count); - if (count < static_count) - count = static_count; - - /* Update the unitid of the next device. */ - ht_unitid_base[ht_dev_num] = next_unitid; - ht_dev_num++; - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid) { - real_last_pos = pos; - real_last_unitid = next_unitid; - real_last_dev = dev; - } -#endif - next_unitid += count; - if (next_unitid > max_unitid) - max_unitid = next_unitid; - - /* Setup the hypertransport link. */ - bus->reset_needed |= ht_setup_link(&prev, dev, pos); - - printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", - dev_path(dev), dev->vendor, dev->device, - (dev->enabled? "enabled" : "disabled"), next_unitid); - - } while (last_unitid != next_unitid); - -end_of_chain: - -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - if (offset_unitid && (ht_dev_num > 1) - && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) - && !end_used) { - u16 flags; - flags = pci_read_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_write_config16(real_last_dev, - real_last_pos + PCI_CAP_FLAGS, flags); - - for (func = real_last_dev; func; func = func->sibling) { - func->path.pci.devfn -= ((real_last_unitid - - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3); - last_func = func; - } - - /* Update last one. */ - ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; - - printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", - real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); - } -#endif - next_unitid = max_unitid; - - if (next_unitid > 0x20) - next_unitid = 0x20; - - if ((bus->secondary == 0) && (next_unitid > 0x18)) - next_unitid = 0x18; /* Avoid K8 on bus 0. */ - - /* - * Die if any leftover static devices are are found. There's probably - * a problem in devicetree.cb. - */ - if (old_devices) { - struct device *left; - for (left = old_devices; left; left = left->sibling) - printk(BIOS_DEBUG, "%s\n", dev_path(left)); - - printk(BIOS_ERR, "HT: Leftover static devices. " - "Check your devicetree.cb\n"); - - /* - * Put back the leftover static device, and let pci_scan_bus() - * disable it. - */ - if (last_func && !last_func->sibling) - last_func->sibling = old_devices; - } - - return next_unitid; -} - -/** - * Scan a PCI bridge and the buses behind the bridge. - * - * Determine the existence of buses behind the bridge. Set up the bridge - * according to the result of the scan. - * - * This function is the default scan_bus() method for PCI bridge devices. - * - * @param bus TODO - * @param min_devfn TODO - * @param max_devfn TODO - */ -static void hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn) -{ - unsigned int ht_unitid_base[4]; - unsigned int offset_unitid = 1; - - unsigned int next_unitid = do_hypertransport_scan_chain(bus, min_devfn, max_devfn, - ht_unitid_base, offset_unitid); - - /* Now that nothing is overlapping it is safe to scan the children. */ - pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); -} - -static void ht_scan_bridge(struct device *dev) -{ - do_pci_scan_bridge(dev, hypertransport_scan_chain_x); -} - -/** Default device operations for hypertransport bridges */ -static struct pci_operations ht_bus_ops_pci = { - .set_subsystem = 0, -}; - -struct device_operations default_ht_ops_bus = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = ht_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &ht_bus_ops_pci, -}; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 6075ebe..bd1b9e5 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -19,7 +19,6 @@ #include <device/pci_ids.h> #include <device/pcix.h> #include <device/pciexp.h> -#include <device/hypertransport.h> #include <pc80/i8259.h> #include <security/vboot/vbnv.h> #include <timestamp.h> @@ -861,19 +860,6 @@ return &default_pcix_ops_bus; } #endif -#if CONFIG(HYPERTRANSPORT_PLUGIN_SUPPORT) - unsigned int htpos = 0; - while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { - u16 flags; - flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); - if ((flags >> 13) == 1) { - /* Host or Secondary Interface */ - printk(BIOS_DEBUG, "%s subordinate bus HT\n", - dev_path(dev)); - return &default_ht_ops_bus; - } - } -#endif #if CONFIG(PCIEXP_PLUGIN_SUPPORT) unsigned int pciexpos; pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h deleted file mode 100644 index 382731f..0000000 --- a/src/include/device/hypertransport.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_H -#define DEVICE_HYPERTRANSPORT_H - -#include <device/hypertransport_def.h> - -extern struct device_operations default_ht_ops_bus; - -#define HT_IO_HOST_ALIGN 4096 -#define HT_MEM_HOST_ALIGN (1024*1024) - -#endif /* DEVICE_HYPERTRANSPORT_H */ diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h deleted file mode 100644 index 3cbd90b..0000000 --- a/src/include/device/hypertransport_def.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef DEVICE_HYPERTRANSPORT_DEF_H -#define DEVICE_HYPERTRANSPORT_DEF_H - -#define HT_FREQ_200Mhz 0 -#define HT_FREQ_300Mhz 1 -#define HT_FREQ_400Mhz 2 -#define HT_FREQ_500Mhz 3 -#define HT_FREQ_600Mhz 4 -#define HT_FREQ_800Mhz 5 -#define HT_FREQ_1000Mhz 6 -#define HT_FREQ_1200Mhz 7 -#define HT_FREQ_1400Mhz 8 -#define HT_FREQ_1600Mhz 9 -#define HT_FREQ_1800Mhz 10 -#define HT_FREQ_2000Mhz 11 -#define HT_FREQ_2200Mhz 12 -#define HT_FREQ_2400Mhz 13 -#define HT_FREQ_2600Mhz 14 -#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */ - -static inline bool offset_unit_id(bool is_sb_ht_chain) -{ - bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) - || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20); - return need_offset && is_sb_ht_chain; -} - -#endif /* DEVICE_HYPERTRANSPORT_DEF_H */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index c1e342c..7c37ff8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -8,7 +8,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 207bec2..2d5234d 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -8,7 +8,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cedc7da..addd40f 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -8,7 +8,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/agesa/nb_common.h b/src/northbridge/amd/agesa/nb_common.h index 31cee3c..66fbf92 100644 --- a/src/northbridge/amd/agesa/nb_common.h +++ b/src/northbridge/amd/agesa/nb_common.h @@ -3,6 +3,9 @@ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ +#define HT_IO_HOST_ALIGN 4096 +#define HT_MEM_HOST_ALIGN (1024 * 1024) + #define DEV_CDB 0x18 #endif diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 90d5603..110dc84 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 09bdd82..86c815c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 75e1f02..41554b8 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -10,7 +10,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <string.h> #include <stdlib.h> #include <lib.h> diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h index a6daba3..bee75c7 100644 --- a/src/northbridge/amd/pi/nb_common.h +++ b/src/northbridge/amd/pi/nb_common.h @@ -3,6 +3,9 @@ #ifndef __AMD_NB_COMMON_H__ #define __AMD_NB_COMMON_H__ +#define HT_IO_HOST_ALIGN 4096 +#define HT_MEM_HOST_ALIGN (1024 * 1024) + #define DEV_CDB 0x18 #define IO_APIC2_ADDR 0xfec20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/47407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Gerrit-Change-Number: 47407 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Angel Pons (Code Review) 25 Nov '20

25 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 3: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/3/src/mainboard/system76/ory… PS3, Line 87: subsystemid 0x1558 0x95e6 inherit > This is not working as I expected: Subsystem is defaulting to 8086:7270 for most PCIe entries despit […] FSP might be writing the subsystem ID, and the registers are write-once. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Nov 2020 08:53:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] soc/intel/tigerlake: Add support for calling microcode update API
by Jamie Ryu (Code Review) 25 Nov '20

25 Nov '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46644 ) Change subject: [WIP] soc/intel/tigerlake: Add support for calling microcode update API ...................................................................... [WIP] soc/intel/tigerlake: Add support for calling microcode update API This adds the entry function to call the main microcode update interface to enable microcode update for Tigerlake SoC and also implements the reboot function required. BUG=b:149547271 TEST=Build and boot volteer2 to OS Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Id60b9828498d1474193e238ec26da26ac322620e --- M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/ucode_update.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/46644/1 diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..b9b0e8c 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += me.c +ramstage-$(CONFIG_INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE) += ucode_update.c smm-y += gpio.c smm-y += p2sb.c diff --git a/src/soc/intel/tigerlake/ucode_update.c b/src/soc/intel/tigerlake/ucode_update.c new file mode 100644 index 0000000..d24e487 --- /dev/null +++ b/src/soc/intel/tigerlake/ucode_update.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <console/console.h> +#include <halt.h> +#include <intelbasecode/ucode_update.h> +#include <reset.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> +#include <soc/intel/common/reset.h> +#include <vb2_api.h> + +static void update_ucode(void *unused) +{ + if (CONFIG(INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE)) { + if (update_ucode_and_topswap_state()) { + /* Update failed */ + if (CONFIG(VBOOT)) { + printk(BIOS_DEBUG, "ucode: Failed to update microcode\n"); + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + die("ucode: Failed to trigger recovery mode\n"); + vb2api_fail(ctx, 0x36, 0x0); + vboot_save_data(ctx); + vboot_reboot(); + } + } + } +} + + +void ucode_update_reboot(void) +{ + if (CONFIG(VBOOT)) + vboot_reboot(); + else + do_board_reset(); + + die("ucode: Failed to reset the system\n"); + halt(); +} + +int ucode_update_rec_mode_enabled(void) +{ + return vboot_recovery_mode_enabled(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, update_ucode, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/46644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id60b9828498d1474193e238ec26da26ac322620e Gerrit-Change-Number: 46644 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 25 Nov '20

25 Nov '20

1 0

Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 25 Nov '20

25 Nov '20

1 0

Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 25 Nov '20

25 Nov '20

Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47892 ) Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... Patch Set 3: (10 comments) https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/devicetree.cb: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 12: # Send an extra VR mailbox command for the PS4 exit issue : register "SendVrMbxCmd" = "2" > Does this apply to your board? I don't even know what it does. But I haven't noticed any bad behavior with it removed. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 34: PchSerialIoPci > SkipInit? Not available on Coffee Lake. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 37: # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) : register "PcieClkSrcUsage[8]" = "0x40" : register "PcieClkSrcClkReq[8]" = "8" > Put under the PEG device? (01. […] Done https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 79: Enable > Nope They're all 0, so just removed the block. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/gpio.h: PS2: > This should be a gpio. […] Done https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… File src/mainboard/system76/oryp5/romstage.c: https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 7: CH0D0/CH0D1/CH1D0/CH1D1. > Two of these do not exist Comment from header. Removed from board. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 19: /* : * For each channel, there are 3 sets of DQ byte mappings, : * where each set has a package 0 and a package 1 value (package 0 : * represents the first 64-bit lpddr4 chip combination, and package 1 : * represents the second 64-bit lpddr4 chip combination). : * The first three sets are for CLK, CMD, and CTL. : * The fsp package actually expects 6 sets, but the last 3 sets are : * not used in CNL, so we only define the three sets that are used : * and let the meminit_lpddr4() routine take care of clearing the : * unused fields for the caller. : */ : .dq_map[DDR_CH0] = { : {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, : //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} : }, : .dq_map[DDR_CH1] = { : {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, : //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} : }, : : /* : * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a : * mapping of a dq bit on the CPU to the bit it's connected to on : * the memory part. The array index represents the dqs bit number : * on the memory part, and the values in the array represent which : * pin on the CPU that DRAM pin connects to. : */ : .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, : .dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7}, > Does this apply at all? I checked with Jeremy and none of our boards use LPDDR, so I've removed them. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 52: DRAM > This is wrong. […] It seems all of these are copied from the header (error including). I've just gone ahead and removed them. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 57: These will typically be the following : * values for Cannon Lake : { 80, 40, 40, 40, 30 } > Why copy this comment? Comment from header. Removed from board. https://review.coreboot.org/c/coreboot/+/47892/2/src/mainboard/system76/ory… PS2, Line 62: /* : * Indicates whether memory is interleaved. : * Set to 1 for an interleaved design, : * set to 0 for non-interleaved design. : */ > I think this is pretty obvious. Comment from header. Removed from board. -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 24 Nov 2020 23:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/oryp5: Add System76 Oryx Pro 5
by Tim Crawford (Code Review) 25 Nov '20

25 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Jeremy Soller, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47892 to look at the new patch set (#3). Change subject: mb/system76/oryp5: Add System76 Oryx Pro 5 ...................................................................... mb/system76/oryp5: Add System76 Oryx Pro 5 Tested with TianoCore payload. Not working: - Discrete/Hybrid graphics - Internal speakers Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/oryp5.md A configs/config.system76_oryp5 A src/mainboard/system76/oryp5/Kconfig A src/mainboard/system76/oryp5/Kconfig.name A src/mainboard/system76/oryp5/Makefile.inc A src/mainboard/system76/oryp5/acpi/gpe.asl A src/mainboard/system76/oryp5/acpi/mainboard.asl A src/mainboard/system76/oryp5/acpi/sleep.asl A src/mainboard/system76/oryp5/board_info.txt A src/mainboard/system76/oryp5/bootblock.c A src/mainboard/system76/oryp5/data.vbt A src/mainboard/system76/oryp5/devicetree.cb A src/mainboard/system76/oryp5/dsdt.asl A src/mainboard/system76/oryp5/gpio.c A src/mainboard/system76/oryp5/gpio_early.c A src/mainboard/system76/oryp5/hda_verb.c A src/mainboard/system76/oryp5/include/mainboard/gpio.h A src/mainboard/system76/oryp5/ramstage.c A src/mainboard/system76/oryp5/romstage.c 20 files changed, 835 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47892/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Gerrit-Change-Number: 47892 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/kbl-u: mainboard ops
by Felix Singer (Code Review) 24 Nov '20

24 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47825 ) Change subject: mb/clevo/kbl-u: mainboard ops ...................................................................... mb/clevo/kbl-u: mainboard ops Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/ramstage.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47825/1 diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c index b5d6786..4ba244d 100644 --- a/src/mainboard/clevo/kbl-u/ramstage.c +++ b/src/mainboard/clevo/kbl-u/ramstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <mainboard/gpio.h> -#include <soc/ramstage.h> /* * TODO: @@ -12,7 +11,11 @@ * - Make TBT port configurable (TBT <> DisplayPort) */ -void mainboard_silicon_init_params(FSP_SIL_UPD *params) +static void init_mainboard(void *chip_info) { mainboard_configure_gpios(); } + +struct chip_operations mainboard_ops = { + .init = init_mainboard, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/47825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288 Gerrit-Change-Number: 47825 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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