coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: arch/x86/smbios: Update SMBIOS type 16 error correction type
by Tim Chu (Code Review) 25 Nov '20

25 Nov '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47508 ) Change subject: arch/x86/smbios: Update SMBIOS type 16 error correction type ...................................................................... arch/x86/smbios: Update SMBIOS type 16 error correction type Add weak function for SMBIOS type 16 error correction type. Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/47508/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index dc676cf..f22e7e7 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -463,6 +463,12 @@ return 0x02; /* Unknown */ } +unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + return meminfo->ecc_capable ? + MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; +} + unsigned int __weak smbios_processor_external_clock(void) { return 0; /* Unknown */ @@ -1025,8 +1031,7 @@ t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; t->use = MEMORY_ARRAY_USE_SYSTEM; - t->memory_error_correction = meminfo->ecc_capable ? - MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE; + t->memory_error_correction = smbios_memory_error_correction_type(meminfo); /* no error information handle available */ t->memory_error_information_handle = 0xFFFE; diff --git a/src/include/smbios.h b/src/include/smbios.h index 6a19655..0800289 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -56,6 +56,7 @@ void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision); +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo); unsigned int smbios_processor_external_clock(void); unsigned int smbios_processor_characteristics(void); struct cpuid_result; -- To view, visit https://review.coreboot.org/c/coreboot/+/47508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85b37e9cfd22a78544d03e5506ff92b1f2404f8e Gerrit-Change-Number: 47508 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOS
by Matt DeVillier (Code Review) 25 Nov '20

25 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47725 ) Change subject: mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOS ...................................................................... mb/google/hatch: select SOC_INTEL_CSE_LITE_SKU only if CHROMEOS Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig. Conditioning on CHROMEOS allows for non-ChromeOS targets to be built. Test: build wyvern variant with CONFIG_CHROMEOS=n Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47725/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 6df8fc4..0abc3af 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,7 +11,7 @@ select RT8168_SET_LED_MODE select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD - select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_LITE_SKU if CHROMEOS select DRIVERS_INTEL_DPTF select DPTF_USE_EISA_HID -- To view, visit https://review.coreboot.org/c/coreboot/+/47725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934 Gerrit-Change-Number: 47725 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: cbfstool: Don't add compression attribute for uncompressed files
by Julius Werner (Code Review) 25 Nov '20

25 Nov '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46835 to review the following change. Change subject: cbfstool: Don't add compression attribute for uncompressed files ...................................................................... cbfstool: Don't add compression attribute for uncompressed files Our current cbfstool has always added a compression attribute to the CBFS file header for all files that used the cbfstool_convert_raw() function (basically anything other than a stage or payload), even if the compression type was NONE. This was likely some sort of oversight, since coreboot CBFS reading code has always accepted the absence of a compression attribute to mean "no compression". This patch fixes the behavior to avoid adding the attribute in these cases. Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de --- M util/cbfstool/cbfstool.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46835/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 454aff9..6b9f664 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -766,6 +766,9 @@ return -1; memcpy(compressed, buffer->data + 8, compressed_size); } else { + if (param.compression == CBFS_COMPRESS_NONE) + goto out; + compress = compression_function(param.compression); if (!compress) return -1; @@ -777,7 +780,7 @@ compressed, &compressed_size)) { WARN("Compression failed - disabled\n"); free(compressed); - return 0; + goto out; } } @@ -797,6 +800,7 @@ buffer->data = compressed; buffer->size = compressed_size; +out: header->len = htonl(buffer->size); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4a41152db9df66376fa26096d6f3a53baea51de Gerrit-Change-Number: 46835 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedef
by Angel Pons (Code Review) 25 Nov '20

25 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47001 ) Change subject: soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedef ...................................................................... soc/intel/{broadwell,quark}: Drop `PEI_DATA` typedef It is not used. Change-Id: I3ef0878811bf2ec406ded03aac6c5dfeb5bf45a2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pei_data.h M src/soc/intel/quark/include/soc/pei_wrapper.h 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47001/1 diff --git a/src/soc/intel/broadwell/pei_data.h b/src/soc/intel/broadwell/pei_data.h index bc9f220..67d73d9 100644 --- a/src/soc/intel/broadwell/pei_data.h +++ b/src/soc/intel/broadwell/pei_data.h @@ -246,6 +246,4 @@ struct pei_memory_info meminfo; } __packed; -typedef struct pei_data PEI_DATA; - #endif diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h index a14da63..5c52d3b 100644 --- a/src/soc/intel/quark/include/soc/pei_wrapper.h +++ b/src/soc/intel/quark/include/soc/pei_wrapper.h @@ -28,6 +28,4 @@ int data_to_save_size; } __packed; -typedef struct pei_data PEI_DATA; - #endif /* _PEI_WRAPPER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ef0878811bf2ec406ded03aac6c5dfeb5bf45a2 Gerrit-Change-Number: 47001 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: crossgcc: Upgrade binutils to 2.35.1
by HAOUAS Elyes (Code Review) 25 Nov '20

25 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45550 ) Change subject: crossgcc: Upgrade binutils to 2.35.1 ...................................................................... crossgcc: Upgrade binutils to 2.35.1 Change-Id: I8694a154d48c5a718b27d4beb858942db0feb997 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/binutils-2.35.1_as-ipxe.patch R util/crossgcc/patches/binutils-2.35.1_mips-gold.patch R util/crossgcc/patches/binutils-2.35.1_no-bfd-doc.patch R util/crossgcc/patches/binutils-2.35.1_no-makeinfo.patch A util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum.calc D util/crossgcc/sum/binutils-2.35.tar.xz.cksum 7 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45550/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f9cac5..e7864e4 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,7 +38,7 @@ MPC_VERSION=1.2.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.35 +BINUTILS_VERSION=2.35.1 GDB_VERSION=9.2 IASL_VERSION=20200717 PYTHON_VERSION=3.8.5 diff --git a/util/crossgcc/patches/binutils-2.35_as-ipxe.patch b/util/crossgcc/patches/binutils-2.35.1_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.35.1_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.35_mips-gold.patch b/util/crossgcc/patches/binutils-2.35.1_mips-gold.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_mips-gold.patch rename to util/crossgcc/patches/binutils-2.35.1_mips-gold.patch diff --git a/util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.35.1_no-bfd-doc.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_no-bfd-doc.patch rename to util/crossgcc/patches/binutils-2.35.1_no-bfd-doc.patch diff --git a/util/crossgcc/patches/binutils-2.35_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.35.1_no-makeinfo.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.35_no-makeinfo.patch rename to util/crossgcc/patches/binutils-2.35.1_no-makeinfo.patch diff --git a/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum.calc b/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum.calc new file mode 100644 index 0000000..b1abda8 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.35.1.tar.xz.cksum.calc @@ -0,0 +1 @@ +45f7a96a2580a422f44b78317f0abf13935fecb6 tarballs/binutils-2.35.1.tar.xz diff --git a/util/crossgcc/sum/binutils-2.35.tar.xz.cksum b/util/crossgcc/sum/binutils-2.35.tar.xz.cksum deleted file mode 100644 index 06c29b0..0000000 --- a/util/crossgcc/sum/binutils-2.35.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6bdd090ce268b6d6c3442516021c4e4b5019e303 tarballs/binutils-2.35.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/45550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8694a154d48c5a718b27d4beb858942db0feb997 Gerrit-Change-Number: 45550 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: crossgcc: Upgrade LLVM to version 11.0.0
by HAOUAS Elyes (Code Review) 25 Nov '20

25 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46379 ) Change subject: crossgcc: Upgrade LLVM to version 11.0.0 ...................................................................... crossgcc: Upgrade LLVM to version 11.0.0 Change-Id: I1cc02355e3fea7eb9ad98be6396a492dbbdc47b2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum A util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum D util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum A util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum 9 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46379/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d5cca6c..c46253f 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -44,7 +44,7 @@ PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number -CLANG_VERSION=10.0.1 +CLANG_VERSION=11.0.0 CMAKE_VERSION=3.18.1 NASM_VERSION=2.15.03 diff --git a/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 6e0d863..0000000 --- a/util/crossgcc/sum/clang-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0e61e92b22a620fe7f833fa8b2a56f2db96f7335 tarballs/clang-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..817234f --- /dev/null +++ b/util/crossgcc/sum/clang-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +02c87f5e07f2a1c1e2dbb8ce8328f0106d70b10d tarballs/clang-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 1b880c7..0000000 --- a/util/crossgcc/sum/clang-tools-extra-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -26c996da082677aca1016bcf2141dbff01dc7300 tarballs/clang-tools-extra-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..f6b260f --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +b77dc0494894b997c8f4012debbf0bf469462386 tarballs/clang-tools-extra-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum deleted file mode 100644 index 2efb413..0000000 --- a/util/crossgcc/sum/compiler-rt-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ee6077b4728b3c750e476938cead11cea45b49ff tarballs/compiler-rt-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..fe447bf --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +be3e79fb93cd99135643a191f27c49449bf9c0ee tarballs/compiler-rt-11.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum deleted file mode 100644 index a6919e8..0000000 --- a/util/crossgcc/sum/llvm-10.0.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -25d07260f3b7bf4f647e115c4a663fdeda130fbd tarballs/llvm-10.0.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..c95d6a5 --- /dev/null +++ b/util/crossgcc/sum/llvm-11.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +5723ae20d1e6e9ccfda208cb9a8cf2f87c3a6107 tarballs/llvm-11.0.0.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/46379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc02355e3fea7eb9ad98be6396a492dbbdc47b2 Gerrit-Change-Number: 46379 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: b/google/volteer/variant/lindar: change speaker smart amplifier to AL...
by Stanley Wu (Code Review) 25 Nov '20

25 Nov '20

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47009 ) Change subject: b/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011 ...................................................................... b/google/volteer/variant/lindar: change speaker smart amplifier to ALC1011 Lindar change amp to ALC1011 adding ALC1011 amp acpi info into devicetree BUG=b:171771736 BRANCH=None TEST=build and verify ALC1011 can be recognized. Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Signed-off-by: stanley.wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb 4 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47009/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..268bd69 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -22,6 +22,8 @@ bool "-> Lindar" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_MALEFOR bool "-> Malefor" diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 0538e74..08c3251 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -81,7 +81,8 @@ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio on UP3.\n"); gpio_configure_pads(i2s_up3_enable_pads, ARRAY_SIZE(i2s_up3_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..79aae1d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -14,6 +14,7 @@ option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 option MAX98373_ALC5682I_I2S_UP4 4 + option RT1011_ALC5682I_I2S 6 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 @@ -356,7 +357,7 @@ ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000), diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb index 5f0f290..2c76d1a 100644 --- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb +++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb @@ -37,6 +37,20 @@ register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/i2c/rt1011 + register "hid" = ""10EC1011"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "0" + device i2c 3a on end + probe AUDIO_RT1011_ALC5682I_I2S + end + chip drivers/i2c/rt1011 + register "hid" = ""10EC1011"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "1" + device i2c 39 on end + probe AUDIO_RT1011_ALC5682I_I2S + end end device ref i2c1 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/47009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4 Gerrit-Change-Number: 47009 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: tests: Add lib/list-test test case
by Name of user not set (Code Review) 25 Nov '20

25 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47507 ) Change subject: tests: Add lib/list-test test case ...................................................................... tests: Add lib/list-test test case Change-Id: If74f241b2bb788b3e2fd1b9062fc74819f7be31e Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/lib/Makefile.inc A tests/lib/list-test.c 2 files changed, 133 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47507/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 219f7e7..2bc1472 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -6,6 +6,7 @@ tests-y += imd-test tests-y += timestamp-test tests-y += edid-test +tests-y += list-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -30,3 +31,6 @@ edid-test-srcs += src/lib/edid.c edid-test-srcs += tests/stubs/console.c +list-test-srcs += tests/lib/list-test.c +list-test-srcs += src/lib/list.c + diff --git a/tests/lib/list-test.c b/tests/lib/list-test.c new file mode 100644 index 0000000..6688c4f --- /dev/null +++ b/tests/lib/list-test.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <stdlib.h> +#include <string.h> +#include <list.h> + +struct test_container { + int value; + + struct list_node list_node; +}; + +void test_list_insert_after(void **state) +{ + int i = 0; + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + const int values[] = { 5, 10, 13 }; /* Random values */ + + memset(c1, 0, sizeof(*c1)); + memset(c2, 0, sizeof(*c2)); + memset(c2, 0, sizeof(*c3)); + + c1->value = values[0]; + c2->value = values[1]; + c3->value = values[2]; + + list_insert_after(&c1->list_node, &root); + list_insert_after(&c2->list_node, &c1->list_node); + list_insert_after(&c3->list_node, &c2->list_node); + + list_for_each(ptr, root, list_node) { + assert_int_equal(values[i], ptr->value); + i++; + } + + assert_int_equal(3, i); + + free(c3); + free(c2); + free(c1); +} + +void test_list_insert_before(void **state) +{ + int i = 0; + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *c3 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + const int values[] = { 19, 71, 991 }; /* Random values */ + + memset(c1, 0, sizeof(*c1)); + memset(c2, 0, sizeof(*c2)); + memset(c2, 0, sizeof(*c3)); + + c1->value = values[0]; + c2->value = values[1]; + c3->value = values[2]; + + list_insert_after(&c3->list_node, &root); + list_insert_before(&c2->list_node, &c3->list_node); + list_insert_before(&c1->list_node, &c2->list_node); + + + list_for_each(ptr, root, list_node) { + assert_int_equal(values[i], ptr->value); + i++; + } + + assert_int_equal(3, i); + + free(c3); + free(c2); + free(c1); +} + +void test_list_remove(void **state) +{ + struct list_node root = { .prev = NULL, .next = NULL }; + struct test_container *c1 = (struct test_container *)malloc(sizeof(*c1)); + struct test_container *c2 = (struct test_container *)malloc(sizeof(*c2)); + struct test_container *ptr; + int len; + + list_insert_after(&c1->list_node, &root); + list_insert_after(&c2->list_node, &c1->list_node); + + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(2, len); + + list_remove(&c1->list_node); + + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(1, len); + + list_remove(&c2->list_node); + len = 0; + list_for_each(ptr, root, list_node) { + len++; + } + assert_int_equal(0, len); + + free(c2); + free(c1); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_list_insert_after), + cmocka_unit_test(test_list_insert_before), + cmocka_unit_test(test_list_remove), + }; + + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74f241b2bb788b3e2fd1b9062fc74819f7be31e Gerrit-Change-Number: 47507 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: MAINTAINERS: Add maintainers for kontron/mal10
by Felix Singer (Code Review) 25 Nov '20

25 Nov '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47889 ) Change subject: MAINTAINERS: Add maintainers for kontron/mal10 ...................................................................... MAINTAINERS: Add maintainers for kontron/mal10 Add Maxim Polyakov, Nico Huber and Felix Singer as maintainers for kontron/mal10. Change-Id: I2f4200708e4aec6d74916fb5e63efe2f20594882 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M MAINTAINERS 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/47889/1 diff --git a/MAINTAINERS b/MAINTAINERS index b4b685c..4f643b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -288,6 +288,13 @@ S: Supported F: src/mainboard/kontron/bsl6/ +KONTRON MAL10 MAINBOARD +M: Maxim Polyakov <max.senia.poliak(a)gmail.com> +M: Nico Huber <nico.h(a)gmx.de> +M: Felix Singer <felixsinger(a)posteo.net> +S: Supported +F: src/mainboard/kontron/mal10/ + LENOVO MAINBOARDS -- To view, visit https://review.coreboot.org/c/coreboot/+/47889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f4200708e4aec6d74916fb5e63efe2f20594882 Gerrit-Change-Number: 47889 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: Support SIO1036 with addresses other than 0x4e/0x4d
by Nikolai Vyssotski (Code Review) 25 Nov '20

25 Nov '20

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47545 ) Change subject: Support SIO1036 with addresses other than 0x4e/0x4d ...................................................................... Support SIO1036 with addresses other than 0x4e/0x4d Newer LPC Mandolin debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d as before. Add support for configurable SIO address (SUPERIO_ADR_RANGE) to support these cards. Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/mainboard/amd/mandolin/bootblock.c M src/superio/smsc/sio1036/Kconfig M src/superio/smsc/sio1036/sio1036_early_init.c 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47545/1 diff --git a/src/mainboard/amd/mandolin/bootblock.c b/src/mainboard/amd/mandolin/bootblock.c index 06da379..dc3ce34 100644 --- a/src/mainboard/amd/mandolin/bootblock.c +++ b/src/mainboard/amd/mandolin/bootblock.c @@ -5,14 +5,19 @@ #include <superio/smsc/sio1036/sio1036.h> #include "gpio.h" -#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) +#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADR_RANGE, SIO1036_SP1) void bootblock_mainboard_early_init(void) { mainboard_program_early_gpios(); if (CONFIG(SUPERIO_SMSC_SIO1036)) { - lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + if ((CONFIG_SUPERIO_ADR_RANGE == 0x4e) || (CONFIG_SUPERIO_ADR_RANGE == 0x2e)) { + lpc_enable_sio_decode(LPC_WIDEIO0_ENABLE); + } else { + // set up 16 byte wide I/O range window for the super IO + lpc_set_wideio_range(CONFIG_SUPERIO_ADR_RANGE & ~0xF, 16); + } lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig index 94899ff..fb13d73 100644 --- a/src/superio/smsc/sio1036/Kconfig +++ b/src/superio/smsc/sio1036/Kconfig @@ -2,3 +2,8 @@ config SUPERIO_SMSC_SIO1036 bool + +config SUPERIO_ADR_RANGE + depends on SUPERIO_SMSC_SIO1036 + hex "I/O address for SMSC1036 SIO" + default 0x4e diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index a65f672..c4a580a 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -10,13 +10,13 @@ static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0x55, port); } static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { - u8 port = dev >> 8; + u16 port = dev >> 8; outb(0xaa, port); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Gerrit-Change-Number: 47545 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 16

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020