coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Lock PAM and SMRAM registers
by Arthur Heymans (Code Review) 25 Nov '20

25 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47168 ) Change subject: soc/intel/xeon_sp: Lock PAM and SMRAM registers ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/47168/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47168/4//COMMIT_MSG@7 PS4, Line 7: soc/intel/xeon_sp: Follow the Integration Guide recommendations > The subject and commit message can be more specific, as there are only two items. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Gerrit-Change-Number: 47168 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 25 Nov 2020 15:23:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig
by Furquan Shaikh (Code Review) 25 Nov '20

25 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47999 ) Change subject: drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Gerrit-Change-Number: 47999 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Nov 2020 14:39:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: introduce possibility of using a full FD binary
by Furquan Shaikh (Code Review) 25 Nov '20

25 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47993 ) Change subject: drivers/intel/fsp2_0: introduce possibility of using a full FD binary ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/47993/4/src/drivers/intel/fsp2_0/K… File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/47993/4/src/drivers/intel/fsp2_0/K… PS4, Line 60: !FSP_USE_REPO Why did this change to !FSP_USE_REPO? https://review.coreboot.org/c/coreboot/+/47993/4/src/drivers/intel/fsp2_0/K… PS4, Line 88: Use a combined FSP FD file instead of individual, split binaries. Probably say that this takes as input a combined FSP FD file instead of individual, split binaries and converts them to individual, split binaries at build time. -- To view, visit https://review.coreboot.org/c/coreboot/+/47993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Gerrit-Change-Number: 47993 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Nov 2020 14:38:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig
by Michael Niewöhner (Code Review) 25 Nov '20

25 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47999 ) Change subject: drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Gerrit-Change-Number: 47999 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Nov 2020 14:27:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: introduce possibility of using a full FD binary
by Michael Niewöhner (Code Review) 25 Nov '20

25 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47993 ) Change subject: drivers/intel/fsp2_0: introduce possibility of using a full FD binary ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Gerrit-Change-Number: 47993 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 25 Nov 2020 14:27:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Lock PAM and SMRAM registers
by Arthur Heymans (Code Review) 25 Nov '20

25 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47168 to look at the new patch set (#11). Change subject: soc/intel/xeon_sp: Lock PAM and SMRAM registers ...................................................................... soc/intel/xeon_sp: Lock PAM and SMRAM registers The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47168/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/47168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Gerrit-Change-Number: 47168 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] mb/google/volteer: Enable microcode update
by Jamie Ryu (Code Review) 25 Nov '20

25 Nov '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46649 ) Change subject: [WIP] mb/google/volteer: Enable microcode update ...................................................................... [WIP] mb/google/volteer: Enable microcode update This enables the top swap based microcode update. BUG=b:149547271 TEST=Build and boot volteer2 to OS. Check ucode staging area is updated with microcode in FW_MAIN_A/B and the top swap is enabled. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Ib821bd52af903bb5c9a7c08231dfbd98fe55a24f --- M src/mainboard/google/volteer/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/46649/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 69f58b5..edbfc61 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -29,6 +29,8 @@ select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE select HAVE_SPD_IN_CBFS + select SOC_INTEL_COMMON_BASECODE + select INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -137,4 +139,8 @@ bool default n +config INTEL_TOP_SWAP_BOOTBLOCK_SIZE + hex + default 0x10000 + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/46649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib821bd52af903bb5c9a7c08231dfbd98fe55a24f Gerrit-Change-Number: 46649 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Arthur Heymans (Code Review) 25 Nov '20

25 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 67: Code-Review+1 (7 comments) A few minor remarks but looks good to me. https://review.coreboot.org/c/coreboot/+/27369/67//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/67//COMMIT_MSG@27 PS67, Line 27: register nit: PCR register https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/Kconfig: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 6: select maybe depends on is better? That way you are a bit more aware in the soc code which dependency you pull in? https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 111: if (rdev_writeat(staging_rdev, cbfs_microcode, 0, : get_microcode_size(cbfs_microcode)) < 0) { : printk(BIOS_ERR, "ucode: Failed to write microcode to staging area\n"); : return UCODE_FWU_STAGING_WRITE_ERROR; : } If the MCU is bigger than the staging area this will fail but it might be a good idea to be more verbose, by for instance adding an additional check after the intel_microcode_find() call? https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 162: tatic int use the return type enum ucode_fwu_failure_reason (Add success to the enum?)? https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 211: stagin staging https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 260: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ucode_fw_sync, NULL); Can this be done as part of coreboot_init_cpus() and somehow avoid calling intel_microcode_find() twice? https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 6: /* : * This is a weak implementation to reboot after ucode update is finished. : * This can be overridden by mainboard/SoC specific implementation. : */ : void ucode_reboot_platform(void); : : /* : * This is a weak implementation for the ucode update module to know if receovery mdoe is : * enabled. This returns non-zero if recovery mode enabled and can be overridden by : * mainboard/SoC specific implementation. : */ : int ucode_update_rec_mode_enabled(void); What kind of override do you plan to implement? Maybe keep it non weak for now and change that when needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 67 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Wed, 25 Nov 2020 12:43:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor/sc7180: Clarify USE_QC_BLOBS requirements
by Julius Werner (Code Review) 25 Nov '20

25 Nov '20

Hello Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45214 to review the following change. Change subject: trogdor/sc7180: Clarify USE_QC_BLOBS requirements ...................................................................... trogdor/sc7180: Clarify USE_QC_BLOBS requirements This patch adds some Kconfig hints to make it clearer that the USE_QC_BLOBS option is required for SC7180 boards and guide the user in the right direction through menuconfig. Also add those little arrows to the Trogdor board options that are there on most other boards. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 --- M src/mainboard/google/trogdor/Kconfig.name M src/soc/qualcomm/sc7180/Kconfig 2 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45214/1 diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index b7c03f9..4c1d351 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,17 +1,24 @@ comment "Trogdor" +if USE_QC_BLOBS + config BOARD_GOOGLE_BUBS - bool "Bubs" + bool "-> Bubs" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_LAZOR - bool "Lazor" + bool "-> Lazor" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_POMPOM - bool "Pompom" + bool "-> Pompom" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_TROGDOR - bool "Trogdor" + bool "-> Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON + +endif + +comment "(Trogdor requires 'Allow QC blobs repository')" + depends on !USE_QC_BLOBS diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index db7350f..488fec6 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -2,6 +2,7 @@ config SOC_QUALCOMM_SC7180 bool default n + depends on USE_QC_BLOBS select ARCH_BOOTBLOCK_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 -- To view, visit https://review.coreboot.org/c/coreboot/+/45214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7 Gerrit-Change-Number: 45214 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Define SMBIOS type 16 error correction type by RasM...
by Tim Chu (Code Review) 25 Nov '20

25 Nov '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47509 ) Change subject: mb/ocp/deltalake: Define SMBIOS type 16 error correction type by RasModesEnabled ...................................................................... mb/ocp/deltalake: Define SMBIOS type 16 error correction type by RasModesEnabled Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type 16 error correction type Tested=Execute "dmidecode -t 16" to check if error correction type is correct. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47509/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9d57090..fc5994d 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -23,9 +23,44 @@ #define SLOT_ID_LEN 2 +/* Bit definitions for RasModes */ +#define CH_INDEPENDENT 0 +#define FULL_MIRROR_1LM BIT0 +#define FULL_MIRROR_2LM BIT1 +#define CH_LOCKSTEP BIT2 +#define RK_SPARE BIT3 +#define PARTIAL_MIRROR_1LM BIT5 +#define PARTIAL_MIRROR_2LM BIT6 +#define STAT_VIRT_LOCKSTEP BIT7 + extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; +/* Override SMBIOS type 16 error correction type. */ +unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo) +{ + const struct SystemMemoryMapHob *hob; + + hob = get_system_memory_map(); + assert(hob != NULL); + + switch(hob->RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + /* * Update SMBIOS type 0 ec version. * In deltalake, BMC version is used to represent ec version. -- To view, visit https://review.coreboot.org/c/coreboot/+/47509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68 Gerrit-Change-Number: 47509 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020