coreboot-gerrit October 2020

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Change in coreboot[master]: nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write
by Angel Pons (Code Review) 18 Feb '21

18 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46994 ) Change subject: nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write ...................................................................... nb/intel/haswell: Drop invalid MMIO_PAVP_MSG write This write was copied from Sandy Bridge. Neither Haswell reference code nor Broadwell perform this write. Therefore, it is safe to remove it. Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46994/1 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e31337b..bbc6bf6 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -585,9 +585,6 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); - - /* Set here before graphics PM init. */ - MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } static struct device_operations mc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82 Gerrit-Change-Number: 46994 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: SMBIOS: Update smbios.h
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44850 ) Change subject: SMBIOS: Update smbios.h ...................................................................... SMBIOS: Update smbios.h Type 9: add PCI Express Gen 5. add OCP NIC. add Slot Type extensions for PCIe Gen6. add support for CXL 2.0. add EDSFF slot types Type 17: add new memory device types DDR5 and LPDDR5 Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/smbios.h 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44850/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index 521339e..a91f6a6 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -174,6 +174,8 @@ MEMORY_TYPE_LOGICAL_NON_VOLATILE_DEVICE = 0x1f, MEMORY_TYPE_HBM = 0x20, MEMORY_TYPE_HBM2 = 0x21, + MEMORY_TYPE_DDR5 = 0x22, + MEMORY_TYPE_LPDDR5 = 0x23, } smbios_memory_type; typedef enum { @@ -664,6 +666,11 @@ SlotTypePciExpressMini52pinWithBSKO = 0x21, SlotTypePciExpressMini52pinWithoutBSKO = 0x22, SlotTypePciExpressMini76pin = 0x23, + SlotTypePciExpressGen4SFF8639 = 0x24, + SlotTypePciExpressGen5SFF8639 = 0x25, + SlotTypeOcpNic3SFF = 0x26, + SlotTypeOcpNic3LFF = 0x27, + SlotTypeOcpNicPriorTo3 = 0x28, SlotTypePC98C20 = 0xA0, SlotTypePC98C24 = 0xA1, SlotTypePC98E = 0xA2, @@ -692,7 +699,16 @@ SlotTypePciExpressGen4x2 = 0xBA, SlotTypePciExpressGen4x4 = 0xBB, SlotTypePciExpressGen4x8 = 0xBC, - SlotTypePciExpressGen4x16 = 0xBD + SlotTypePciExpressGen4x16 = 0xBD, + SlotTypePciExpressGen5 = 0xBE, + SlotTypePciExpressGen5x1 = 0xBF, + SlotTypePciExpressGen5x2 = 0xC0, + SlotTypePciExpressGen5x4 = 0xC1, + SlotTypePciExpressGen5x8 = 0xC2, + SlotTypePciExpressGen5x16 = 0xC3, + SlotTypePciExpressGen6 = 0xC4, + SlotTypeEDSFFE1 = 0xC5, + SlotTypeEDSFFE3 0xC6 }; /* System Slots - Slot Data Bus Width. */ @@ -744,6 +760,9 @@ #define SMBIOS_SLOT_HOTPLUG (1 << 1) #define SMBIOS_SLOT_SMBUS (1 << 2) #define SMBIOS_SLOT_BIFURCATION (1 << 3) +#define SMBIOS_SLOT_ASYNC (1 << 4) +#define SMBIOS_SLOT_CXL_1 (1 << 5) +#define SMBIOS_SLOT_CXL_2 (1 << 6) struct slot_peer_groups { u16 peer_seg_num; -- To view, visit https://review.coreboot.org/c/coreboot/+/44850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I023b901c1cb4ebe07679885a9f5e0d1e95488a30 Gerrit-Change-Number: 44850 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46283 ) Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..5a394c6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -105,18 +105,18 @@ pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); + mchbar32_or(SAPMCTL, (1 << 9) | (1 << 10)); /* Enable SA Clock Gating */ - MCHBAR32_OR(SAPMCTL, 1); + mchbar32_or(SAPMCTL, 1); /* GPU RC6 workaround for sighting 366252 */ - MCHBAR32_OR(SSKPD_HI, 1 << 31); + mchbar32_or(SSKPD_HI, 1 << 31); /* VLW (Virtual Legacy Wire?) */ - MCHBAR32_AND(0x6120, ~(1 << 0)); + mchbar32_unset(0x6120, (1 << 0)); - MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); + mchbar32_or(INTRDIRCTL, (1 << 4) | (1 << 5)); } static void start_peg_link_training(void) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 26c5306..1550253 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -18,13 +18,13 @@ pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_or(PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_or(SAPMCTL, 1 << 31); /* SA PM */ + mchbar32_or(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_or(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_or(REQLIM, 1 << 31); + mchbar32_or(DMIVCLIM, 1 << 31); + mchbar32_or(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 541bf73..db768a8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -359,10 +359,10 @@ * * FIXME: Never clock gate on Ivy Bridge stepping A0! */ - MCHBAR32_OR(PEGCTL, 1); + mchbar32_or(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } else { - MCHBAR32_AND(PEGCTL, ~1); + mchbar32_unset(PEGCTL, 1); } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..4c6c284 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -190,11 +190,11 @@ stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + mchbar32_unset_and_set(addr, 0x00003c00, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + mchbar32_unset_and_set(addr, 0x000f0000, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -254,7 +254,7 @@ MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); + mchbar32_or(addr, 0x00020000); dram_odt_stretch(ctrl, channel); @@ -271,7 +271,7 @@ printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + mchbar32_or(TC_RFP_ch(channel), 0xff); /* Self-refresh timing parameters */ reg = 0; @@ -652,19 +652,19 @@ MCHBAR32(MC_INIT_STATE_G) = reg; /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + mchbar32_unset(MC_INIT_STATE_G, 2); /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + mchbar32_or(MC_INIT_STATE_G, 2); /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + mchbar32_or(MC_INIT_STATE_G, 4); /* XXX Wait 20ns */ udelay(1); @@ -957,10 +957,10 @@ } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x200000); wait_for_iosav(channel); @@ -2637,15 +2637,15 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + mchbar32_or(TC_RWP_ch(channel), 0x8000000); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2678,10 +2678,10 @@ wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x00200000); MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); @@ -2723,7 +2723,7 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); } FOR_ALL_POPULATED_CHANNELS { @@ -2747,7 +2747,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); } return 0; } @@ -2978,11 +2978,11 @@ iosav_run_once(channel); wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); } /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); @@ -3985,8 +3985,8 @@ FOR_ALL_POPULATED_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + mchbar32_unset_and_set(GDCRCMDDEBUGMUXCFG_Cz_S(channel), + 0x3f000000, rege3c_b24[i] << 24); udelay(2); @@ -4053,7 +4053,7 @@ FOR_ALL_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); } @@ -4423,7 +4423,7 @@ FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + mchbar32_or(TC_RAP_ch(channel), 0x20000000); } udelay(1); @@ -4463,7 +4463,7 @@ int channel; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + mchbar32_unset(TC_RAP_ch(channel), 0x20000000); } } @@ -4487,7 +4487,7 @@ MCHBAR32(WMM_READ_CONFIG) = 0x46; FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + mchbar32_unset_and_set(TC_OTHP_ch(channel), 0x00003000, 0x1000); if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,14 +4522,14 @@ } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); - MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); + mchbar32_unset_and_set(MEM_TRML_THRESHOLDS_CONFIG, 0x00ffffff, 0x00e4d5d0); + mchbar32_unset(MEM_TRML_INTERRUPT, 0x1f); FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + mchbar32_unset_and_set(TC_RFP_ch(channel), (3 << 16), 1 << 16); - MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + mchbar32_or(MC_INIT_STATE_G, 1); + mchbar32_or(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel */ @@ -4555,7 +4555,7 @@ /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + mchbar32_unset_and_set(SSKPD, 3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } @@ -4586,11 +4586,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + mchbar32_or(TC_RWP_ch(channel), 0x08000000); FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x00200000); } printram("CPE\n"); @@ -4646,7 +4646,7 @@ MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index c86b524..217b186 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -50,16 +50,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #include "registers/epbar.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/46283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Gerrit-Change-Number: 46283 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: crossgcc: Upgrade GCC to 10.1.0
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42251 ) Change subject: crossgcc: Upgrade GCC to 10.1.0 ...................................................................... crossgcc: Upgrade GCC to 10.1.0 nds32, GNAT bad constant and gnat_eh patches are integrated in upstream so we don't need them anymore. Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-10.1.0_ada-musl_workaround.patch R util/crossgcc/patches/gcc-10.1.0_gnat.patch R util/crossgcc/patches/gcc-10.1.0_libgcc.patch D util/crossgcc/patches/gcc-8.3.0_gnat-bad_constant.patch D util/crossgcc/patches/gcc-8.3.0_gnat_eh.patch D util/crossgcc/patches/gcc-8.3.0_nds32_ite.patch A util/crossgcc/sum/gcc-10.1.0.tar.xz.cksum D util/crossgcc/sum/gcc-8.3.0.tar.xz.cksum 9 files changed, 2 insertions(+), 21,441 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42251/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d279dd6cfc7b2382b51469b04dbec83a91295d1 Gerrit-Change-Number: 42251 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

9 41

Change in coreboot[master]: nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46279 ) Change subject: nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/x4x: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: I89fe15143abcbb74abae6ebf126b219ed88b4153 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 2 files changed, 282 insertions(+), 292 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46279/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 617ce11..5e5f473 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -36,7 +36,7 @@ { u8 i, j; u32 reg32; - MCHBAR16_OR(0xc1c, (1 << 15)); + mchbar16_or(0xc1c, (1 << 15)); static const u32 clkxtab[6][3][13] = { /* MEMCLK 400 N/A */ @@ -108,7 +108,7 @@ } MCHBAR32(0xc50) = reg32; MCHBAR32(0xc54) = clkxtab[i][j][2]; - MCHBAR8_OR(0xc08, (1 << 7)); + mchbar8_or(0xc08, (1 << 7)); MCHBAR32(0x6d8) = clkxtab[i][j][3]; MCHBAR32(0x6e0) = clkxtab[i][j][3]; MCHBAR32(0x6dc) = clkxtab[i][j][4]; @@ -126,29 +126,29 @@ static void setioclk_dram(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; - MCHBAR16_OR(0x1c0, 0x200); - MCHBAR16_OR(0x1c0, 0x100); - MCHBAR16_OR(0x1c0, 0x20); - MCHBAR16_AND(0x1c0, ~1); + mchbar16_or(0x1c0, 0x200); + mchbar16_or(0x1c0, 0x100); + mchbar16_or(0x1c0, 0x20); + mchbar16_unset(0x1c0, 1); switch (s->selected_timings.mem_clk) { default: case MEM_CLOCK_800MHz: case MEM_CLOCK_1066MHz: - MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2); - MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0); - MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0); + mchbar8_unset_and_set(0x5d9, 0x2, 0x2); + mchbar8_unset_and_set(0x9d9, 0x2, 0x2); + mchbar8_unset_and_set(0x189, 0xf0, 0xc0); + mchbar8_unset_and_set(0x189, 0xf0, 0xe0); + mchbar8_unset_and_set(0x189, 0xf0, 0xa0); break; case MEM_CLOCK_667MHz: case MEM_CLOCK_1333MHz: - MCHBAR8_AND(0x5d9, ~0x2); - MCHBAR8_AND(0x9d9, ~0x2); - MCHBAR8_AND_OR(0x189, ~0xf0, 0x40); + mchbar8_unset(0x5d9, 0x2); + mchbar8_unset(0x9d9, 0x2); + mchbar8_unset_and_set(0x189, 0xf0, 0x40); break; } - MCHBAR32_OR(0x594, 1 << 31); - MCHBAR32_OR(0x994, 1 << 31); + mchbar32_or(0x594, 1 << 31); + mchbar32_or(0x994, 1 << 31); } static void launch_dram(struct sysinfo *s) @@ -236,84 +236,84 @@ MCHBAR32(0x400*i + 0x220) = launch1; MCHBAR32(0x400*i + 0x224) = launch2; MCHBAR32(0x400*i + 0x21c) = 0; - MCHBAR32_OR(0x400*i + 0x248, 1 << 23); + mchbar32_or(0x400*i + 0x248, 1 << 23); } - MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000); - MCHBAR32_OR(0x2c0, 0x1e0); - MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc); + mchbar32_unset_and_set(0x2c0, 0x58000000, 0x48000000); + mchbar32_or(0x2c0, 0x1e0); + mchbar32_unset_and_set(0x2c4, 0xf, 0xc); if (s->spd_type == DDR3) - MCHBAR32_OR(0x2c4, 0x100); + mchbar32_or(0x2c4, 0x100); } static void clkset0(u8 ch, const struct dll_setting *setting) { - MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440, + mchbar32_unset_and_set(0x260 + (channel << 10), 0xf00000, (setting->clk_delay << 14) | (setting->db_sel << 6) | (setting->db_en << 10)); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x581, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x581, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x581, 0xf, setting->tap); } static void clkset1(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880, + mchbar16_unset_and_set(0x400*i + 0x260, 0x3fe, (setting->clk_delay << 16) | (setting->db_sel << 7) | (setting->db_en << 11)); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x582, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x582, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x582, 0xf, setting->tap); } static void ctrlset0(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000, + mchbar16_unset_and_set(0x400*i + 0x265, 0x3f00, (setting->clk_delay << 24) | (setting->db_sel << 20) | (setting->db_en << 21)); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x584, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x584, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x584, 0xf, setting->tap); } static void ctrlset1(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000, + mchbar8_unset_and_set(0x400*ch + 0x500 + lane * 4 + rank, 0x7f, (setting->clk_delay << 27) | (setting->db_sel << 22) | (setting->db_en << 23)); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x585, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x585, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x585, 0xf, setting->tap); } static void ctrlset2(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4)), (setting->clk_delay << 14) | (setting->db_sel << 12) | (setting->db_en << 13)); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x586, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x586, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x586, 0xf, setting->tap); } static void ctrlset3(u8 ch, const struct dll_setting *setting) { - MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000, + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4)), (setting->clk_delay << 10) | (setting->db_sel << 8) | (setting->db_en << 9)); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x587, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x587, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x587, 0xf, setting->tap); } static void cmdset(u8 ch, const struct dll_setting *setting) { - MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4); - MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60, + mchbar8_unset_and_set(0x400*ch + 0x598, 0x30, setting->clk_delay << 4); + mchbar16_unset_and_set(0x400*i + 0x320, 0xffff, (setting->db_sel << 5) | (setting->db_en << 6)); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0x70, setting->pi << 4); - MCHBAR8_AND_OR(0x400*ch + 0x580, ~0xf, setting->tap); + mchbar8_unset_and_set(0x400*ch + 0x580, 0x70, setting->pi << 4); + mchbar8_unset_and_set(0x400*ch + 0x580, 0xf, setting->tap); } /** @@ -324,16 +324,16 @@ { int rank; - MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)), + mchbar32_unset_and_set(0x400 * ch + 0x5fc, (1 << (lane * 4 + 1)), setting->coarse << (lane * 4 + 1)); for (rank = 0; rank < 4; rank++) { - MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane), + mchbar8_unset_and_set(0x400*ch + 0x594, 0x60, (setting->db_en << (9 + lane)) | (setting->db_sel << lane)); - MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4, - ~(0x3 << (16 + lane * 2)), + mchbar32_unset_and_set(0x400*ch + 0x5c8 + rank * 4, + 3 << (16 + lane * 2)), setting->clk_delay << (16+lane * 2)); MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) = @@ -346,18 +346,18 @@ void dqset(u8 ch, u8 lane, const struct dll_setting *setting) { int rank; - MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)), + mchbar32_unset_and_set(0x400 * ch + 0x5b4 + rank * 4, (0x201 << lane), setting->coarse << (lane * 4)); for (rank = 0; rank < 4; rank++) { - MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane), + mchbar32_unset_and_set(0x400*ch + 0x598, 0x18c00000, (setting->db_en << (9 + lane)) | (setting->db_sel << lane)); - MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4, - ~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane)); + mchbar32_unset_and_set(0x400 * ch + 0x5c8 + rank * 4, + 3 << lane * 2, setting->clk_delay << (2 * lane)); - MCHBAR8_AND_OR(0x400*ch + 0x500 + lane * 4 + rank, ~0x7f, + mchbar32_unset_and_set(0x400*i + addr[j], 0xff000, (setting->pi << 4) | setting->tap); } } @@ -498,12 +498,12 @@ } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR8_OR(0x400*i + 0x26f, 0x3); - MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2); + mchbar8_or(0x400*i + 0x26f, 0x3); + mchbar8_unset_and_set(0x400*i + 0x228, 0x7, 0x2); /* tWL - x ?? */ - MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4); - MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas); - MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00, + mchbar8_unset_and_set(0x400*i + 0x240, 0xf0, 0 << 4); + mchbar8_unset_and_set(0x400*i + 0x240, 0xf, adjusted_cas); + mchbar16_unset_and_set(C0CKTX, 0x00030880, (adjusted_cas + 9) << 8); reg16 = (s->selected_timings.tRAS << 11) | @@ -539,10 +539,10 @@ MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | s->selected_timings.tRFC; - MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe, + mchbar16_unset_and_set(C0CKTX, 0xc440, (s->spd_type == DDR2 ? 100 : 256) << 1); MCHBAR8(0x400*i + 0x264) = 0xff; - MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f, + mchbar8_unset_and_set(0x400*i + addr[j], 1, s->selected_timings.tRAS); MCHBAR16(0x400*i + 0x244) = 0x2310; @@ -555,7 +555,7 @@ break; } - MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1); + mchbar8_unset_and_set(0x400*i + 0x246, 0x1f, (reg8 << 2) | 1); fsb = fsb_to_ps[s->selected_timings.fsb_clk]; ddr = ddr_to_ps[s->selected_timings.mem_clk]; @@ -566,7 +566,7 @@ ddr_to_mhz(s->selected_timings.mem_clk)) > 2) { reg32 |= 1 << 24; } - MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32); + mchbar32_unset_and_set(0x400*i + 0x248, 0x0f001f00, reg32); if (twl > 2) flag1 = 1; @@ -582,13 +582,13 @@ } reg16 |= flag1 << 8; reg16 |= flag2 << 9; - MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16); + mchbar16_unset_and_set(0x400*i + 0x24d, 0x1ff, reg16); MCHBAR16(0x400*i + 0x25e) = 0x15a5; - MCHBAR32_AND(0x400*i + 0x265, ~0x1f); - MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff, + mchbar32_unset(0x400*i + 0x265, 0x1f); + mchbar8_unset_and_set(0x400*i + 0x25d, 0x3f, (0x3f << 14) | lut1[s->selected_timings.mem_clk]); - MCHBAR8_OR(0x400*i + 0x274, 1); - MCHBAR8_AND(0x400*i + 0x24c, ~0x3); + mchbar8_or(0x400*i + 0x274, 1); + mchbar8_unset(0x400*i + 0x24c, 0x3); reg16 = 0; if (s->spd_type == DDR2) { @@ -620,36 +620,36 @@ reg16 &= 0x7; reg16 += twl + 9; reg16 <<= 10; - MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16); - MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13); - MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a); + mchbar16_unset_and_set(0x400*i + 0x24d, 0x7c00, reg16); + mchbar8_unset_and_set(0x400*i + 0x267, 0x3f, 0x13); + mchbar8_unset_and_set(0x400*i + 0x268, 0xff, 0x4a); reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; reg16 += 2 << 12; reg16 |= (0x15 << 6) | 0x1f; - MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16); + mchbar16_unset_and_set(0x400*i + 0x26d, 0x7fff, reg16); reg32 = (1 << 25) | (6 << 27); - MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32); - MCHBAR8_AND(0x400*i + 0x271, ~0x80); - MCHBAR8_AND(0x400*i + 0x274, ~0x6); + mchbar32_unset_and_set(0x400*i + 0x269, 0xfa300000, reg32); + mchbar8_unset(0x400*i + 0x271, 0x80); + mchbar8_unset(0x400*i + 0x274, 0x6); } // END EACH POPULATED CHANNEL reg16 = 0x1f << 5; reg16 |= 0xe << 10; - MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16); - MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540); - MCHBAR8_OR(0x129, 0x1f); - MCHBAR8_OR(0x12c, 0xa0); - MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11); - MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11); - MCHBAR8_AND(0x246, ~0x10); - MCHBAR8_AND(0x646, ~0x10); + mchbar16_unset_and_set(0x125, 0x3fe0, reg16); + mchbar16_unset_and_set(0x127, 0x7ff, 0x540); + mchbar8_or(0x129, 0x1f); + mchbar8_or(0x12c, 0xa0); + mchbar32_unset_and_set(0x241, 0x1ffff, 0x11); + mchbar32_unset_and_set(0x641, 0x1ffff, 0x11); + mchbar8_unset(0x246, 0x10); + mchbar8_unset(0x646, 0x10); MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); - MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4); + mchbar8_unset_and_set(0x12d, 0xf0, reg8 << 4); reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); - MCHBAR8_AND_OR(0x12d, ~0xf, reg8); + mchbar8_unset_and_set(0x12d, 0xf, reg8); MCHBAR8(0x12f) = 0x4c; reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); if (s->spd_type == DDR3) { @@ -660,8 +660,8 @@ reg16 &= 0x1ff; reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); } - MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32); - MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2); + mchbar32_unset_and_set(0x6c0, 0xffffff00, reg32); + mchbar8_unset_and_set(0x6c4, 0x7, 0x2); } static void program_dll(struct sysinfo *s) @@ -673,11 +673,11 @@ const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, 0x08, 0x10 }; - MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04); - MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8); - MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f); - MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100); - MCHBAR8_AND_OR(0x194, ~0x77, 0x33); + mchbar16_unset_and_set(0x180, 0x7e06, 0xc04); + mchbar16_unset_and_set(0x182, 0x3ff, 0xc8); + mchbar16_unset_and_set(0x18a, 0x1f1f, 0x0f0f); + mchbar16_unset_and_set(0x1b4, 0x8020, 0x100); + mchbar8_unset_and_set(0x194, 0x77, 0x33); switch (s->selected_timings.mem_clk) { default: case MEM_CLOCK_667MHz: @@ -691,48 +691,48 @@ reg16 = (0x7 << 9) | 0x7; break; } - MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16); - MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010); + mchbar16_unset_and_set(0x19c, 0x1e0f, reg16); + mchbar16_unset_and_set(0x19c, 0x2030, 0x2010); udelay(1); - MCHBAR16_AND(0x198, ~0x100); + mchbar16_unset(0x198, 0x100); - MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd); + mchbar16_unset_and_set(0x1c8, 0x1f, 0xd); udelay(1); - MCHBAR8_AND(0x190, ~1); + mchbar8_unset(0x190, 1); udelay(1); // 533ns - MCHBAR32_AND(0x198, ~0x11554000); + mchbar32_unset(0x198, 0x11554000); udelay(1); - MCHBAR32_AND(0x198, ~0x1455); + mchbar32_unset(0x198, 0x1455); udelay(1); - MCHBAR8_AND(0x583, ~0x1c); - MCHBAR8_AND(0x983, ~0x1c); + mchbar8_unset(0x583, 0x1c); + mchbar8_unset(0x983, 0x1c); udelay(1); // 533ns - MCHBAR8_AND(0x583, ~0x3); - MCHBAR8_AND(0x983, ~0x3); + mchbar8_unset(0x583, 0x3); + mchbar8_unset(0x983, 0x3); udelay(1); // 533ns // ME related - MCHBAR32_AND_OR(0x1a0, ~0x7ffffff, + mchbar32_unset_and_set(0x400*ch + 0x59c, 0x18c00000, s->spd_type == DDR2 ? 0x551803 : 0x555801); - MCHBAR16_AND(0x1b4, ~0x800); + mchbar16_unset(0x1b4, 0x800); if (s->spd_type == DDR2) { - MCHBAR8_OR(0x1a8, 0xf0); + mchbar8_or(0x1a8, 0xf0); } else { /* DDR3 */ reg8 = 0x9; /* 0x9 << 4 ?? */ if (s->dimms[0].ranks == 2) reg8 &= ~0x80; if (s->dimms[3].ranks == 2) reg8 &= ~0x10; - MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8); + mchbar8_unset_and_set(0x1a8, 0xf0, reg8); } FOR_EACH_CHANNEL(i) { reg16 = 0; if ((s->spd_type == DDR3) && (i == 0)) reg16 = (0x3 << 12); - MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16); + mchbar16_unset_and_set(0x400*i + 0x59c, 0x3000, reg16); reg32 = 0; FOR_EACH_RANK_IN_CHANNEL(r) { @@ -740,8 +740,8 @@ reg32 |= 0x111 << r; } - MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32); - MCHBAR8_AND(0x400*i + 0x594, ~1); + mchbar32_unset_and_set(0x400*i + 0x59c, 0xfff, reg32); + mchbar8_unset(0x400*i + 0x594, 1); if (s->spd_type == DDR2) { if (!CHANNEL_IS_POPULATED(s->dimms, i)) { @@ -766,13 +766,13 @@ } else { die("Unhandled case\n"); } - MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000, + mchbar32_unset_and_set(0x400*i + 0x269, 0x000fffff, (u32)(reg8 << 24)); } else { /* DDR3 */ FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { - MCHBAR8_AND(0x400 * i + 0x5a0 + 3, - ~rank2clken[r + i * 4]); + mchbar8_unset(0x400 * i + 0x5a0 + 3, + rank2clken[r + i * 4]); } } @@ -780,24 +780,24 @@ } // END EACH CHANNEL if (s->spd_type == DDR2) { - MCHBAR8_OR(0x1a8, 1); - MCHBAR8_AND(0x1a8, ~0x4); + mchbar8_or(0x1a8, 1); + mchbar8_unset(0x1a8, 0x4); } else { /* DDR3 */ - MCHBAR8_AND(0x1a8, ~1); - MCHBAR8_OR(0x1a8, 0x4); + mchbar8_unset(0x1a8, 1); + mchbar8_or(0x1a8, 0x4); } // Update DLL timing - MCHBAR8_AND(0x1a4, ~0x80); - MCHBAR8_OR(0x1a4, 0x40); - MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400); + mchbar8_unset(0x1a4, 0x80); + mchbar8_or(0x1a4, 0x40); + mchbar16_unset_and_set(0x5f0, 0x400, 0x400); FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc); - MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc); - MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0, + mchbar16_unset_and_set(0x400*i + 0x5f0, 0x3fc, 0x3fc); + mchbar32_unset(0x400*i + 0x5fc, 0xcccccccc); + mchbar32_unset_and_set(0xfa0, 0x20002, s->spd_type == DDR2 ? 0x70 : 0x60); - MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff, + mchbar16_unset_and_set(0x400*ch + 0x5a0, 0xc440, s->spd_type == DDR2 ? 0x5555 : 0xa955); } @@ -833,12 +833,12 @@ } // XXX if not async mode - MCHBAR16_AND(0x180, ~0x8200); - MCHBAR8_OR(0x180, 0x4); + mchbar16_unset(0x180, 0x8200); + mchbar8_or(0x180, 0x4); j = 0; for (i = 0; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0xffffffff) { @@ -858,8 +858,8 @@ j = 0; i++; for (; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x4); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x4); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0) { @@ -868,8 +868,8 @@ } } for (; i < 16; i++) { - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; if (MCHBAR32(0x184) == 0xffffffff) { @@ -881,8 +881,8 @@ } } if (j < 2) { - MCHBAR8_AND(0x1c8, ~0x1f); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset(0x1c8, 0x1f); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; j = 2; @@ -890,7 +890,7 @@ } if (j < 2) { - MCHBAR8_AND(0x1c8, ~0x1f); + mchbar8_unset(0x1c8, 0x1f); async = 1; } @@ -917,7 +917,7 @@ break; } - MCHBAR8_AND(0x180, ~0x80); + mchbar8_unset(0x180, 0x80); if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz @@ -927,8 +927,8 @@ i = (i + 10) % 14; else /* DDR3 */ i = (i + 3) % 12; - MCHBAR8_AND_OR(0x1c8, ~0x1f, i); - MCHBAR8_OR(0x180, 0x10); + mchbar8_unset_and_set(0x1c8, 0x1f, i); + mchbar8_or(0x180, 0x10); while (MCHBAR8(0x180) & 0x10) ; } @@ -942,7 +942,7 @@ MCHBAR8(0x188) = reg8; if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) - MCHBAR8_OR(0x18c, 1); + mchbar8_or(0x18c, 1); } static void select_default_dq_dqs_settings(struct sysinfo *s) @@ -1091,65 +1091,65 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { for (j = 0; j < 6; j++) { if (j == 0) { - MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000, + mchbar32_unset_and_set(0x400*i + addr[j], 0xff000, 0xaa000); - MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, + mchbar32_unset_and_set(C0DQSDQRyTX3(rank), ((1 << (dqs * 2 + 17)) | (1 << (dqs * 2 + 16))), 0x6666); for (k = 0; k < 8; k++) { - MCHBAR32_AND_OR(0x400*i + addr[j] + + mchbar32_unset_and_set(0x400*i + addr[j] + 0xe + (k << 2), - ~0x3f3f3f3f, x32a[k]); - MCHBAR32_AND_OR(0x400*i + addr[j] + + 0x3f3f3f3f, x32a[k]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x2e + (k << 2), - ~0x3f3f3f3f, x32a[k]); + 0x3f3f3f3f, x32a[k]); } } else { - MCHBAR16_AND_OR(0x400*i + addr[j], - ~0xf000, 0xa000); - MCHBAR16_AND_OR(0x400*i + addr[j] + 4, - ~0xffff, x378[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe, - ~0x3f3f3f3f, x382[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12, - ~0x3f3f3f3f, x386[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16, - ~0x3f3f3f3f, x38a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a, - ~0x3f3f3f3f, x38e[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e, - ~0x3f3f3f3f, x392[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22, - ~0x3f3f3f3f, x396[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26, - ~0x3f3f3f3f, x39a[j]); - MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, - ~0x3f3f3f3f, x39e[j]); + mchbar16_unset_and_set(0x400*i + addr[j], + 0xf000, 0xa000); + mchbar16_unset_and_set(0x400*i + addr[j] + 4, + 0xffff, x378[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0xe, + 0x3f3f3f3f, x382[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x12, + 0x3f3f3f3f, x386[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x16, + 0x3f3f3f3f, x38a[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x1a, + 0x3f3f3f3f, x38e[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x1e, + 0x3f3f3f3f, x392[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x22, + 0x3f3f3f3f, x396[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x26, + 0x3f3f3f3f, x39a[j]); + mchbar32_unset_and_set(0x400*i + addr[j] + 0x2a, + 0x3f3f3f3f, x39e[j]); } if (s->spd_type == DDR3 && BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { - MCHBAR16_AND_OR(0x378 + 0x400 * i, - ~0xffff, 0xcccc); + mchbar16_unset_and_set(0x378 + 0x400 * i, + 0xffff, 0xcccc); } - MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]); + mchbar8_unset_and_set(0x400*i + addr[j], 1, bit[j]); } reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36; - MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8); - MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x45a, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x45e, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x462, 0x3f, reg8); + mchbar8_unset_and_set(0x400*i + 0x466, 0x3f, reg8); } // END EACH POPULATED CHANNEL - MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00); - MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff); + mchbar32_unset_and_set(0x134, 0x63c00, 0x63c00); + mchbar16_unset_and_set(0x174, 0x63ff, 0x63ff); MCHBAR16(0x178) = 0x0135; - MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0); + mchbar32_unset_and_set(0x130, 0x7bdffe0, 0x7a9ffa0); if (!CHANNEL_IS_POPULATED(s->dimms, 0)) - MCHBAR32_AND(0x130, ~(1 << 27)); + mchbar32_unset(0x130, (1 << 27)); if (!CHANNEL_IS_POPULATED(s->dimms, 1)) - MCHBAR32_AND(0x130, ~(1 << 28)); + mchbar32_unset(0x130, (1 << 28)); - MCHBAR8_OR(0x130, 1); + mchbar8_or(0x130, 1); } static void program_odt(struct sysinfo *s) @@ -1209,7 +1209,7 @@ reg16 &= ~0xfff; reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778); MCHBAR16(0x400*i + 0x29c) = reg16; - MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00); + mchbar32_unset_and_set(0x400*i + 0x260, 0x70e3c00, 0x3063c00); } } @@ -1242,8 +1242,8 @@ * by the SPD. */ /* Set rank 0-3 populated */ - MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000); - MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000); + mchbar32_unset_and_set(C0CKECTRL, 1, 0xf00000); + mchbar32_unset_and_set(C1CKECTRL, 1, 0xf00000); /* Set size of each rank to 128M */ MCHBAR16(C0DRA01) = 0x0101; MCHBAR16(C0DRA23) = 0x0101; @@ -1259,7 +1259,7 @@ /* In stacked mode the last present rank on ch1 needs to have its size doubled in c1drbx */ MCHBAR16(C1DRB3) = 0x0010; - MCHBAR8_OR(0x111, STACKED_MEM); + mchbar8_or(0x111, STACKED_MEM); MCHBAR32(0x104) = 0; MCHBAR16(0x102) = 0x400; MCHBAR8(0x110) = (2 << 5) | (3 << 3); @@ -1305,8 +1305,8 @@ data8 = (u8)mirror_shift_bit(data8, 4); } - MCHBAR8_AND_OR(0x271, ~0x3e, data8); - MCHBAR8_AND_OR(0x671, ~0x3e, data8); + mchbar8_unset_and_set(0x271, 0x3e, data8); + mchbar8_unset_and_set(0x671, 0x3e, data8); data32 = val; if (s->spd_type == DDR3 && (r & 1) && s->dimms[ch * 2 + (r >> 1)].mirrored) { @@ -1318,8 +1318,8 @@ read32((void *)((data32 | addr))); udelay(10); - MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD); - MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD); + mchbar8_unset_and_set(0x271, 0x3e, NORMALOP_CMD); + mchbar8_unset_and_set(0x671, 0x3e, NORMALOP_CMD); } static void jedec_ddr2(struct sysinfo *s) @@ -1545,22 +1545,22 @@ MCHBAR32(0x208) = c0dra; MCHBAR32(0x608) = c1dra; - MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0); - MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0); + mchbar8_unset_and_set(0x262, 0xf0, (rankpop0 << 4) & 0xf0); + mchbar8_unset_and_set(0x662, 0xf0, (rankpop1 << 4) & 0xf0); if (s->spd_type == DDR3) { FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { /* ZQCAL enable */ - MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26); + mchbar32_or(0x269 + 0x400 * ch, 1 << 26); } } if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) - MCHBAR8_OR(0x260, 1); + mchbar8_or(0x260, 1); if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) - MCHBAR8_OR(0x660, 1); + mchbar8_or(0x660, 1); // DRB lastrank_ch1 = 0; @@ -1604,10 +1604,10 @@ size_me = ME_UMA_SIZEMB; if (s->stacked_mode) { - MCHBAR8_OR(0x111, STACKED_MEM); + mchbar8_or(0x111, STACKED_MEM); } else { - MCHBAR8_AND(0x111, ~STACKED_MEM); - MCHBAR8_OR(0x111, 1 << 4); + mchbar8_unset(0x111, STACKED_MEM); + mchbar8_or(0x111, 1 << 4); } if (s->stacked_mode) { @@ -1623,7 +1623,7 @@ /* Set ME UMA size in MiB */ MCHBAR16(0x100) = size_me; /* Set ME UMA Present bit */ - MCHBAR32_OR(0x111, 1); + mchbar32_or(0x111, 1); } dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2; } @@ -1753,21 +1753,21 @@ MCHBAR32(0xfbc) = 0xf; MCHBAR32(0xfc4) = 0xfe22244; MCHBAR8(0x12f) = 0x5c; - MCHBAR8_OR(0xfb0, 1); + mchbar8_or(0xfb0, 1); if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz) - MCHBAR8_OR(0x12f, 0x2); + mchbar8_or(0x12f, 0x2); else - MCHBAR8_AND(0x12f, ~0x2); - MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0); + mchbar8_unset(0x12f, 0x2); + mchbar8_unset_and_set(0x6c0, 0xf0, 0xa0); MCHBAR32(0xfa8) = 0x30d400; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR8_OR(0x400*ch + 0x26c, 1); + mchbar8_or(0x400*ch + 0x26c, 1); MCHBAR32(0x400*ch + 0x278) = 0x88141881; MCHBAR16(0x400*ch + 0x27c) = 0x0041; MCHBAR8(0x400*ch + 0x292) = 0xf2; - MCHBAR16_OR(0x400*ch + 0x272, 0x100); - MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1); + mchbar16_or(0x400*ch + 0x272, 0x100); + mchbar8_unset_and_set(0x400*ch + 0x243, 0x2, 1); MCHBAR32(0x400*ch + 0x288) = 0x8040200; MCHBAR32(0x400*ch + 0x28c) = 0xff402010; MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; @@ -1775,7 +1775,7 @@ reg8 = pci_read_config8(HOST_BRIDGE, 0xf0); pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1); - MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk == + mchbar8_unset_and_set(0x400*i + 0x5d9, 0xf0, 0x2 | (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz ? 0x20000 : 0)); reg32 = 0x219100c2; if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) { @@ -1785,7 +1785,7 @@ } else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) { reg32 &= ~0x10000; } - MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32); + mchbar32_unset_and_set(0xfa4, 0x219100c3, reg32); reg32 = 0x44a00; switch (s->selected_timings.fsb_clk) { case FSB_CLOCK_1333MHz: @@ -1811,7 +1811,7 @@ reg32 = 0x8f038000; if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) reg32 &= ~0x4000000; - MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32); + mchbar32_unset_and_set(0x40, 0x8f038000, reg32); reg32 = 0x00013001; if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz) reg32 |= 0x20000; @@ -1884,50 +1884,50 @@ MCHBAR32(0x14) = 0x0010691f; MCHBAR32(0x18) = 0xdf6437f7; MCHBAR32(0x1c) = 0x0; - MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000); - MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000); + mchbar32_unset_and_set(0x24, 0xe0000000, 0x60000000); + mchbar32_unset_and_set(0x44, 0x1fef0000, 0x6b0000); MCHBAR16(0x115) = (u16) reg1; - MCHBAR32_AND_OR(0x117, ~0xffffff, reg2); + mchbar32_unset_and_set(0x117, 0xffffff, reg2); MCHBAR8(0x124) = 0x7; // not sure if dummy reads are needed - MCHBAR16_AND_OR(0x12a, 0, 0x80); - MCHBAR8_AND_OR(0x12c, 0, 0xa0); - MCHBAR16_AND(0x174, ~(1 << 15)); - MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00); - MCHBAR8_AND(0x18c, ~0x8); - MCHBAR8_OR(0x192, 1); - MCHBAR8_OR(0x193, 0xf); - MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80); - MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii + mchbar16_unset_and_set(0x12a, 0xffff, 0x80); + mchbar8_unset_and_set(0x12c, 0xff, 0xa0); + mchbar16_unset(0x174, (1 << 15)); + mchbar16_unset_and_set(0x188, 0x1f00, 0x1f00); + mchbar8_unset(0x18c, 0x8); + mchbar8_or(0x192, 1); + mchbar8_or(0x193, 0xf); + mchbar16_unset_and_set(0x1b4, 0x480, 0x80); + mchbar16_unset_and_set(0x210, 0x1fff, 0x3f); // | clockgatingiii // non-aligned access: possible bug? - MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate); - MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f); - MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0); - MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70); + mchbar32_unset_and_set(0x6d1, 0xff03ff, 0x100 | clkgate); + mchbar8_unset_and_set(0x212, 0x7f, 0x7f); + mchbar32_unset_and_set(0x2c0, 0xffff0, 0xcc5f0); + mchbar8_unset_and_set(0x2c4, 0x70, 0x70); // non-aligned access: possible bug? - MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi + mchbar32_unset_and_set(0x2d1, 0xffffff, 0xff2831); // | clockgatingi MCHBAR32(0x2d4) = 0x40453600; MCHBAR32(0x300) = 0xc0b0a08; MCHBAR32(0x304) = 0x6040201; - MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405); + mchbar32_unset_and_set(0x30c, 0x43c0f, 0x41405); MCHBAR16(0x610) = reg3; MCHBAR16(0x612) = reg4; - MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000); + mchbar32_unset_and_set(0x62c, 0xc000000, 0x4000000); MCHBAR32(0xae4) = 0; - MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000); + mchbar32_unset_and_set(0xc00, 0xf0000, 0x10000); MCHBAR32(0xf00) = 0x393a3b3c; MCHBAR32(0xf04) = 0x3d3e3f40; MCHBAR32(0xf08) = 0x393a3b3c; MCHBAR32(0xf0c) = 0x3d3e3f40; - MCHBAR32_AND(0xf18, ~0xfff00001); + mchbar32_unset(0xf18, 0xfff00001); MCHBAR32(0xf48) = 0xfff0ffe0; MCHBAR32(0xf4c) = 0xffc0ff00; MCHBAR32(0xf50) = 0xfc00f000; MCHBAR32(0xf54) = 0xc0008000; - MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000); - MCHBAR32_AND(0xfac, ~0x80000000); - MCHBAR32_AND(0xfb8, ~0xff000000); - MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000); + mchbar32_unset_and_set(0xf6c, 0xffff0000, 0xffff0000); + mchbar32_unset(0xfac, 0x80000000); + mchbar32_unset(0xfb8, 0xff000000); + mchbar32_unset_and_set(0xfbc, 0x7f800, 0xf000); MCHBAR32(0x1104) = 0x3003232; MCHBAR32(0x1108) = 0x74; if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) @@ -1943,31 +1943,31 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { MCHBAR8(0x400*ch + 0x239) = twl + 15; MCHBAR16(0x400*ch + 0x23c) = x23c; - MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033); - MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16); + mchbar32_unset_and_set(0x400*ch + 0x248, 0x706033, 0x406033); + mchbar32_unset_and_set(0x400*ch + 0x260, (1 << 16), 1 << 16); MCHBAR8(0x400*ch + 0x264) = x264; - MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592); - MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e); + mchbar8_unset_and_set(0x400*ch + 0x592, 0x3f, 0x3c & x592); + mchbar8_unset_and_set(0x400*ch + 0x593, 0x1f, 0x1e); } for (lane = 0; lane < 8; lane++) - MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3)); + mchbar8_unset(0x561 + (lane << 2), (1 << 3)); } static void software_ddr3_reset(struct sysinfo *s) { printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); - MCHBAR8_OR(0x1a8, 0x02); - MCHBAR8_AND(0x5da, ~0x80); - MCHBAR8_AND(0x1a8, ~0x02); - MCHBAR8_AND_OR(0x5da, ~0x03, 1); + mchbar8_or(0x1a8, 0x02); + mchbar8_unset(0x5da, 0x80); + mchbar8_unset(0x1a8, 0x02); + mchbar8_unset_and_set(0x5da, 0x03, 1); udelay(200); - MCHBAR8_AND(0x1a8, ~0x02); - MCHBAR8_OR(0x5da, 0x80); - MCHBAR8_AND(0x5da, ~0x80); + mchbar8_unset(0x1a8, 0x02); + mchbar8_or(0x5da, 0x80); + mchbar8_unset(0x5da, 0x80); udelay(500); - MCHBAR8_OR(0x5da, 0x03); - MCHBAR8_AND(0x5da, ~0x03); + mchbar8_or(0x5da, 0x03); + mchbar8_unset(0x5da, 0x03); /* After write leveling the dram needs to be reset and reinitialised */ jedec_ddr3(s); } @@ -1984,16 +1984,16 @@ | PMSTS_BOTH_SELFREFRESH; // Clear host clk gate reg - MCHBAR32_OR(0x1c, 0xffffffff); + mchbar32_or(0x1c, 0xffffffff); // Select type if (s->spd_type == DDR2) - MCHBAR8_AND(0x1a8, ~0x4); + mchbar8_unset(0x1a8, 0x4); else - MCHBAR8_OR(0x1a8, 0x4); + mchbar8_or(0x1a8, 0x4); // Set freq - MCHBAR32_AND_OR(0xc00, ~0x70, + mchbar32_unset_and_set(0x400*i + 0x5a0, 0x3f000000, (s->selected_timings.mem_clk << 4) | (1 << 10)); // Overwrite freq if chipset rejects it @@ -2046,36 +2046,36 @@ // IOBUFACT if (CHANNEL_IS_POPULATED(s->dimms, 0)) { - MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); - MCHBAR8_OR(0x5d8, 0x7); + mchbar8_unset_and_set(0x5dd, 0x3f, 0x3f); + mchbar8_or(0x5d8, 0x7); } if (CHANNEL_IS_POPULATED(s->dimms, 1)) { if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) { - MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f); - MCHBAR8_OR(0x5d8, 1); + mchbar8_unset_and_set(0x5dd, 0x3f, 0x3f); + mchbar8_or(0x5d8, 1); } - MCHBAR8_OR(0x9dd, 0x3f); - MCHBAR8_OR(0x9d8, 0x7); + mchbar8_or(0x9dd, 0x3f); + mchbar8_or(0x9d8, 0x7); } /* DDR3 reset */ if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { printk(BIOS_DEBUG, "DDR3 Reset.\n"); - MCHBAR8_AND(0x1a8, ~0x2); - MCHBAR8_OR(0x5da, 0x80); + mchbar8_unset(0x1a8, 0x2); + mchbar8_or(0x5da, 0x80); udelay(500); - MCHBAR8_AND(0x1a8, ~0x2); - MCHBAR8_AND(0x5da, ~0x80); + mchbar8_unset(0x1a8, 0x2); + mchbar8_unset(0x5da, 0x80); udelay(500); } // Pre jedec - MCHBAR8_OR(0x40, 0x2); + mchbar8_or(0x40, 0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR32_OR(0x400*ch + 0x260, 1 << 27); + mchbar32_or(0x400*ch + 0x260, 1 << 27); } - MCHBAR16_OR(0x212, 0xf000); - MCHBAR16_OR(0x212, 0xf00); + mchbar16_or(0x212, 0xf000); + mchbar16_or(0x212, 0xf00); printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset @@ -2096,7 +2096,7 @@ } // After JEDEC reset - MCHBAR8_AND(0x40, ~0x2); + mchbar8_unset(0x40, 0x2); FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { reg32 = (2 << 18); reg32 |= post_jedec_tab[s->selected_timings.fsb_clk] @@ -2113,23 +2113,23 @@ [s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1] << 8; } - MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32); - MCHBAR8_AND(0x400*ch + 0x274, ~0x80); - MCHBAR8_OR(0x400*ch + 0x26c, 1); + mchbar32_unset_and_set(0x400*ch + 0x274, 0xfff00, reg32); + mchbar8_unset(0x400*ch + 0x274, 0x80); + mchbar8_or(0x400*ch + 0x26c, 1); MCHBAR32(0x400*ch + 0x278) = 0x88141881; MCHBAR16(0x400*ch + 0x27c) = 0x41; MCHBAR8(0x400*ch + 0x292) = 0xf2; - MCHBAR8_OR(0x400*ch + 0x271, 0xe); + mchbar8_or(0x400*ch + 0x271, 0xe); } - MCHBAR8_OR(0x2c4, 0x8); - MCHBAR8_OR(0x2c3, 0x40); - MCHBAR8_OR(0x2c4, 0x4); + mchbar8_or(0x2c4, 0x8); + mchbar8_or(0x2c3, 0x40); + mchbar8_or(0x2c4, 0x4); printk(BIOS_DEBUG, "Done post-jedec\n"); // Set DDR init complete FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { - MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000); + mchbar32_or(0x400*ch + 0x268, 0xc0000000); } // Dummy reads @@ -2147,14 +2147,14 @@ // Finish rcven FOR_EACH_CHANNEL(ch) { - MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x2); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x4); - MCHBAR8_OR(0x400*ch + 0x5d8, 0x8); + mchbar8_unset(0x400*ch + 0x5d8, 0xe); + mchbar8_or(0x400*ch + 0x5d8, 0x2); + mchbar8_or(0x400*ch + 0x5d8, 0x4); + mchbar8_or(0x400*ch + 0x5d8, 0x8); } - MCHBAR8_OR(0x5dc, 0x80); - MCHBAR8_AND(0x5dc, ~0x80); - MCHBAR8_OR(0x5dc, 0x80); + mchbar8_or(0x5dc, 0x80); + mchbar8_unset(0x5dc, 0x80); + mchbar8_or(0x5dc, 0x80); // XXX tRD @@ -2180,9 +2180,9 @@ printk(BIOS_DEBUG, "Done enhanced mode\n"); // Periodic RCOMP - MCHBAR16_AND_OR(0x160, ~0xfff, 0x999); - MCHBAR16_OR(0x1b4, 0x3000); - MCHBAR8_OR(0x130, 0x82); + mchbar16_unset_and_set(0x160, 0xfff, 0x999); + mchbar16_or(0x1b4, 0x3000); + mchbar8_or(0x130, 0x82); printk(BIOS_DEBUG, "Done PRCOMP\n"); // Power settings @@ -2197,11 +2197,11 @@ if (ME_UMA_SIZEMB != 0) { if (RANK_IS_POPULATED(s->dimms, 0, 0) || RANK_IS_POPULATED(s->dimms, 1, 0)) - MCHBAR8_OR(0xa2f, 1 << 0); + mchbar8_or(0xa2f, 1 << 0); if (RANK_IS_POPULATED(s->dimms, 0, 1) || RANK_IS_POPULATED(s->dimms, 1, 1)) - MCHBAR8_OR(0xa2f, 1 << 1); - MCHBAR32_OR(0xa30, 1 << 26); + mchbar8_or(0xa2f, 1 << 1); + mchbar32_or(0xa30, 1 << 26); } printk(BIOS_DEBUG, "Done raminit\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 58160b7..89165e0 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -41,16 +41,6 @@ * MCHBAR */ -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - #define CHDECMISC 0x111 #define STACKED_MEM (1 << 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89fe15143abcbb74abae6ebf126b219ed88b4153 Gerrit-Change-Number: 46279 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: nb/intel/haswell: Use common MCHBAR accessor functions
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45574 ) Change subject: nb/intel/haswell: Use common MCHBAR accessor functions ...................................................................... nb/intel/haswell: Use common MCHBAR accessor functions This change the binary using "BUILD_TIMELESS=1" for lenovo/t440p baord. Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/haswell/haswell_init.c M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 8 files changed, 19 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/45574/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 5f3debb..86c69f8 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -14,6 +14,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/name.h> #include <delay.h> +#include <northbridge/intel/common/mchbar_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <southbridge/intel/lynxpoint/pch.h> #include <cpu/intel/common/common.h> diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index b2fd530..8f9f33d 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -11,14 +11,17 @@ ramstage-y += acpi.c ramstage-y += minihd.c +ramstage-y += ../common/mchbar_ops.c romstage-y += memmap.c romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c +romstage-y += ../common/mchbar_ops.c smm-y += finalize.c +smm-y += ../common/mchbar_ops.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index cc4487c..81ed757 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" +#include <northbridge/intel/common/mchbar_ops.h> #include <southbridge/intel/lynxpoint/pch.h> unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b1fe430 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "haswell.h" diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index 93c89ce..ebce6e9 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "haswell.h" void intel_northbridge_haswell_finalize_smm(void) @@ -17,13 +19,13 @@ pci_or_config32(HOST_BRIDGE, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(HOST_BRIDGE, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1UL << 31); - MCHBAR32_OR(DMIVCLIM, 1UL << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_set(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_set(SAPMCTL, 1UL << 31); /* SA PM */ + mchbar32_set(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_set(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_set(REQLIM, 1UL << 31); + mchbar32_set(DMIVCLIM, 1UL << 31); + mchbar32_set(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 44ea9b9..5cacec6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -27,22 +27,8 @@ /* * MCHBAR + * As there are many registers, define them on a separate file */ - -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - -/* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e1c26d1..fd4a238 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -12,6 +12,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> +#include <northbridge/intel/common/mchbar_ops.h> #include "chip.h" #include "haswell.h" diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9c6c00f..f382db5 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -16,6 +16,8 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> +#include <northbridge/intel/common/mchbar_ops.h> + #include "raminit.h" #include "pei_data.h" #include "haswell.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/45574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15b7d122c3762e2dbbce283934f06db4166d1a9 Gerrit-Change-Number: 45574 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 23

Change in coreboot[master]: nb/i945: Drop unneeded loop
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40369 ) Change subject: nb/i945: Drop unneeded loop ...................................................................... nb/i945: Drop unneeded loop At sdram_power_management() function, MCHBAR32(UPMC3) bit 16 is already set. Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40369/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dad1cb2..4353a9c 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2147,7 +2147,6 @@ u16 reg16; u32 reg32; int integrated_graphics = pci_read_config16(PCI_DEV(0, 0x00, 0), GGC) & 2; - int i; reg32 = MCHBAR32(C0DRT2); reg32 &= 0xffffff00; @@ -2193,11 +2192,6 @@ MCHBAR32(UPMC3) = 0x000f06ff; - for (i = 0; i < 5; i++) { - MCHBAR32(UPMC3) &= ~(1 << 16); - MCHBAR32(UPMC3) |= (1 << 16); - } - MCHBAR32(GIPMC1) = 0x8000000c; reg16 = MCHBAR16(CPCTL); -- To view, visit https://review.coreboot.org/c/coreboot/+/40369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa53ceaa4fb9dd7868ea59a21d9bd11f3bf27b9 Gerrit-Change-Number: 40369 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 11

Change in coreboot[master]: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1)
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40370 ) Change subject: nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) ...................................................................... nb/i945: Rewrite peg_bits for MCHBAR16(UPMC1) Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 5 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/40370/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4353a9c..bb886d4 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2171,18 +2171,14 @@ MCHBAR32(C1DRC1) = reg32; if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { - if (i945_silicon_revision() > 1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = MCHBAR16(UPMC1); + peg_bits &= ((1 << 5) | (1 << 0)); + if (i945_silicon_revision() > 1) MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); - + else /* Rev 0 and 1 */ MCHBAR16(UPMC1) = 0x0010 | peg_bits; - } } reg16 = MCHBAR16(UPMC2); -- To view, visit https://review.coreboot.org/c/coreboot/+/40370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9e848077cdd13158dbfd19326b95b42fc1c1fb Gerrit-Change-Number: 40370 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45273 ) Change subject: nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax ...................................................................... nb/intel/i945/acpi: COnvert igd.asl to ASL+ Syntax Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/acpi/igd.asl 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45273/1 diff --git a/src/northbridge/intel/i945/acpi/igd.asl b/src/northbridge/intel/i945/acpi/igd.asl index 5258c52..43662d1 100644 --- a/src/northbridge/intel/i945/acpi/igd.asl +++ b/src/northbridge/intel/i945/acpi/igd.asl @@ -28,7 +28,7 @@ Method (XBCM, 1, NotSerialized) { - Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC) + ^^DSPC.BRTC = ((Arg0 << 0x04) | 0x0F) #ifdef SMI_SAVE_CMOS Trap(SMI_SAVE_CMOS) #endif @@ -36,8 +36,8 @@ Method (XBQC, 0, NotSerialized) { - Store (^^DSPC.BRTC, Local0) - ShiftRight (Local0, 4, Local0) + Local0 = ^^DSPC.BRTC + Local0 >>= 4 Return (Local0) } #include <drivers/intel/gma/acpi/common.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/45273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0c3063b5a448fee4bcf283e56e7dc2008edcf7c Gerrit-Change-Number: 45273 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
by HAOUAS Elyes (Code Review) 17 Feb '21

17 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46281 ) Change subject: nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ...................................................................... nb/intel/ironlake: Get rid of MCHBARxx_{AND_OR,AND,OR} macros Change-Id: If8f30f558c422d1168efd218759a406b26338ef5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/ironlake/finalize.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/ironlake/raminit.c 3 files changed, 103 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46281/1 diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 88bc98d..6b91965 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -4,13 +4,13 @@ void intel_ironlake_finalize_smm(void) { - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1 << 31); - MCHBAR32_OR(0x7000, 1 << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + mchbar32_or(0x5500, 1 << 0); /* PAVP */ + mchbar32_or(0x5f00, 1 << 31); /* SA PM */ + mchbar32_or(0x6020, 1 << 0); /* UMA GFX */ + mchbar32_or(0x63fc, 1 << 0); /* VTDTRK */ + mchbar32_or(0x6800, 1 << 31); + mchbar32_or(0x7000, 1 << 31); + mchbar32_or(0x77fc, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(0x50fc) = 0x8f; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index b9e5322..4d30500 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -98,19 +98,6 @@ #define MSAC 0x62 /* Multi Size Aperture Control */ /* - * MCHBAR - */ - -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -/* * EPBAR - Egress Port Root Complex Register Block */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 05323f1..fe20c8c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -323,10 +323,10 @@ MCHBAR8(0x5ff) = 0x0; MCHBAR8(0x5ff) = 0x80; MCHBAR32(0x580 + (channel << 10)) = 0x8493c012 | addr; - MCHBAR8_OR(0x580 + (channel << 10), 1); + mchbar8_or(0x580 + (channel << 10), 1); while (!((ret = MCHBAR32(0x580 + (channel << 10))) & 0x10000)) ; - MCHBAR8_AND(0x580 + (channel << 10), ~1); + mchbar8_unset(0x580 + (channel << 10), 1); return ret; } @@ -478,7 +478,7 @@ } } - MCHBAR32_OR(0x130, 1); + mchbar32_or(0x130, 1); while (MCHBAR8(0x130) & 1) ; } @@ -1235,7 +1235,7 @@ if (MCHBAR8(0x2ca9) & 1) some_delay_3_half_cycles = 3; for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_OR(0x220 + (channel << 10), 0x18001117); + mchbar32_or(0x220 + (channel << 10), 0x18001117); MCHBAR32(0x224 + (channel << 10)) = (info->max_slots_used_in_channel - 1) | ((info->cas_latency - 5 - info->clock_speed_index) @@ -1258,7 +1258,7 @@ MCHBAR8(0x267 + (channel << 10)) = 0x4; MCHBAR16(0x272 + (channel << 10)) = 0x155; - MCHBAR32_AND_OR(0x2bc + (channel << 10), 0xFF000000, 0x707070); + mchbar32_unset_and_set(0x2bc + (channel << 10), 0x00ffffff, 0x707070); write_500(info, channel, ((!info->populated_ranks[channel][1][1]) @@ -1332,8 +1332,8 @@ MCHBAR16(0x610) = (MIN(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) | (MCHBAR16(0x610) & 0x1C3) | 0x3C; - MCHBAR16_OR(0x612, 0x100); - MCHBAR16_OR(0x214, 0x3E00); + mchbar16_or(0x612, 0x100); + mchbar16_or(0x214, 0x3E00); for (i = 0; i < 8; i++) { pci_write_config32(QPI_SAD, SAD_DRAM_RULE(i), (info->total_memory_mb - 64) | !i | 2); @@ -2227,7 +2227,7 @@ write_1d0(reg1b3 ^ 32, 0x1b3, 6, 1); write_1d0(reg1b3 ^ 32, 0x1a3, 6, 1); failmask = check_testing(info, total_rank, 0); - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); do_fsm(state, count, failmask, 5, 47, lower_usable, upper_usable, reg1b3); } @@ -2292,7 +2292,7 @@ check_testing_type2(info, total_rank, 3, i, 1); } - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -2393,7 +2393,7 @@ 1); } - MCHBAR32_OR(0xfb0, 0x00030000); + mchbar32_or(0xfb0, 0x00030000); for (lane = 0; lane < 8; lane++) { if (num_successfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { @@ -3520,8 +3520,8 @@ 2 * info->cas_latency - 7 + 11); delay_d_ps += info->revision >= 8 ? 2758 : 4428; - MCHBAR32_AND_OR(0x140, 0xfaffffff, 0x2000000); - MCHBAR32_AND_OR(0x138, 0xfaffffff, 0x2000000); + mchbar32_unset_and_set(0x140, 0x05000000, 0x2000000); + mchbar32_unset_and_set(0x138, 0x05000000, 0x2000000); if ((MCHBAR8(0x144) & 0x1f) > 0x13) delay_d_ps += 650; delay_c_ps = delay_d_ps + 1800; @@ -3580,9 +3580,9 @@ info->training.reg274265[channel][2] << 8; } if (info->training.reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); } static void restore_274265(struct raminfo *info) @@ -3597,9 +3597,9 @@ info->cached_training->reg274265[channel][2] << 8; } if (info->cached_training->reg2ca9_bit0) - MCHBAR8_OR(0x2ca9, 1); + mchbar8_or(0x2ca9, 1); else - MCHBAR8_AND(0x2ca9, ~1); + mchbar8_unset(0x2ca9, 1); } static void dmi_setup(void) @@ -3607,7 +3607,7 @@ gav(DMIBAR8(0x254)); DMIBAR8(0x254) = 0x1; DMIBAR16(0x1b8) = 0x18f2; - MCHBAR16_AND_OR(0x48, 0, 0x2); + mchbar16_unset_and_set(0x48, 0xffff, 0x2); DMIBAR32(0xd68) |= 0x08000000; @@ -3634,7 +3634,7 @@ MCHBAR16(0x1170) = 0xa880; MCHBAR8(0x11c1) = 0x1; MCHBAR16(0x1170) = 0xb880; - MCHBAR8_AND_OR(0x1210, 0, 0x84); + mchbar8_unset_and_set(0x1210, 0xff, 0x84); if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { /* 0 for 32MB */ @@ -3651,9 +3651,9 @@ if (deven & 8) { MCHBAR8(0x2c30) = 0x20; pci_read_config8(NORTHBRIDGE, 0x8); // = 0x18 - MCHBAR16_OR(0x2c30, 0x200); + mchbar16_or(0x2c30, 0x200); MCHBAR16(0x2c32) = 0x434; - MCHBAR32_AND_OR(0x2c44, 0, 0x1053687); + mchbar32_unset_and_set(0x2c44, 0xffffffff, 0x1053687); pci_read_config8(GMA, MSAC); // = 0x2 pci_write_config8(GMA, MSAC, 0x2); read8(DEFAULT_RCBA + 0x2318); @@ -3662,7 +3662,7 @@ write8(DEFAULT_RCBA + 0x2320, 0xfc); } - MCHBAR32_AND_OR(0x30, 0, 0x40); + mchbar32_unset_and_set(0x30, 0xffffffff, 0x40); pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); @@ -3815,7 +3815,7 @@ /* after SPD */ timestamp_add_now(102); - MCHBAR8_AND(0x2ca8, 0xfc); + mchbar8_unset(0x2ca8, 3); collect_system_info(&info); calculate_timings(&info); @@ -3851,9 +3851,9 @@ MCHBAR16(0x2c20) = 0x10; } - MCHBAR32_OR(0x18b4, 0x210000); - MCHBAR32_OR(0x1890, 0x2000000); - MCHBAR32_OR(0x18b4, 0x8000); + mchbar32_or(0x18b4, 0x210000); + mchbar32_or(0x1890, 0x2000000); + mchbar32_or(0x18b4, 0x8000); gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!! pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12); @@ -3861,10 +3861,10 @@ gav(MCHBAR16(0x2c10)); MCHBAR16(0x2c10) = 0x412; gav(MCHBAR16(0x2c10)); - MCHBAR16_OR(0x2c12, 0x100); + mchbar16_or(0x2c12, 0x100); gav(MCHBAR8(0x2ca8)); // !!!! - MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080); + mchbar32_unset_and_set(0x1804, 0x00000003, 0x8400080); pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0); @@ -3872,7 +3872,7 @@ gav(MCHBAR32(0x1804)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); + mchbar8_or(0x2ca8, 1); } MCHBAR32(0x18d8) = 0x120000; @@ -3894,13 +3894,13 @@ gav(MCHBAR32(0x18dc)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } MCHBAR32(0x188c) = 0x20bc09; pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09); MCHBAR32(0x1a10) = 0x4200010e; - MCHBAR32_OR(0x18b8, 0x200); + mchbar32_or(0x18b8, 0x200); gav(MCHBAR32(0x1918)); // !!!! MCHBAR32(0x1918) = 0x332; @@ -3910,17 +3910,17 @@ MCHBAR32(0x182c) = 0x10202; gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!! pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202); - MCHBAR32_AND(0x1a1c, 0x8fffffff); - MCHBAR32_OR(0x1a70, 0x100000); + mchbar32_unset(0x1a1c, 0x70000000); + mchbar32_or(0x1a70, 0x100000); - MCHBAR32_AND(0x18b4, 0xffff7fff); + mchbar32_unset(0x18b4, 0x00008000); gav(MCHBAR32(0x1a68)); // !!!! MCHBAR32(0x1a68) = 0x343800; gav(MCHBAR32(0x1e68)); // !!!! gav(MCHBAR32(0x1a68)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!! @@ -3936,7 +3936,7 @@ gav(MCHBAR32(0x1af0)); // !!!! if (x2ca8 == 0) { - MCHBAR8_OR(0x2ca8, 1); // guess + mchbar8_or(0x2ca8, 1); // guess } gav(MCHBAR32(0x1890)); // !!!! @@ -3974,14 +3974,14 @@ set_2dxx_series(&info, s3resume); if (!(deven & 8)) { - MCHBAR32_AND_OR(0x2cb0, 0, 0x40); + mchbar32_unset_and_set(0x2cb0, 0xffffffff, 0x40); } udelay(1000); if (deven & 8) { - MCHBAR32_OR(0xff8, 0x1800); - MCHBAR32_AND(0x2cb0, 0x00); + mchbar32_or(0xff8, 0x1800); + mchbar32_unset(0x2cb0, 0xffffffff); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c); pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e); @@ -4040,11 +4040,11 @@ MCHBAR16(0x11c0) = 0xc40b; MCHBAR16(0x11c2) = 0x303; MCHBAR16(0x11c4) = 0x301; - MCHBAR32_AND_OR(0x1190, 0, 0x8900080a); + mchbar32_unset_and_set(0x1190, 0xffffffff, 0x8900080a); MCHBAR32(0x11b8) = 0x70c3000; MCHBAR8(0x11ec) = 0xa; MCHBAR16(0x1100) = 0x800; - MCHBAR32_AND_OR(0x11bc, 0, 0x1e84800); + mchbar32_unset_and_set(0x11bc, 0xffffffff, 0x1e84800); MCHBAR16(0x11ca) = 0xfa; MCHBAR32(0x11e4) = 0x4e20; MCHBAR8(0x11bc) = 0xf; @@ -4078,8 +4078,8 @@ if ((deven & 8) && x2ca8 == 0) { MCHBAR16(0x1214) = 0x320; MCHBAR32(0x1600) = 0x40000000; - MCHBAR32_AND_OR(0x11f4, 0, 0x10000000); - MCHBAR16_AND_OR(0x1230, 0, 0x8000); + mchbar32_unset_and_set(0x11f4, 0xffffffff, 0x10000000); + mchbar16_unset_and_set(0x1230, 0xffff, 0x8000); MCHBAR32(0x1400) = 0x13040020; MCHBAR32(0x1404) = 0xe090120; MCHBAR32(0x1408) = 0x5120220; @@ -4176,14 +4176,14 @@ MCHBAR16(0x1220) = 0x1388; } - MCHBAR32_AND_OR(0x2c80, 0, 0x1053688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x1053688); // !!!! MCHBAR32(0x1c04); // !!!! MCHBAR32(0x1804) = 0x406080; MCHBAR8(0x2ca8); if (x2ca8 == 0) { - MCHBAR8_AND(0x2ca8, ~3); + mchbar8_unset(0x2ca8, 3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? /* This issues a CPU reset without resetting the platform */ printk(BIOS_DEBUG, "Issuing a CPU reset\n"); @@ -4192,12 +4192,12 @@ if (s3resume) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (SLP_TYP_S3 << 10)); - MCHBAR32_OR(0x1af0, 0x10); + mchbar32_or(0x1af0, 0x10); halt(); } MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); - MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! + mchbar32_unset_and_set(0x2c80, 0xffffffff, 0x53688); // !!!! pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! @@ -4214,8 +4214,8 @@ MCHBAR16(0x616) = 0x26a; MCHBAR32(0x134) = 0x856000; MCHBAR32(0x160) = 0x5ffffff; - MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!! - MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!! + mchbar32_unset_and_set(0x114, 0xffffffff, 0xc2024440); // !!!! + mchbar32_unset_and_set(0x118, 0xffffffff, 0x4); // !!!! for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x260 + (channel << 10)) = 0x30809ff | ((info.populated_ranks_mask[channel] & 3) << 20); @@ -4256,7 +4256,7 @@ program_base_timings(&info); - MCHBAR8_OR(0x5ff, 0x80); + mchbar8_or(0x5ff, 0x80); write_1d0(0x2, 0x1d5, 2, 1); write_1d0(0x20, 0x166, 7, 1); @@ -4304,9 +4304,9 @@ write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1); } - MCHBAR32_AND_OR(0x1f4, 0, 0x20000); // !!!! + mchbar32_unset_and_set(0x1f4, 0xffffffff, 0x20000); // !!!! MCHBAR32(0x1f0) = 0x1d000200; - MCHBAR8_AND_OR(0x1f0, 0, 0x1); // !!!! + mchbar8_unset_and_set(0x1f0, 0xff, 0x1); // !!!! MCHBAR8(0x1f0); // !!!! program_board_delay(&info); @@ -4315,7 +4315,7 @@ MCHBAR8(0x5ff) = 0x80; MCHBAR8(0x5f4) = 0x1; - MCHBAR32_AND(0x130, 0xfffffffd); // | 2 when ? + mchbar32_unset(0x130, 2); // | 2 when ? while (MCHBAR32(0x130) & 1) ; gav(read_1d0(0x14b, 7)); // = 0x81023100 @@ -4335,10 +4335,10 @@ write_1d0(0, 0xae, 6, 1); read_1d0(0x300, 4); // = 0x48088080 // !!!! write_1d0(0, 0x300, 6, 1); - MCHBAR16_AND_OR(0x356, 0, 0x1040); // !!!! - MCHBAR16_AND_OR(0x756, 0, 0x1040); // !!!! - MCHBAR32_AND(0x140, ~0x07000000); - MCHBAR32_AND(0x138, ~0x07000000); + mchbar16_unset_and_set(0x356, 0xffff, 0x1040); // !!!! + mchbar16_unset_and_set(0x756, 0xffff, 0x1040); // !!!! + mchbar32_unset(0x140, 0x07000000); + mchbar32_unset(0x138, 0x07000000); MCHBAR32(0x130) = 0x31111301; /* Wait until REG130b0 is 1. */ while (MCHBAR32(0x130) & 1) @@ -4404,13 +4404,13 @@ 1); write_500(&info, channel, 0x3, 0x69b, 2, 1); } - MCHBAR32_AND_OR(0x2d0, 0xff2c01ff, 0x200000); + mchbar32_unset_and_set(0x2d0, 0x00d3fe00, 0x200000); MCHBAR16(0x6c0) = 0x14a0; - MCHBAR32_AND_OR(0x6d0, 0xff0080ff, 0x8000); + mchbar32_unset_and_set(0x6d0, 0x00ff7f00, 0x8000); MCHBAR16(0x232) = 0x8; /* 0x40004 or 0 depending on ? */ - MCHBAR32_AND_OR(0x234, 0xfffbfffb, 0x40004); - MCHBAR32_AND_OR(0x34, 0xfffffffd, 5); + mchbar32_unset_and_set(0x234, 0x00040004, 0x40004); + mchbar32_unset_and_set(0x34, 0x00000002, 5); MCHBAR32(0x128) = 0x2150d05; MCHBAR8(0x12c) = 0x1f; MCHBAR8(0x12d) = 0x56; @@ -4422,10 +4422,10 @@ for (channel = 0; channel < NUM_CHANNELS; channel++) MCHBAR32(0x294 + (channel << 10)) = (info.populated_ranks_mask[channel] & 3) << 16; - MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000); - MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000); + mchbar32_unset_and_set(0x134, 0x03fe0000, 0x10000); + mchbar32_unset_and_set(0x134, 0x037a0000, 0x850000); for (channel = 0; channel < NUM_CHANNELS; channel++) - MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 | + mchbar32_unset_and_set(0x400*ch + 0x598, 0x18c00000, 0x8000000 | ((info.populated_ranks_mask[channel] & 3) << 20)); if (!s3resume) @@ -4443,8 +4443,8 @@ MCHBAR8(0x12c) = 0x9f; - MCHBAR8_AND_OR(0x271, 0, 0xe); // 2 // !!!! - MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!! + mchbar8_unset_and_set(0x271, 0xff, 0xe); // 2 // !!!! + mchbar8_unset_and_set(0x671, 0xff, 0xe); // !!!! if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -4455,7 +4455,7 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!! { u8 a, b; @@ -4492,7 +4492,7 @@ pci_write_config16(NORTHBRIDGE, 0xc8, 3); write_26c(0, 0x820); write_26c(1, 0x820); - MCHBAR32_OR(0x130, 2); + mchbar32_or(0x130, 2); /* end */ if (s3resume) { @@ -4504,10 +4504,10 @@ (info.populated_ranks[channel][0][1] << 5); MCHBAR32(0x29c + (channel << 10)) = 0x77a; } - MCHBAR32_AND_OR(0x2c0, 0, 0x6009cc00); // !!!! + mchbar32_unset_and_set(0x2c0, 0xffffffff, 0x6009cc00); // !!!! } - MCHBAR32_AND(0xfa4, ~0x01000002); + mchbar32_unset(0xfa4, 0x01000002); MCHBAR32(0xfb0) = 0x2000e019; /* Before training. */ @@ -4533,20 +4533,20 @@ else MCHBAR8(0x111) = 0x20 | (3 << 2) | (1 << 6) | (0 << 7); - MCHBAR32_AND(0xfac, ~0x80000000); + mchbar32_unset(0xfac, 0x80000000); MCHBAR32(0xfb4) = 0x4800; MCHBAR32(0xfb8) = (info.revision < 8) ? 0x20 : 0x0; MCHBAR32(0xe94) = 0x7ffff; MCHBAR32(0xfc0) = 0x80002040; MCHBAR32(0xfc4) = 0x701246; - MCHBAR8_AND(0xfc8, ~0x70); - MCHBAR32_OR(0xe5c, 0x1000000); - MCHBAR32_AND_OR(0x1a70, ~0x00100000, 0x00200000); + mchbar8_unset(0xfc8, 0x70); + mchbar32_or(0xe5c, 0x1000000); + mchbar32_unset_and_set(0x1a70, 0x00100000, 0x00200000); MCHBAR32(0x50) = 0x700b0; MCHBAR32(0x3c) = 0x10; MCHBAR8(0x1aa8) = (MCHBAR8(0x1aa8) & ~0x35) | 0xa; - MCHBAR8_OR(0xff4, 0x2); - MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020); + mchbar8_or(0xff4, 0x2); + mchbar32_unset_and_set(0xff8, 0xe008, 0x1020); MCHBAR32(0xd00) = IOMMU_BASE2 | 1; MCHBAR32(0xd40) = IOMMU_BASE1 | 1; @@ -4560,28 +4560,28 @@ u32 eax; eax = info.fsb_frequency / 9; - MCHBAR32_AND_OR(0xfcc, 0xfffc0000, + mchbar32_unset_and_set(0xfcc, 0x0003ffff, (eax * 0x280) | (eax * 0x5000) | eax | 0x40000); MCHBAR32(0x20) = 0x33001; } for (channel = 0; channel < NUM_CHANNELS; channel++) { - MCHBAR32_AND(0x220 + (channel << 10), ~0x7770); + mchbar32_unset(0x220 + (channel << 10), 0x7770); if (info.max_slots_used_in_channel == 1) - MCHBAR16_OR(0x237 + (channel << 10), 0x0201); + mchbar16_or(0x237 + (channel << 10), 0x0201); else - MCHBAR16_AND(0x237 + (channel << 10), ~0x0201); + mchbar16_unset(0x237 + (channel << 10), 0x0201); - MCHBAR8_OR(0x241 + (channel << 10), 1); + mchbar8_or(0x241 + (channel << 10), 1); if (info.clock_speed_index <= 1 && (info.silicon_revision == 2 || info.silicon_revision == 3)) - MCHBAR32_OR(0x248 + (channel << 10), 0x00102000); + mchbar32_or(0x248 + (channel << 10), 0x00102000); else - MCHBAR32_AND(0x248 + (channel << 10), ~0x00102000); + mchbar32_unset(0x248 + (channel << 10), 0x00102000); } - MCHBAR32_OR(0x115, 0x1000000); + mchbar32_or(0x115, 0x1000000); { u8 al; @@ -4605,7 +4605,7 @@ EPBAR32(EPVC1RCAP) = reg1c; // OK MCHBAR8(0xe08); // = 0x0 pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126 - MCHBAR8_OR(0x1210, 2); + mchbar8_or(0x1210, 2); MCHBAR32(0x1200) = 0x8800440; MCHBAR32(0x1204) = 0x53ff0453; MCHBAR32(0x1208) = 0x19002043; @@ -4613,10 +4613,10 @@ if (info.revision == 0x10 || info.revision == 0x11) { MCHBAR16(0x1214) = 0x220; - MCHBAR8_OR(0x1210, 0x40); + mchbar8_or(0x1210, 0x40); } - MCHBAR8_OR(0x1214, 0x4); + mchbar8_or(0x1214, 0x4); MCHBAR8(0x120c) = 0x1; MCHBAR8(0x1218) = 0x3; MCHBAR8(0x121a) = 0x3; @@ -4627,13 +4627,13 @@ /* revision dependent here. */ - MCHBAR16_OR(0x1230, 0x1f07); + mchbar16_or(0x1230, 0x1f07); if (info.uma_enabled) - MCHBAR32_OR(0x11f4, 0x10000000); + mchbar32_or(0x11f4, 0x10000000); - MCHBAR16_OR(0x1230, 0x8000); - MCHBAR8_OR(0x1214, 1); + mchbar16_or(0x1230, 0x8000); + mchbar8_or(0x1214, 1); u8 bl, ebpb; u16 reg_1020; @@ -4663,7 +4663,7 @@ MCHBAR8(0x123e) = (MCHBAR8(0x123e) & 0xf) | 0x60; if (reg_1020 != 0) { - MCHBAR32_AND_OR(0x123c, ~0x00900000, 0x600000); + mchbar32_unset_and_set(0x123c, 0x00900000, 0x600000); MCHBAR8(0x101c) = 0xb8; } @@ -4671,20 +4671,20 @@ if (info.uma_enabled) { u16 ax; - MCHBAR32_OR(0x11b0, 0x4000); - MCHBAR32_OR(0x11b4, 0x4000); - MCHBAR16_OR(0x1190, 0x4000); + mchbar32_or(0x11b0, 0x4000); + mchbar32_or(0x11b4, 0x4000); + mchbar16_or(0x1190, 0x4000); ax = MCHBAR16(0x1190) & 0xf00; // = 0x480a // OK MCHBAR16(0x1170) = ax | (MCHBAR16(0x1170) & 0x107f) | 0x4080; - MCHBAR16_OR(0x1170, 0x1000); + mchbar16_or(0x1170, 0x1000); udelay(1000); u16 ecx; for (ecx = 0xffff; ecx && (MCHBAR16(0x1170) & 0x1000); ecx--) ; - MCHBAR16_AND(0x1190, ~0x4000); + mchbar16_unset(0x1190, 0x4000); } pci_write_config8(SOUTHBRIDGE, GEN_PMCON_2, -- To view, visit https://review.coreboot.org/c/coreboot/+/46281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8f30f558c422d1168efd218759a406b26338ef5 Gerrit-Change-Number: 46281 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020