Change in coreboot[master]: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46283 )
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/1
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..5a394c6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -105,18 +105,18 @@ pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
/* Erratum workarounds */ - MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); + mchbar32_or(SAPMCTL, (1 << 9) | (1 << 10));
/* Enable SA Clock Gating */ - MCHBAR32_OR(SAPMCTL, 1); + mchbar32_or(SAPMCTL, 1);
/* GPU RC6 workaround for sighting 366252 */ - MCHBAR32_OR(SSKPD_HI, 1 << 31); + mchbar32_or(SSKPD_HI, 1 << 31);
/* VLW (Virtual Legacy Wire?) */ - MCHBAR32_AND(0x6120, ~(1 << 0)); + mchbar32_unset(0x6120, (1 << 0));
- MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); + mchbar32_or(INTRDIRCTL, (1 << 4) | (1 << 5)); }
static void start_peg_link_training(void) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 26c5306..1550253 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -18,13 +18,13 @@ pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
- MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar32_or(PAVP_MSG, 1 << 0); /* PAVP */ + mchbar32_or(SAPMCTL, 1 << 31); /* SA PM */ + mchbar32_or(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar32_or(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar32_or(REQLIM, 1 << 31); + mchbar32_or(DMIVCLIM, 1 << 31); + mchbar32_or(CRDTLCK, 1 << 0);
/* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 541bf73..db768a8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -359,10 +359,10 @@ * * FIXME: Never clock gate on Ivy Bridge stepping A0! */ - MCHBAR32_OR(PEGCTL, 1); + mchbar32_or(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } else { - MCHBAR32_AND(PEGCTL, ~1); + mchbar32_unset(PEGCTL, 1); } }
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..4c6c284 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -190,11 +190,11 @@ stretch = 3;
addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + mchbar32_unset_and_set(addr, 0x00003c00, (stretch << 12) | (stretch << 10)); printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + mchbar32_unset_and_set(addr, 0x000f0000, (stretch << 16) | (stretch << 18)); printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -254,7 +254,7 @@ MCHBAR32(TC_DTP_ch(channel)) = reg; }
- MCHBAR32_OR(addr, 0x00020000); + mchbar32_or(addr, 0x00020000);
dram_odt_stretch(ctrl, channel);
@@ -271,7 +271,7 @@ printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg;
- MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + mchbar32_or(TC_RFP_ch(channel), 0xff);
/* Self-refresh timing parameters */ reg = 0; @@ -652,19 +652,19 @@ MCHBAR32(MC_INIT_STATE_G) = reg;
/* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + mchbar32_unset(MC_INIT_STATE_G, 2);
/* Wait 200us */ udelay(200);
/* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + mchbar32_or(MC_INIT_STATE_G, 2);
/* Wait 500us */ udelay(500);
/* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + mchbar32_or(MC_INIT_STATE_G, 4);
/* XXX Wait 20ns */ udelay(1); @@ -957,10 +957,10 @@ }
/* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8);
FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x200000);
wait_for_iosav(channel);
@@ -2637,15 +2637,15 @@ int err;
FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + mchbar32_or(TC_RWP_ch(channel), 0x8000000);
FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); }
/* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2678,10 +2678,10 @@ wait_for_iosav(channel);
/* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + mchbar32_or(MC_INIT_STATE_G, 8);
FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + mchbar32_unset(SCHED_CBIT_ch(channel), 0x00200000); MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel);
@@ -2723,7 +2723,7 @@ printram("CPF\n");
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); }
FOR_ALL_POPULATED_CHANNELS { @@ -2747,7 +2747,7 @@ program_timings(ctrl, channel);
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar32_unset(IOSAV_By_BW_MASK_ch(channel, lane), 0xffffffff); } return 0; } @@ -2978,11 +2978,11 @@ iosav_run_once(channel);
wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x200000); }
/* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + mchbar32_unset(MC_INIT_STATE_G, 8); FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel);
@@ -3985,8 +3985,8 @@ FOR_ALL_POPULATED_CHANNELS {
/* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + mchbar32_unset_and_set(GDCRCMDDEBUGMUXCFG_Cz_S(channel), + 0x3f000000, rege3c_b24[i] << 24);
udelay(2);
@@ -4053,7 +4053,7 @@
FOR_ALL_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); }
@@ -4423,7 +4423,7 @@
FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + mchbar32_or(TC_RAP_ch(channel), 0x20000000); }
udelay(1); @@ -4463,7 +4463,7 @@ int channel; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + mchbar32_unset(TC_RAP_ch(channel), 0x20000000); } }
@@ -4487,7 +4487,7 @@ MCHBAR32(WMM_READ_CONFIG) = 0x46;
FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + mchbar32_unset_and_set(TC_OTHP_ch(channel), 0x00003000, 0x1000);
if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,14 +4522,14 @@ }
MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); - MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); + mchbar32_unset_and_set(MEM_TRML_THRESHOLDS_CONFIG, 0x00ffffff, 0x00e4d5d0); + mchbar32_unset(MEM_TRML_INTERRUPT, 0x1f);
FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + mchbar32_unset_and_set(TC_RFP_ch(channel), (3 << 16), 1 << 16);
- MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + mchbar32_or(MC_INIT_STATE_G, 1); + mchbar32_or(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa;
/* Find a populated channel */ @@ -4555,7 +4555,7 @@
/* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, + mchbar32_unset_and_set(SSKPD, 3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } @@ -4586,11 +4586,11 @@ }
FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + mchbar32_or(TC_RWP_ch(channel), 0x08000000);
FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + mchbar32_or(SCHED_CBIT_ch(channel), 0x00200000); }
printram("CPE\n"); @@ -4646,7 +4646,7 @@ MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0;
FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + mchbar32_unset(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f000000); udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index c86b524..217b186 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -50,16 +50,6 @@ * MCHBAR */
-#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) - /* As there are many registers, define them on a separate file */ #include "registers/mchbar.h" #include "registers/epbar.h"
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46283
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 47 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/3
HAOUAS Elyes has removed Angel Pons from this change. ( https://review.coreboot.org/c/coreboot/+/46283 )
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
Removed reviewer Angel Pons.
Patrick Georgi has uploaded a new patch set (#5) to the change originally created by HAOUAS Elyes. ( https://review.coreboot.org/c/coreboot/+/46283 )
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 36 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/5
Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46283
to look at the new patch set (#13).
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 36 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/13
Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46283
to look at the new patch set (#16).
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros
Change-Id: I39fe8195b849e8bcfa9d8ae6d4707aac5fb42d73 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 36 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46283/16
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46283 )
Change subject: nb/intel/sandybridge: Get rid of MCHBARxx_{AND_OR,AND,OR} macros ......................................................................
Abandoned
-
HAOUAS Elyes (Code Review) -
Patrick Georgi (Code Review)